JP2003234652A - Pll circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a PLL (phase-locked loop) circuit capable of holding the responsiveness of the PLL circuit and effectively using the band of the oscillation frequency characteristics of a VCO (voltage controlled oscillator). <P>SOLUTION: Clock signals 2s inputted from the outside of a device and an output clock 10s outputted from the VCO 9 are compared. Corresponding to the compared result, in the adjustment of the VCO 9, a maximum current 13s outputted from a maximum current generation circuit 13 is controlled and supplied to a frequency control DAC 6 and maximum frequency control signals 141s supplied from a system controller 14 and selected by a selector 80 are digital/analog converted. Also, the maximum current 13s outputted by the maximum current generation circuit 13 is adjusted by a maximum current gain adjustment circuit 83 and supplied to a phase control DAC 7 and maximum phase control signals 142s selected by a selector 81 are digital/analog converted. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL for extracting a clock from a reproduction signal of an optical disk or a magnetic disk.
The present invention relates to a circuit, and more particularly to a circuit having a configuration for optimizing a VCO gain in order to stabilize the characteristics of an output clock.

[0002]

2. Description of the Related Art With the recent development of digital technology, optical discs capable of recording digital information at high density are widely used. By the way, the signal itself read from this optical disc has a high strength (high and low) according to the recorded digital information, but since it is an analog signal as it is, it is necessary to correct the digital signal in order to process it.
Must be valued.

Therefore, a digital PLL (Phase-Phase-) which extracts a clock from the analog reproduction signal and samples it by an AD converter by using the extracted clock
Locked Loop) circuit is used. FIG. 12 shows a schematic configuration example of this PLL circuit. In FIG. 12, 20 is a PLL circuit main body. 1 is a reproduction signal input terminal,
1s is an input reproduction signal. A reproduction clock output terminal 3 outputs the reproduction clock 10s extracted from the reproduction signal 1s.

Reference numeral 4 is an AD converter, which receives the input reproduction signal 1s and converts it into a digital signal 4s. The internal processing is digitized. Reference numeral 5 denotes a phase comparator (first phase comparison means), which compares the sampling phases of the digitized reproduction signal 4s and the reproduction clock 10s output to the outside. 6
Is a frequency control DAC (digital / analog conversion), which converts the frequency control signal 51s, which is the output of the phase comparator 5, into an analog frequency control signal 6s.

Reference numeral 7 is a phase control DAC, and the phase comparator 5
The phase control signal 52s, which is the output of the above, is converted into the analog phase control signal 7s. Further, reference numeral 80 is a selector for input switching of the frequency control DAC 6, and 81 is a selector for switching input of the phase control DAC 7. Reference numeral 82 is an adder, which adds the output currents of the analog frequency control signal 6s and the analog phase control signal 7s and converts them into a voltage, and outputs a VCO oscillation control signal 82s.

A low pass filter 8 removes noise from the VCO oscillation control signal 82s. 9 is VCO (vo
The VCO oscillation control signal 8s from which noise is removed by the low-pass filter 8 is applied and output as an oscillation clock 9s. Reference numeral 10 denotes an M frequency divider, which receives the oscillation clock 9s of the VCO 9 and divides it by M. 10s is the divided clock signal which is the output. Further, 13 is a maximum current generating circuit, which is a frequency control DAC 6 and a phase control DAC 7.
The maximum current 13 s output by is given.

Reference numeral 14 denotes a system controller, which is a VC
In the O adjustment mode, the switching signal 143s is output to the two selectors 80 and 81, and the signals 141s and 142s from the system controller 14 are output from the output signal of the phase comparator 5.
And control signal 144s.
Is output to the maximum current generation circuit 13, and the frequency control DAC
6, and the current value 13s of the maximum current generation circuit 13 is adjusted so that the oscillation frequency when the VCO 9 is oscillated at the maximum oscillation frequency with the phase control DAC 7 at the maximum output. Further, in the normal operation mode after the adjustment of the VCO 9 is completed, the maximum current generating circuit 13 adjusted via the control signal 144s generates a constant maximum current 13s, and the switching signal 143s is changed to the two selectors 80 and 8.
1 and outputs the output signals 51s, 52 from the phase comparator 5.
Control to select s.

The operation of the conventional PLL circuit thus constructed will be described. Here, it is assumed that the reproduction signal 1s is an analog (reproduction) signal that has been reproduced from an optical disk (not shown) before binarization. The reproduction clock 10s is a reproduction clock extracted from the reproduction signal 1s, and this reproduction clock 10s is used as a sampling clock of the reproduction signal 1s in another circuit.

First, when the reproduction signal 1s and the reproduction clock 10s are input into the PLL circuit 20 through the reproduction signal input terminal 1, the A / D converter 4 converts the reproduction signal 1s into a digital signal 4s, In the phase comparator 5, the digital signal 4s and the reproduction clock 10s output to the outside
The sampling phases of and are compared, and the frequency control signal 5
1s and the phase control signal 52s are output. The frequency control signal 51s is for performing a rough frequency pull-in control, and the phase control signal 52s is for performing a phase matching control.

The frequency control DAC 6 converts the frequency control signal 51s output from the phase comparator 5 into an analog frequency control signal 6s. It should be noted that the reason why the analog signal is converted here is that the VCO described later performs an oscillating operation corresponding to the strength of the input analog signal.

On the other hand, the phase control DAC 7 converts the phase control signal 52s output from the phase comparator 5 into an analog phase control signal 7s. Similar to the frequency control DAC 6, the analog signal is converted because the VCO performs an oscillating operation corresponding to the strength of the input analog signal. Further, in the phase control DAC 7, the frequency control DAC 6 makes a rough gain decision, while the fine gain decision is made. Inputs to the frequency control DAC 6 and the phase control DAC 7 are controlled by a selector 80 and a selector 81, respectively.

Next, in the adder 82, the output currents of the analog frequency control signal 6s and the analog phase control signal 7s are added and converted into a voltage, which is output as the VCO oscillation control signal 82s, and the low-pass filter 8 outputs the voltage. Noise is removed from the VCO oscillation control signal 82s to reduce jitter in the oscillation of the VCO 9.

Then, the VCO 9 oscillates at a corresponding frequency by applying the VCO oscillation control signal 8s from which noise has been removed by the low-pass filter 8 and outputs the oscillation clock 9s. This oscillation clock 9s is used for the M divider 1
It is divided by M by 0 and output as a reproduced clock signal 10s. As described above, the combination of the VCO 9 and the M frequency divider 10 allows the output clock 1 having a wide range of frequencies.
0s can be obtained. As a result, reproduction of a music CD having a relatively low frequency is supported in addition to reproduction at the highest speed of DVD or CD-ROM.

In the system controller 14, V
In the CO adjustment mode, the switching signal 143s is output so that the two selectors 80 and 81 are not the output signals (51s and 52s) of the phase comparator 5 but the system controller 1
The signals 141s and 142s from 4 are selected,
On the other hand, by outputting the control signal 144s of the maximum current generation circuit 13, the oscillation frequency when the VCO 9 is oscillated at the maximum oscillation frequency by setting the frequency control DAC 6 and the phase control DAC 7 to the maximum output, and falls within the target value. Thus, the current value 13s of the maximum current generating circuit 13 is adjusted.

Then, in the normal operation mode after the adjustment of the VCO 9 is completed, a constant maximum current 13 s is output from the maximum current generating circuit 13 adjusted via the control signal 144 s.
Is generated and the switching signal 143s is output to output 2
The two selectors 80 and 81 are switched, and the output signals 51s and 52s from the respective phase comparators 5 are frequency-controlled D
It will be output to the AC 6 and the phase control DAC 7. As a result, the output clock 10s of the VCO 9 is controlled to be the reproduction clock extracted from the reproduction signal.

The PLL circuit 20 having the above configuration
Is a frequency control signal 1 from the system controller 14.
41s, phase control signal 142s, selector switching signal 1
43s, the control signal 144s of the maximum current generating circuit, and the reproduction signal 1s from the outside are input, and the reproduction clock 10s controlled by the feedback circuit is output from the reproduction clock output terminal 3.

FIG. 13 shows another example of the conventional PLL circuit. In the figure, the same reference numerals are used for the same or corresponding components as in FIG. 12, and the description thereof will be omitted. In FIG. 13, reference numeral 21 is a PLL circuit body. Reference numeral 19 is a VCO adjusting means, which receives the output signal 5s of the phase comparator 5 as an input and outputs an analog frequency control signal 19s for adjusting the VCO 9.

In the figure, 1s is an input reproduction signal (strictly speaking, whether the signal line is the signal line or not, if written correctly, it becomes complicated and there is no fear of misunderstanding. (This is also true for other signals. In principle, the "signal" of the clock signal is also omitted for the same reason).

The operation of the conventional PLL circuit thus constructed will be described. Here, the reproduced signal 1s is an analog (reproduced) signal reproduced from the optical disc and before being binarized. Also, the reproduction clock 10s is the reproduction signal 1s.
This is the recovered clock extracted from
0s is used as a sampling clock for the reproduction signal 1s in another circuit.

First, when a reproduction signal and a reproduction clock 1s are input into the PLL circuit 20 through the reproduction signal input terminal 1, the A / D converter 4 converts the reproduction signal 1s into a digital signal 4s. The internal processing is digitized.

Then, in the phase comparator 5, the digitized reproduction signal 4s and the reproduction clock 10 to be output to the outside.
VCO adjusting means 1 by comparing the sampling phase with s
The control signal 5s of 9 is output, and the VCO adjusting means 19
The signal 5s output from the phase comparator 5 is converted into an analog frequency control signal 19s and output to the VCO 9.

In the VCO 9, the VCO oscillation control signal 19s
By oscillating at the corresponding frequency, the oscillation clock 9s is output, and the M frequency divider 10 frequency-divides the oscillation clock 9s by M. As described above, by combining the VCO 9 and the M frequency divider 10, it is possible to obtain the output clock 10s having a wide range of frequencies. And this
In addition to the maximum double speed reproduction of DVD and CD-ROM, reproduction of music CD having a relatively low frequency is also supported.

In the system controller 14, V
The control signal 140s of the CO adjusting means 19 is output to output the VCO.
9 control signal (analog frequency control signal) 19s is optimized so that the control signal 146s of the M frequency divider 10 is output to switch the frequency division ratio of the M frequency divider 10 as necessary. To do.

As described above, in the PLL circuit 20, the control signal 140s for the VCO adjusting means 19 from the system controller 14 and the control signal 146s for the M frequency divider 10 are provided.
Also, the reproduction signal 1s from the outside is input, and the reproduction clock 10s controlled by the feedback circuit is output.

As described above, in the conventional PLL circuit, the AD
The converter converts the input analog signal into a digital signal by sampling it with the clock signal output from the VCO, and the phase comparator detects the frequency and phase error between the clock signal and the input signal. If the PLL locks, the input signal is synchronized. The feedback circuit, which performs sampling with the clock taken, performs phase comparison between the analog reproduced signal from the outside and the output clock to determine the voltage to be applied to the VCO,
The output clock was obtained by the oscillation of the VCO.

It should be noted that the above is one example of the conventional PLL circuit. In addition, in the VCO adjustment mode, the maximum current circuit is adjusted by an analog bias signal from a separate register or by an operator. There are also things.

Further, although the system controller has been described as a circuit configuration of the PLL circuit, it is actually an integral configuration, or has additional circuits (configurations) such as various compensation circuits. There is a case.

[0028]

[Patent Document 1] Japanese Patent Laid-Open No. 2001-273725

[0029]

However, in recent years, various systems have been proposed for optical disk media, and PLL has been proposed.
The analog playback signal to be processed by the circuit is also a DVD or C
It covers a wide range of frequencies from the highest speed of D-ROM to the first speed of music CD. As one countermeasure example, in the above-mentioned configuration, the gain characteristic of the VCO is fixed while being adjusted in accordance with the analog reproduction signal using the corresponding highest frequency, and for frequencies lower than that, the M divider is used. It is designed to correspond by dividing by.

However, since the semiconductor used for the constant current source and the constant voltage source of the maximum current (bias value) generating circuit is basically a fired product, the capacity, resistance value, etc. may vary slightly. Also, it is difficult to effectively use the band of the oscillation frequency characteristic of the VCO.
As a result, the performance of the PLL cannot be improved.

Even if the oscillation range of the VCO varies,
If the oscillator is set to oscillate at a frequency higher than the frequency of the analog playback signal that uses the highest corresponding frequency, it can operate in a wide range of frequencies. The frequency cannot be minimized, and as a result, the response characteristic of the PLL deteriorates.

Therefore, it has been desired to develop a technique capable of maximally effectively utilizing the oscillation frequency characteristic of the VCO for analog reproduced signals over a wide range of frequencies. Therefore, the present invention has been made to solve the above-mentioned problems.
An object of the present invention is to provide a PLL circuit which can maintain the response of the L circuit and can effectively use the band of the oscillation frequency characteristic of the VCO.

[0033]

In order to solve the above-mentioned problems, a PLL circuit according to claim 1 of the present invention comprises a signal obtained by digitizing an analog reproduction signal inputted from the outside and a loop circuit in a loop. A voltage controlled oscillator (VCO) and a digital signal obtained by converting an input analog reproduction signal in a PLL circuit that oscillates by performing feedback control on an in-loop oscillator so that the phase difference with the output from the oscillator becomes constant. A phase control signal used to control the frequency and phase of the output clock signal by comparing the phase with a clock signal output to the outside from the first phase comparison means, and the first phase comparison means. First D / A conversion means for converting the frequency control signal output from the first phase comparison means into an analog control current signal; and the first D / A conversion means.
A maximum current generating means for generating a maximum current in the A conversion means,
An analog control of the phase control signal output from the first phase comparison means is performed by using a gain adjusting means for adjusting the gain of the maximum current value output from the maximum current generating means and the gain-adjusted constant current. Second D / A conversion means for converting into a current signal, a fixed clock signal input from the outside and a clock signal output from the voltage controlled oscillator (VCO) to the outside are compared, and depending on the comparison result. In the adjustment mode for adjusting the maximum current generating means, the second phase comparing means for controlling the gain adjusting means, and the oscillator, a predetermined frequency control signal and a predetermined phase control signal are generated, and these signals are generated. Using the first D / A conversion means and the second D / A conversion means for adjusting the oscillator.
In the normal operation mode in which the A / A conversion means is controlled and the oscillator is not adjusted, the frequency control signal output from the first phase comparison means and the phase control output from the first phase comparison means The voltage-controlled oscillator includes the first D / A conversion means and the control means for controlling the second D / A conversion means to use a signal.
It is characterized in that adjustment is performed based on a value obtained by adding the signals output from the conversion means and the second D / A conversion means, and a reproduction clock synchronized with the input analog reproduction signal is output.

A PLL circuit according to a second aspect of the present invention is the PLL circuit according to the first aspect, wherein the control means has a maximum value of a predetermined frequency control signal in the first adjustment mode, and Generating a minimum value of a predetermined phase control signal, controlling the first D / A converting means and the second D / A converting means to adjust the oscillator using these values, and In the adjustment mode of No. 2, the maximum value of the predetermined frequency control signal and the maximum value of the predetermined phase control signal are generated, and the first D / A conversion is performed so as to adjust the oscillator using these values. Means for controlling the means and the second D / A conversion means.

Further, in the PLL circuit according to claim 3 of the present invention, the phase difference between the signal obtained by digitizing the analog reproduction signal inputted from the outside and the output from the oscillator in the loop becomes constant. In the PLL circuit that oscillates by performing feedback control on the in-loop oscillator,
The frequency used for controlling the frequency and phase of the output clock signal by comparing the phases of the digital signal obtained by converting the input analog reproduction signal and the clock signal output from the voltage controlled oscillator (VCO) to the outside. First phase comparison means for generating a control signal and a phase control signal, and first D / A conversion means for converting the frequency control signal output from the first phase comparison means into an analog control current signal,
First gain adjusting means for adjusting the output of the analog control current signal output from the first D / A converting means, and the phase control signal output from the first phase comparing means is converted into an analog control current signal. Second D / A converting means, second gain adjusting means for adjusting the output of the analog control current signal output from the second D / A converting means, and a fixed clock signal input from the outside. A second phase comparison for comparing the clock signal output from the voltage controlled oscillator (VCO) to the outside and controlling the first gain adjusting means and the second gain adjusting means according to the comparison result. Means, in the adjustment mode for adjusting the oscillator, to generate a predetermined frequency control signal and a predetermined phase control signal,
In the normal operation mode in which the first D / A converting means and the second D / A converting means are controlled to adjust the oscillator using these signals and the oscillator is not adjusted, The first D / A conversion means and the second D / A conversion means for using the frequency control signal output from the first phase comparison means and the phase control signal output from the first phase comparison means. A control means for controlling the A conversion means is provided,
The voltage controlled oscillator performs adjustment based on a value obtained by adding the signals output from the first D / A conversion means and the second D / A conversion means, and reproduces in synchronization with the input analog reproduction signal. It is characterized by outputting a clock.

According to a fourth aspect of the present invention, in the PLL circuit according to the third aspect, the control means has a maximum value of a predetermined frequency control signal in the first adjustment mode, and Generating a minimum value of a predetermined phase control signal, controlling the first D / A converting means and the second D / A converting means to adjust the oscillator using these values, and In the adjustment mode of No. 2, the maximum value of the predetermined frequency control signal and the maximum value of the predetermined phase control signal are generated, and the first D / A conversion is performed so as to adjust the oscillator using these values. Means for controlling the means and the second D / A conversion means.

In the PLL circuit according to the fifth aspect of the present invention, the phase difference between the signal obtained by digitizing the analog reproduction signal input from the outside and the output from the oscillator in the loop becomes constant. In the PLL circuit that oscillates by performing feedback control on the in-loop oscillator,
The frequency used for controlling the frequency and phase of the output clock signal by comparing the phases of the digital signal obtained by converting the input analog reproduction signal and the clock signal output from the voltage controlled oscillator (VCO) to the outside. First phase comparison means for generating a control signal and a phase control signal, and first D / A conversion means for converting the frequency control signal output from the first phase comparison means into an analog control voltage signal,
First gain adjusting means for adjusting the output of the analog control voltage signal output from the first D / A converting means, and the phase control signal output from the first phase comparing means into an analog control voltage signal. Second D / A conversion means for converting,
Second gain adjusting means for adjusting the output of the analog control voltage signal output from the second D / A converting means, a fixed clock signal input from the outside, and output from the voltage controlled oscillator (VCO) to the outside. Of the adjustment mode for adjusting the oscillator and the second gain adjusting means for controlling the first gain adjusting means and the second gain adjusting means according to the comparison result. When
Controlling the first D / A converting means and the second D / A converting means so as to generate a predetermined frequency control signal and a predetermined phase control signal and adjust the oscillator using these signals. However, in the normal operation mode in which the adjustment of the oscillator is not performed, the frequency control signal output from the first phase comparison unit and the phase control signal output from the first phase comparison unit are used. 1, D / A conversion means,
And a control means for controlling the second D / A conversion means, wherein the voltage controlled oscillator adds signals output from the first D / A conversion means and the second D / A conversion means. It is characterized in that adjustment is performed based on the value obtained and a reproduction clock synchronized with the input analog reproduction signal is output.

According to a sixth aspect of the present invention, in the PLL circuit according to the fifth aspect, the control means has a maximum value of a predetermined frequency control signal in the first adjustment mode, and Generating a minimum value of a predetermined phase control signal, controlling the first D / A converting means and the second D / A converting means to adjust the oscillator using these values, and In the adjustment mode of No. 2, the maximum value of the predetermined frequency control signal and the maximum value of the predetermined phase control signal are generated, and the first D / A conversion is performed so as to adjust the oscillator using these values. Means for controlling the means and the second D / A conversion means.

According to a seventh aspect of the present invention, in the PLL circuit according to the third or fifth aspect, the output of the first D / A converter is the second D / A.
It is characterized in that it is a control signal for the converter.

A PLL circuit according to an eighth aspect of the present invention is the PLL circuit according to any one of the first to sixth aspects, in which a high frequency component of a signal input to the oscillator is removed. It is characterized by having a low-pass filter.

Further, the PLL circuit according to claim 9 of the present invention is such that the phase difference between the signal obtained by digitizing the analog reproduction signal input from the outside and the output from the oscillator in the loop becomes constant. In a PLL circuit that oscillates a reproduction clock signal by performing feedback control on an internal oscillator, a first circuit used for comparing the phase of the digitized signal and the reproduction clock signal and controlling the frequency of the reproduction clock signal. A first phase comparison means for generating a frequency control signal and a second phase control means for inputting an external clock signal, comparing the input clock signal with the reproduced clock, and controlling the frequencies so that they coincide with each other.
And a VCO adjusting means for converting either the first frequency control signal or the second frequency control signal into an analog signal to adjust the oscillator. In the adjustment mode for adjusting the maximum oscillation frequency of the oscillator, the VCO adjusting means controls the second frequency control signal so as to fall within a predetermined range, and the controlled second frequency control is performed. The signal is used to adjust the maximum oscillation frequency of the oscillator, and the first frequency control signal is output to the oscillator in the normal operation mode.

A PLL according to claim 10 of the present invention.
10. The PLL circuit according to claim 9, wherein the external input clock signal input to the second phase comparison means is a fixed reference clock signal or an extracted clock signal extracted from a reproduction signal of a recording medium. In any one of the above, the second phase comparison means compares the fixed reference clock signal with the reproduced clock in the first adjustment mode, generates the second frequency control signal, and outputs the second frequency control signal. In the adjustment mode, the extracted clock signal is compared with the reproduced clock to generate the second frequency control signal, and the VCO adjusting means is the first
In the adjustment mode and the second adjustment mode, the second frequency control signal is controlled so as to fall within a predetermined first range, and the controlled second frequency control signal is used to The maximum oscillation frequency of the oscillator is adjusted, and the maximum oscillation frequency of the oscillator is periodically adjusted in the normal operation mode.

A PLL according to claim 11 of the present invention.
11. The PLL circuit according to claim 10, further comprising a filter that removes noise from the extracted clock and an N divider that divides the fixed reference clock signal by N. Is.

[0044]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. The embodiment shown here is merely an example, and the present invention is not necessarily limited to this embodiment.

(First Embodiment) A PLL circuit according to the first embodiment of the present invention will be described below. FIG. 1 is a diagram showing the configuration of the PLL circuit according to the first embodiment. In this figure, the same or corresponding components as those in FIG. 12 are designated by the same reference numerals, and the description thereof will be omitted. The PLL circuit 200 according to the first embodiment includes a fixed clock 2s and a frequency control signal 141 from the system controller 14 in addition to the analog reproduction signal 1s from the outside.
s, phase control signal 142s, selector selection signal 143
s, a control signal 14 of a clock frequency phase comparator described later
5s is input and the reproduced clock 10s is output.

In the figure, 2 is a fixed input terminal for inputting a fixed clock signal 2s. Fixed clock 2
s is a wobble clock output from an external crystal oscillator or the like, or a wobble clock from an optical disk whose frequency is known in advance, and serves as a reference for the frequency of the reproduction clock 10s. Reference numeral 12 is a clock frequency phase comparator which serves as a second phase comparing means, and compares the phase of the fixed clock 2s with the phase of the output clock 10s of the M frequency divider 10.

The output signal 121s of the clock frequency phase comparator 12 is the maximum current generating circuit (maximum current generating means) 13
The signal 122s is a phase control D which will be described later.
Maximum current gain adjusting circuit (gain adjusting means) 8 for AC
3 is a control signal for controlling 3. Since the clock frequency phase comparator 12 controls the output of the maximum current generation circuit 13 by comparing only the frequencies here, in this case, the clock frequency phase comparator 12
It will operate as a clock frequency comparator.

145s is a control signal of the clock frequency phase comparator 12 output from the system controller 14. 143s is a signal (selector switching signal) for controlling signal selection by the selectors 80 and 81 output from the system controller 14, and the M frequency divider 1
It controls the opening and closing of the switch between 0 and the clock frequency phase comparator 12. 146s is a frequency division switching control signal for performing switching control of the frequency division ratio of the M frequency divider 10 between M and M + 1.
Reference numeral 83 is a maximum current gain adjusting circuit of the phase control DAC 7, which is an output signal 122 of the clock frequency phase comparator 122.
The maximum current 83s for phase control DAC is output based on s.

Here, the control of the clock frequency phase comparator 12 will be described. In the "VCO adjustment mode 1", that is, at the time T1 when a certain time (a predetermined time measured by a counter (not shown)) has elapsed from the start-up T0, the control signal 145s is output from the system clock 14 to the clock frequency phase comparator 12. Then, the output 121s of the clock frequency phase comparator 12 is locked.

When the time T2 (T1 <T2) measured by a counter (not shown) has elapsed, the system controller 1
4 to the clock frequency phase comparator 12 to the control signal 145
s is output, and the output 1 of the clock frequency phase comparator 12
22s is locked. By locking the output of the clock frequency phase comparator 12, the gain of the VCO 9 is locked after time T2.

Next, switching between the selector 80 and the selector 81 will be described. At time T2 (T1 <T2) measured by a counter (not shown), the PLL circuit 20
A switching signal 143s for switching 0 from the “VCO adjustment mode” to the “normal operation mode” is output from the system controller 14 to the selector 80 and the selector 81. Then, the selector 80 causes the switching signal 143s described above.
Input, the frequency control signal 141s from the system controller 14 is selected in the "VCO adjustment mode 1" and the "VCO adjustment mode 2", and the "normal operation mode" is selected.
At this time, the frequency control signal 51s is selected.

Similarly, the selector 81 selects the phase control signal 142s from the system controller 14 in "VCO adjustment mode 1" and "VCO adjustment mode 2", and selects the phase control signal 142s in "normal operation mode". 52s
Select.

Next, the control of the VCO 9 will be described.
In the clock frequency phase comparator 12, the fixed clock 2s and the output clock 10s of the M frequency divider 10 are compared in frequency and phase to determine the maximum current 13s output from the maximum current generation circuit 13, which is composed of, for example, 4 bits. The control signal 121s is output, and the maximum current generation circuit 13 outputs the maximum current value 13s in response to the input of the control signal 121s.

In the "VCO adjustment mode 1", the maximum frequency control signal 141s, the minimum phase control signal 142s, and the maximum current 13s are given at the same time, and the frequency divider switching control signal 146s controls the M frequency divider 10 to M. By switching to the frequency division, the gain in which the frequency control DAC 6 of the VCO 9 is involved is determined. Further, in the "VCO adjustment mode 2", the maximum frequency control signal 141s and the maximum phase control signal 1
42s and the maximum current 13s are given simultaneously, and further,
The M frequency divider 10 is set to M + by the frequency division switching control signal 146s.
VCO9 phase control D by switching to 1 frequency division
The gain with which AC6 is involved is determined.

Further, in the "normal operation mode", the output from the clock frequency phase comparator 12 is locked, so that the maximum current generating circuit 13 outputs a constant current. The M frequency divider 10 is a variable type from 1 frequency division to 32 frequency division. For example, the external clock is 33 MHz and the VCO is VCO.
When 9 oscillates at 198 MHz, the frequency is divided by 6. It goes without saying that the frequency division of the M frequency divider 10 is not limited to 32 frequency division.

The operation of the PLL circuit 200 will be described below in more detail with reference to FIG. FIG. 2 is a timing chart showing how the input / output signals of the respective parts of the PLL circuit 200 shown in FIG. 1 change with the lapse of time from the start of adjustment. In FIG. 2, time T0 is an initial state, and each signal has an initial value.

Next, after time T0, "VCO adjustment mode 1" is entered, where M of the maximum frequency control signal 141s is reached.
AX fixed, minimum phase control signal 142s MIN fixed, frequency control DAC FF (in case of 8 bits)
A fixed value of 00 is input to the phase control DAC 7.
As a result, the VCO 9 becomes the maximum oscillation frequency controlled by the frequency control DAC 6.

At time T1, the clock frequency phase comparator 1
The control signal 122s from 2 is locked. This is because the phase comparison between the reproduction clock 10s and the fixed clock 2s is completed. By locking this control signal 122s, the maximum current value of the frequency control DAC 6 will not be changed more than necessary.

After time T1, the "VCO adjustment mode 2" is entered, the maximum frequency control signal 141s is fixed to MAX and the minimum phase control signal 142s is fixed to MAX, and the frequency control DAC 6 is provided with FF (in the case of 8 bits). Phase control D
A fixed value of FF is input to AC7. Further, the M frequency divider 10 selects M + 1. And this allows VCO9
Is the maximum oscillation frequency controlled by the phase control DAC 7.

Then, at time T2, the selectors 80 and 81
The switching signal 143s is switched from "VCO adjustment mode 2" to "normal operation mode". And
After this time T2, the optimum gain of the VCO 9 has already been determined, so the input reproduction signal 1s
The reproduced clock 10s sufficiently corresponding to the band is output. After time T2, the maximum frequency control signal 1
41s, the value of the maximum phase control signal 142s is Z, that is, undefined (it does not matter whatever the value is because it is not used)
Becomes

As described above, according to the first embodiment, the clock signal 2s input from the outside of the device is compared with the output clock 10s output from the VCO 9, and the maximum value is adjusted when the VCO 9 is adjusted according to the comparison result. Current generation circuit 13
The maximum current 13 s output from the controller is controlled and supplied to the frequency control DAC 6, and the maximum frequency control signal 141 s selected by the selector 80 and supplied from the system controller 14 is digital-analog converted.
The maximum current 13s output from the maximum current generating circuit 13 is adjusted by the maximum current gain adjusting circuit 83 and supplied to the phase control DAC 7, so that the maximum phase control signal 142s selected by the selector 81 is converted into digital-analog. The maximum current 13 s can be supplied according to the frequency of the analog reproduction signal 1 s to be used, and as a result, the frequency per bit of the DAC is minimized and the PLL responsiveness is maintained while stable PLL operation is achieved. It can be performed.

(Second Embodiment) A PLL circuit according to the second embodiment of the present invention will be described below. The difference from the PLL circuit according to the first embodiment is that in the PLL circuit according to the first embodiment, the frequency control DAC 6 and the phase control DAC by the clock frequency phase comparator are used.
The output of 7 is adjusted by adjusting the maximum current of each DAC, whereas in the second embodiment, the gains of the outputs of the frequency control DAC 6 and the phase control DAC 7 are adjusted. The point is that it is configured to adjust. Another difference is that the output current of the frequency control DAC 6 is used as the maximum current of the phase control DAC 7 so that the output current of the frequency control DAC 6 and the output current of the phase control DAC 7 are always proportional to each other.

FIG. 3 is a diagram showing the configuration of the PLL circuit 201 according to the second embodiment. In the figure, the same reference numerals are used for the same or corresponding components as in FIG.
The description is omitted. In FIG. 3, reference numeral 84 is a frequency control DAC output gain adjustment circuit controlled by the control signal 123s output from the clock frequency phase comparator 12, and the output control signal 84s is the phase control DAC.
The input current is 7.

Reference numeral 85 denotes a phase control D controlled by the control signal 124s output from the clock frequency phase comparator 12.
This is an AC output gain adjustment circuit, and the gain-adjusted phase control DAC output signal 85s is input to the adder 82. In addition, the maximum current value 13 from the maximum current generation circuit 13
s is a control signal 144 from the system controller 14.
It is adjusted to an optimum value in advance by s and is fixed during the operation of the system.

PLL circuit 201 configured as described above
The operation of will be described. FIG. 4 is a timing chart showing how the input / output signals of the respective parts of the PLL circuit 201 shown in FIG. 3 change with the passage of time from the start of adjustment.

As can be seen from the figure, in the "VCO adjustment mode 1", the output 84s of the frequency control DAC gain adjustment circuit 84 becomes the input current of the phase control DAC 7,
In the "VCO adjustment mode 2", the output 85s from the phase control DAC gain adjustment circuit 85 is the output signal 84.
The current value (mA) is almost the same as s.

As described above, according to the second embodiment, the clock signal 2s inputted from the outside 201 of the apparatus and the VCO 9
From the output clock 10 s, the output of the frequency control DAC 6 is controlled using the frequency control DAC gain adjustment circuit 84, and the output of the phase control DAC 7 is adjusted according to the comparison result. Circuit 8
5, the VCO oscillation control signal 82s applied to the VCO 9 can be adjusted.
It is possible to perform stable PLL operation while minimizing the frequency per bit of the DAC and maintaining the responsiveness of the PLL, and to adjust the current at a position closer to the VCO 9 as compared with the configuration of the first embodiment. By performing the above, it is possible to improve the adjustment accuracy.

Further, by using the output current of the frequency control DAC 6 as the maximum current of the phase control DAC 7, the output current of the frequency control DAC 6 and the output current of the phase control DAC 7 are always proportional to each other, and the phase control DAC 6 and the phase control DAC 7 are in phase with each other. Current variations between the control DAC 7 and the control DAC 7 are reduced, and the adjustment accuracy can be improved.

(Third Embodiment) A PLL circuit according to the third embodiment of the present invention will be described below. The difference from the second embodiment is that in the PLL circuit of the second embodiment, the frequency control DAC 6, the phase control DAC 7,
The maximum current generation circuit 13 is of the current control type, whereas the third embodiment is of the voltage control type.

FIG. 5 is a diagram showing the structure of the PLL circuit according to the third embodiment. 5, components that are the same as or correspond to those in FIG. 3 are assigned the same reference numerals and explanations thereof are omitted.

Reference numeral 202 is a PLL circuit, 61 is a voltage control type frequency control DAC, 71 is a voltage control type phase control DAC, 131 is a maximum voltage controlled by a control signal 144s output from the system controller 14. It is a generation circuit. In addition, the maximum frequency control signal 141s and the maximum phase control signal 1 from the system controller 14
42s and VCO oscillation control signal 82s from the adder 82
Etc. are not voltage signals but voltage signals. Since the operation is the same as that of the second embodiment, the description thereof is omitted here.

With the above structure, the same effect as that of the second embodiment can be obtained. In the first to third embodiments, a plurality of constituent elements (constituent elements, parts) are integrated or, conversely, one part is a plurality of objects for the convenience of manufacturing. The current signal for maximum frequency control signal in the first embodiment is a concept including an input signal from the system controller 14.
Further, since the clock frequency / phase comparator 12 controls only the frequency to control the output of the maximum current generation circuit 13, in this case, the clock frequency / phase comparator 12 becomes a clock frequency comparator. .

Further, depending on the VCO, etc., (M)
Instead of using the frequency divider 10, it is also possible to use a multiplier or a configuration without a frequency divider. further,
A configuration that has a frequency divider or multiplier on the fixed clock side,
The configuration in which the switch of the selector is opened / closed by the control signal of the clock frequency / phase comparator 12 can be variously modified.

(Fourth Embodiment) A PLL circuit according to a fourth embodiment of the present invention will be described below. Figure 6
FIG. 9 is a diagram showing a configuration of a PLL circuit according to a fourth exemplary embodiment. In the figure, the same or corresponding components as those in FIG. 13 are designated by the same reference numerals, and the description thereof will be omitted.

PLL circuit 203 according to the fourth embodiment
Is a fixed clock 2s, a control signal 147s for the selector from the system controller 14, a control signal 140s for the VCO adjusting means 19, and a control signal 145s for the clock frequency phase comparator 12 in addition to the analog reproduced signal 1s from the outside. And the frequency division control signal 146s of the M frequency divider 10 are input, and the reproduction clock 10s is output.

In the figure, 2 is a fixed input terminal,
The fixed clock signal 2s is input. The fixed clock 2s is a wobble clock output from an external crystal oscillator or the like or from an optical disk whose frequency is known in advance, and serves as a reference for the frequency of the reproduction clock 10s.

A selector 11 selects the output signal 5s of the phase comparator 5 or the output signal 12s of the clock frequency phase comparator 12, and outputs the selected signal 11s to the VCO adjusting means 19. Only when the output signal 12s of the clock frequency / phase comparator 12 is selected, it is also input to the system controller 14. Reference numeral 12 is a frequency phase comparator, and 12s is an output signal of the clock frequency phase comparator 12, which is a control signal of the VCO adjusting means 19.

Here, the control of the clock frequency phase comparator 12 will be described. In the “VCO adjustment mode 1” of the PLL circuit 203, that is, from the start-up T0 to the time T1 after a predetermined time measured by a counter (not shown), the system controller 14 outputs the control signal 145s to the clock frequency phase comparator 12. Then, the output 12s of the clock frequency phase comparator 12 is locked.
By locking the output, the gain of the VCO 9 is locked after time T1.

Next, switching of the selector 11 will be described. At time T1 measured by a counter (not shown), a switching signal 147 for switching the PLL circuit 203 from “VCO adjustment mode 1” to “normal operation mode”
s is output from the system controller 14 to the selector 11.

The selector 11 selects the output 12s of the clock frequency phase comparator 12 in the "VCO adjustment mode 1" by the input of the switching signal 147s, and the VCO adjustment means 19 and the system controller 14 are selected.
Output to. In the “normal operation mode”, the frequency control signal 5s is selected and output to the VCO adjusting means 19.

Next, the adjustment of the VCO 9 will be described.
In the clock frequency phase comparator 12, the fixed clock 2s and the reproduced clock 10s are compared in frequency and phase,
The control signal 12s for controlling the VCO adjusting means 19 is determined and output, and the VCO adjusting means 19 outputs this control signal 12s.
Based on s, the VCO control signal 19s is output.

In the "VCO adjustment mode 1", the gain related to the VCO 9 is changed by switching the M frequency divider 10 to the M frequency by the control signal 140s of the VCO adjusting means 19 and the frequency division switching control signal 146s. Decided. In the "normal operation mode", the output signal 5s of the phase comparator 5 is output to the VCO 9. It should be noted that, in order to periodically adjust the deviation of the gain of the VCO 9 due to the influence of the change of the ambient temperature and the fluctuation of the power supply voltage with time, when the predetermined time is reached, "VC
O adjustment mode ”is executed.

In this embodiment, for example, the M frequency divider 10 is of a variable type from 1 frequency division to 32 frequency division, and for example, the external clock is 33 MHz and the VCO 9 is 198 MHz.
If it oscillates at, the frequency will be divided by 6. The M divider has the same effect in this embodiment even if it is divided by 32 or more.

PLL circuit 203 configured as described above
The operation of will be described. FIG. 7 is a timing chart showing how the input / output signals of the respective parts of the PLL circuit 203 shown in FIG. 6 change with the lapse of time from the start of adjustment. In FIG. 7, time T0 is an initial state, and each signal has an initial value.

After time T0, the "VCO adjustment mode 1" is entered, the selector 11 is switched by the switching signal 147s from the system controller 14, the output 12s of the clock frequency phase comparator 12 is selected, and the VC
It is output to the VCO adjusting means 19 and the system controller 14 as the control signal 11s of the O adjusting means 19. At this time, in the system controller 14, the control signal 145
By outputting s, the clock frequency phase comparator 12
The clock frequency phase comparator 12 compares the external clock 2s with the output clock 10s of the M frequency divider 10 and outputs the control signal 12s based on the comparison result.

Further, by outputting the frequency division control signal 146s from the system controller 14, the M frequency divider 10
Set the division ratio of. The frequency division ratio is set so that the frequency of the external clock signal 2s and the frequency of the output 10s of the M frequency divider 10 are the same. At this time, the control signal 140s from the system controller 14 sets the output signal 19s of the VCO adjusting means 19 to the maximum or minimum voltage or current value. In addition, the frequency of the external clock signal 2s and the frequency of the output clock 10s of the M frequency divider 10 are compared by the clock frequency phase comparator 12, and the frequency control signal 12s based on the result of the comparison is selected by the selector 11, and V
It is input to the CO adjustment means 19 and the system controller 14. Then, in the system controller 14, the output 19 of the VCO adjusting means 19 is adjusted so that the value of the selection signal 11s (output signal 12s from the clock frequency phase comparator 12s) of the selector 11 becomes a predetermined target value.
Adjust s.

Next, after the time T1, the "normal operation mode" is entered, and the signal 1 output from the system controller 14 is output.
40s is fixed to the value determined in the "VCO adjustment mode 1". Further, since the external input clock 2s and the output signal 12s of the clock frequency phase comparator 12 do not need to be referenced, they are fixed to constant values. On the other hand, the first phase comparator 5 compares the signal 4s obtained by converting the analog signal 1s into a digital value by the AD converter 4 and the output clock 10s of the M frequency divider 10, and outputs the signal 5 indicating the frequency and phase error.
Output s. Then, the output signal 5s of the phase comparator 5 is selected by the selector 11, and the VCO adjusting means 19 outputs the signal 19s based on the output signal 5s of the phase comparator 5.
Is output. By this operation, the analog signal 1s
The clock 10s synchronized with is output from the output terminal 3 to the outside.

FIG. 8 shows that the external clock input terminal 2 is reproduced from the optical disk instead of the fixed clock after the input signals of the respective parts of the PLL circuit 203 have become the "VCO adjustment mode 1" and the "normal operation mode". The wobble clock extracted from the selected signal is selected again, and the VCO adjusting means 1 is selected again.
FIG. 9 is a timing chart when entering a “VCO adjustment mode 2” for performing gain adjustment 9 and a subsequent “normal operation mode”. The “VCO adjustment mode 1” and the subsequent “normal operation mode” are the same as those described with reference to FIG.

After time T2, the "VCO adjustment mode 2" is entered, the wobble clock 2s is input, and the other operations are the same as those in the "VCO adjustment mode 1". The frequency comparison result 12s by the clock frequency phase comparator 12 between the wobble clock 2s and the output clock 10s of the M frequency divider 10 is selected by the selector 11 and VC
It is output to the O adjusting means 19 and the system controller 14. Then, in the system controller 14, the selection signal 11s (the output signal 12 of the frequency phase comparator 12
s) is compared with a predetermined target value when the wobble clock is used, the value of the signal 140s is corrected from the value in the "VCO adjustment mode 1", and the gain of the VCO adjustment means 19 is also corrected.

After the time T3, the "normal operation mode" is entered, and the value of the signal 140s at that time is held at the value determined in the VCO adjustment mode 2. The detailed description of the operation in the “normal operation mode” has been described with reference to FIG. 7, and will not be repeated here.

As described above, according to the fourth embodiment, the clock signal 2s input from the outside of the device is compared with the output clock 10s from the VCO 9, and the VCO adjustment is performed according to the comparison result. The maximum frequency of the VCO 9 can be controlled according to the frequency of the reproduction signal 1s, and as a result, stable PLL operation can be performed while maintaining the responsiveness of the PLL.

(Fifth Embodiment) A PLL circuit according to a fifth embodiment of the present invention will be described below. The difference from the fourth embodiment is that, in the PLL circuit according to the fourth embodiment, a signal in which a fixed clock and a wobble clock are externally switched is input as the external clock 2s. In the PLL circuit according to the fifth embodiment, a selector capable of selecting a fixed clock or a wobble clock is provided inside and switching is performed by a system controller.

FIG. 9 is a diagram showing the structure of the PLL circuit according to the fifth embodiment. In the figure, the same or corresponding components as those in FIG. 6 are designated by the same reference numerals, and the description thereof will be omitted. In FIG. 9, reference numeral 204 is a PLL circuit body.

Reference numeral 2 is a fixed clock input terminal for inputting a fixed clock signal (fixed reference clock signal) 2s, and 15 is a wobble clock input terminal for inputting a wobble clock signal 15s from an optical disk. is there. Reference numeral 17 denotes a selector that selects either the fixed clock 2s or the wobble clock 15s by the switching signal 148 from the system controller 14. The operation of the PLL circuit 204 configured as above is almost the same as that of the above-described fourth embodiment, and thus the description thereof is omitted.

According to the fifth embodiment, either the fixed clock 2s or the wobble clock 15s input from the outside of the apparatus and the output clock 10s of the VCO 9 are used.
And the VCO adjustment is performed according to the comparison result, the VCO is adjusted according to the frequency of the reproduction signal 1s.
It is possible to control the maximum frequency of 9 and, as a result, PL
A stable PLL operation can be performed while maintaining the responsiveness of L.

Since the fixed clock 2s and the wobble clock 15s can be switched internally,
It is possible to switch between the fixed clock 2s and the wobble clock 15s as necessary, without outputting the switching signal to the outside as in the fourth embodiment.

(Sixth Embodiment) A PLL circuit according to a sixth embodiment of the present invention will be described below. The difference from the PLL circuit according to the fifth embodiment is that in the PLL circuit according to the fifth embodiment, the wobble clock signal 15s and the external clock signal 2s are used as they are in the selector 1.
7 was selected, the PL according to the sixth embodiment
In the L circuit, the wobble clock signal 15s is passed through the wobble signal filter 18, and the external clock signal 2s is divided by N. Further, the sixth embodiment is different in that the VCO adjusting means 19 is composed of a maximum current generating circuit, a current control type DAC and a low pass filter.

FIG. 10 is a diagram showing the structure of the PLL circuit according to the sixth embodiment. In the figure, components that are the same as or correspond to those in FIG. In FIG. 10, 205 is a PLL circuit main body.

Reference numeral 18 is a wobble signal filter for removing noise contained in the wobble signal 15s, and 18s is an output thereof. Reference numeral 16 is an N divider that divides the external clock (fixed reference clock signal) 2s based on the control signal 149s output from the system controller 14, and 16s is a clock signal that is divided by N. Reference numeral 13 denotes a maximum current generation circuit that generates a maximum current value 13s based on the control signal 140s output from the system controller 14.

Reference numeral 20 is a current control type DAC, and 7s is its output current value. 8 is a low-pass filter (LP
F) and 8s is its output signal. The maximum current generating circuit 13, the DAC 20, and the LPF 8 correspond to the VCO adjusting means 19 in the fourth or fifth embodiment. 146s is a control signal for the N frequency divider, and 142s is a control signal for the maximum current generation circuit 12.

Other than the above, the description is omitted because it is almost the same as in the fifth embodiment. Embodiment 6 as described above
According to the method, either the fixed clock 2s or the wobble clock 15s input from the outside of the device is compared with the output clock 10s of the VCO 9, and V is output according to the comparison result.
Since the CO adjustment is performed, the maximum frequency of the VCO 9 can be controlled according to the frequency of the reproduction signal 1s, and as a result, stable PLL operation can be performed while maintaining the responsiveness of the PLL.

Since the filter 18 for removing noise from the wobble signal 15s and the N divider 16 for dividing the fixed reference clock signal 2s by N are provided,
The stability of the PLL circuit is increased, and the VCO can be adjusted without depending on the frequency of the external clock.

(Seventh Embodiment) A PLL circuit according to a seventh embodiment of the present invention will be described below. The difference from the sixth embodiment is that, in the PLL circuit according to the sixth embodiment, the VCO control DAC and the maximum current generation circuit are current control type, whereas the seventh embodiment is different. The PLL circuit according to 1 is a voltage control type.

FIG. 12 shows a PLL according to the seventh embodiment.
It is a figure which shows the structure of a circuit. In the figure, the same or corresponding components as those in FIG. 10 are designated by the same reference numerals, and the description thereof will be omitted. In the figure, 206 is a PLL circuit main body, 21 is a voltage control type VCO control DAC, and 131 is a maximum voltage generation circuit controlled by a control signal 144s output from the system controller 14. Further, the control signal 140s or the like from the system controller 14 is not a current signal but a voltage signal. Since the operation is the same as that of the sixth embodiment, the description thereof is omitted here.

With the above structure, the same effect as that of the sixth embodiment can be obtained. In the above fourth to seventh embodiments, a plurality of constituent elements (constituent elements, parts) are integrated or, conversely, one part is made into a plurality of things for convenience of manufacturing, but, for example, The current signal for maximum frequency control signal in the first embodiment is a concept including an input signal from the system controller 14.
Further, since the clock frequency / phase comparator 12 controls only the frequencies to control the output of the maximum current generating circuit 13, the clock frequency / phase comparator becomes a clock frequency comparator in this case.

Furthermore, depending on how the VCO and the like are (M)
Instead of using the frequency divider 10, it is also possible to use a multiplier or a configuration without a frequency divider. further,
A configuration that has a frequency divider or multiplier on the fixed clock side,
The configuration in which the switch of the selector is opened / closed by the control signal of the clock frequency / phase comparator 12 can be variously modified.

[0107]

As described above, according to the PLL circuit of the first aspect of the present invention, the signal obtained by digitizing the analog reproduction signal inputted from the outside and the output from the oscillator in the loop are provided. PL that oscillates by performing feedback control on the oscillator in the loop so that the phase difference between
In the L circuit, the phase of the digital signal obtained by converting the input analog reproduction signal and the phase of the clock signal output from the voltage controlled oscillator (VCO) to the outside are compared, and the frequency and phase of the output clock signal are controlled. And a first phase comparing means for generating a frequency control signal and a phase control signal, and a first D for converting the frequency control signal output from the first phase comparing means into an analog control current signal.
/ A conversion means, maximum current generation means for generating a maximum current in the first D / A conversion means, gain adjustment means for adjusting the gain of the maximum current value output from the maximum current generation means, and Second D / A conversion means for converting the phase control signal, which is the output of the first phase comparison means, into an analog control current signal using a constant current whose gain has been adjusted, and a fixed clock signal input from the outside. And a clock signal output from the voltage controlled oscillator (VCO) to the outside, and second phase comparing means for controlling the maximum current generating means and the gain adjusting means according to the comparison result, The first D / A conversion means for generating a predetermined frequency control signal and a predetermined phase control signal in the adjustment mode for adjusting the oscillator, and adjusting the oscillator using these signals; In the normal operation mode in which the second D / A conversion means is controlled and the oscillator is not adjusted, the frequency control signal output from the first phase comparison means and the first phase comparison means The voltage controlled oscillator includes the first D / A conversion means and the control means for controlling the second D / A conversion means so as to use the phase control signal which is an output. Since the adjustment is performed based on the value obtained by adding the signals output from the conversion means and the second D / A conversion means, and the reproduction clock synchronized with the input analog reproduction signal is output, the analog reproduction used The maximum current can be supplied to the first and second D / A conversion means in accordance with the frequency of the signal, and as a result, the frequency per bit of the D / A conversion means is minimized and the responsiveness of the PLL circuit is reduced. While maintaining Boss was PLL
The effect that an operation can be performed is obtained.

According to the PLL circuit of claim 2 of the present invention, in the PLL circuit of claim 1, the control means has the maximum value of the predetermined frequency control signal in the first adjustment mode. , And generating a minimum value of a predetermined phase control signal, and controlling the first D / A conversion means and the second D / A conversion means to adjust the oscillator using these values. In the second adjustment mode, the maximum value of the predetermined frequency control signal and the maximum value of the predetermined phase control signal are generated, and these values are used to perform the adjustment of the oscillator. A conversion means, and the second D / A
Since the conversion means is controlled, finer adjustment of the oscillator can be performed.

According to the PLL circuit of the third aspect of the present invention, the phase difference between the signal obtained by digitizing the analog reproduction signal input from the outside and the output from the oscillator in the loop is constant. In the PLL circuit that oscillates by performing feedback control on the in-loop oscillator, the digital signal obtained by converting the input analog reproduction signal and the clock signal output from the voltage controlled oscillator (VCO) to the outside are obtained. A frequency control signal used for comparing the phases and controlling the frequency and phase of the output clock signal, and a first phase comparing means for generating the phase control signal, and a frequency which is an output of the first phase comparing means. A first D / A conversion means for converting the control signal into an analog control current signal; and an analog control current signal output from the first D / A conversion means. First gain adjusting means for adjusting the force, second D / A converting means for converting the phase control signal output from the first phase comparing means into an analog control current signal, and the second D / A Second gain adjusting means for adjusting the output of the analog control current signal outputted from the converting means, and a fixed clock signal inputted from the outside and a clock signal outputted from the voltage controlled oscillator (VCO) to the outside are compared. And a second gain controlling means for controlling the first gain adjusting means and the second gain adjusting means according to the comparison result.
In the adjustment mode for adjusting the phase comparing means and the oscillator, a predetermined frequency control signal and a predetermined phase control signal are generated, and these signals are used to adjust the oscillator. A conversion means, and the second D / A
In the normal operation mode in which the conversion means is controlled and the oscillator is not adjusted, the frequency control signal output from the first phase comparison means and the phase control signal output from the first phase comparison means are output. A control means for controlling the first D / A conversion means and the second D / A conversion means for use is provided, and the voltage controlled oscillator includes the first D / A conversion means and the second D / A conversion means. Since the adjustment is performed based on the value obtained by adding the signals output from the D / A conversion means and the reproduction clock synchronized with the input analog reproduction signal is output, the current supplied to the VCO is gain adjusted in advance. The maximum current can be supplied to the VCO according to the frequency of the analog reproduction signal used, and as a result,
It is possible to obtain an effect that a stable PLL operation can be performed while maintaining the responsiveness of the PLL circuit by minimizing the frequency per bit of the D / A conversion means.

According to a fourth aspect of the present invention, in the PLL circuit according to the third aspect, the control means has the maximum value of the predetermined frequency control signal in the first adjustment mode. , And generating a minimum value of a predetermined phase control signal, and controlling the first D / A conversion means and the second D / A conversion means to adjust the oscillator using these values. In the second adjustment mode, the maximum value of the predetermined frequency control signal and the maximum value of the predetermined phase control signal are generated, and these values are used to perform the adjustment of the oscillator. A conversion means, and the second D / A
Since the conversion means is controlled, finer adjustment of the oscillator can be performed.

According to the PLL circuit of the fifth aspect of the present invention, the phase difference between the signal obtained by digitizing the analog reproduction signal input from the outside and the output from the oscillator in the loop is constant. In the PLL circuit that oscillates by performing feedback control on the in-loop oscillator, the digital signal obtained by converting the input analog reproduction signal and the clock signal output from the voltage controlled oscillator (VCO) to the outside are obtained. A frequency control signal used for comparing the phases and controlling the frequency and phase of the output clock signal, and a first phase comparing means for generating the phase control signal, and a frequency which is an output of the first phase comparing means. A first D / A conversion means for converting the control signal into an analog control voltage signal; and an analog control voltage signal output from the first D / A conversion means. First gain adjusting means for adjusting the force, second D / A converting means for converting the phase control signal output from the first phase comparing means into an analog control voltage signal, and the second D / A converting means. A second gain adjusting means for adjusting the output of the analog control voltage signal output from the A converting means, a fixed clock signal input from the outside, and a clock signal output from the voltage controlled oscillator (VCO) to the outside. A predetermined frequency control is performed in the adjustment mode in which the comparison is performed and the first gain adjusting means and the second gain adjusting means are controlled according to the comparison result, and the oscillator is adjusted. A first D / A conversion means and a second D / A conversion means for generating a signal and a predetermined phase control signal and adjusting the oscillator using these signals.
In the normal operation mode in which the A conversion means is controlled and the oscillator is not adjusted, the frequency control signal which is the output of the first phase comparison means and the phase control signal which is the output of the first phase comparison means To control the first D / A converting means and the second D / A converting means so that the voltage controlled oscillator includes the first D / A converting means and the second D / A converting means. Since the adjustment is performed based on the value obtained by adding the signals output from the D / A conversion means in (1) and the reproduction clock synchronized with the input analog reproduction signal is output, the voltage supplied to the VCO is gain adjusted in advance. The maximum voltage can be supplied to the VCO in accordance with the frequency of the analog reproduction signal to be used, and as a result, the frequency per bit of the D / A conversion means is minimized and the response of the PLL circuit is reduced. While maintaining the gender, stable PLL
The effect that an operation can be performed is obtained.

According to a sixth aspect of the present invention, in the PLL circuit according to the fifth aspect, the control means has the maximum value of the predetermined frequency control signal in the first adjustment mode. , And generating a minimum value of a predetermined phase control signal, and controlling the first D / A conversion means and the second D / A conversion means to adjust the oscillator using these values. In the second adjustment mode, the maximum value of the predetermined frequency control signal and the maximum value of the predetermined phase control signal are generated, and these values are used to perform the adjustment of the oscillator. A conversion means, and the second D / A
Since the conversion means is controlled, finer adjustment of the oscillator can be performed.

According to the PLL circuit of claim 7 of the present invention, in the PLL circuit of claim 3 or 5, the output of the first D / A converter is the second D / A converter. Since it is the control signal of the A converter, the output current of the first D / A conversion means and the output current of the second D / A conversion means are always proportional to each other, and the first D / A conversion means The effect that the current variation between the A conversion means and the second D / A conversion means is reduced and the adjustment accuracy can be improved is obtained.

According to the eighth aspect of the PLL circuit of the present invention, in the PLL circuit according to any one of the first to sixth aspects, the high frequency component of the signal input to the oscillator is Since the low-pass filter for removing is provided, it is possible to prevent deterioration of the VCO jitter.

The PLL circuit according to claim 9 of the present invention is arranged such that the phase difference between the signal obtained by digitizing the analog reproduction signal input from the outside and the output from the oscillator in the loop is constant. In a PLL circuit that oscillates a reproduction clock signal by performing feedback control on an internal oscillator, a first circuit used for comparing the phase of the digitized signal and the reproduction clock signal and controlling the frequency of the reproduction clock signal. A first phase comparison means for generating a frequency control signal and a second phase control means for inputting an external clock signal, comparing the input clock signal with the reproduced clock, and controlling the frequencies so that they coincide with each other.
And a VCO adjusting means for converting either the first frequency control signal or the second frequency control signal into an analog signal to adjust the oscillator. In the adjustment mode for adjusting the maximum oscillation frequency of the oscillator, the VCO adjusting means controls the second frequency control signal so as to fall within a predetermined range, and the controlled second frequency control is performed. The signal is used to adjust the maximum oscillation frequency of the oscillator, and in the normal operation mode, the first frequency control signal is output to the oscillator. The maximum current can be supplied to the VCO, and as a result, it is possible to obtain the effect that stable PLL operation can be performed while maintaining the responsiveness of the PLL circuit.

A PLL according to claim 10 of the present invention.
According to the circuit, in the PLL circuit according to claim 9,
The externally input clock signal input to the second phase comparison means is either a fixed reference clock signal or an extracted clock signal extracted from a reproduction signal of the recording medium, and the second phase comparison means is In the first adjustment mode, the fixed reference clock signal is compared with the reproduced clock to generate the second frequency control signal, and in the second adjustment mode, the extracted clock signal and the reproduced clock signal. To generate the second frequency control signal, and the VCO adjusting means presets the second frequency control signal in the first adjustment mode and the second adjustment mode. In the normal operation mode, the maximum oscillation frequency of the oscillator is adjusted using the controlled second frequency control signal. Since the maximum oscillation frequency of the oscillator is adjusted periodically, the maximum current can be supplied to the VCO in accordance with the frequency of the analog reproduction signal used, and as a result, the responsiveness of the PLL circuit is maintained. At the same time, a stable PLL operation can be achieved, and a fixed reference clock and an extracted clock reproduced from the storage medium are internally generated as needed without outputting a clock switching signal to the outside. It can be switched.

A PLL according to claim 11 of the present invention.
According to the circuit, in the PLL circuit according to claim 10, a filter that performs noise removal processing of the extracted clock, and N that divides the fixed reference clock signal by N
By further including the frequency divider, the stability of the PLL circuit is increased, and the VCO can be adjusted without depending on the frequency of the external clock.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a PLL circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram for explaining an operation timing of the PLL circuit according to the first exemplary embodiment of the present invention.

FIG. 3 is a configuration diagram of a PLL circuit according to a second exemplary embodiment of the present invention.

FIG. 4 is a diagram for explaining an operation timing of the PLL circuit according to the second exemplary embodiment of the present invention.

FIG. 5 is a configuration diagram of a PLL circuit according to a third embodiment of the present invention.

FIG. 6 is a configuration diagram of a PLL circuit according to a fourth embodiment of the present invention.

FIG. 7 is a diagram for explaining an operation timing when performing VCO adjustment using a fixed clock in the PLL circuit according to the fourth exemplary embodiment of the present invention.

FIG. 8 is a diagram for explaining an operation timing when the VCO adjustment is performed using the wobble clock in the PLL circuit according to the fourth exemplary embodiment of the present invention.

FIG. 9 is a configuration diagram of a PLL circuit according to a fifth embodiment of the present invention.

FIG. 10 is a configuration diagram of a PLL circuit according to a sixth embodiment of the present invention.

FIG. 11 is a configuration diagram of a PLL circuit according to a seventh embodiment of the present invention.

FIG. 12 is a diagram showing an example of a conventional PLL circuit.

FIG. 13 is a diagram showing an example of a conventional PLL circuit.

[Explanation of symbols]

20,201,202,203,204,205,206 P
LL circuit 1 reproduction signal input terminal 2 fixed clock input terminal 3 reproduction clock output terminal 4 A / D converter 5 phase comparator 6 frequency control DAC 61 voltage control type frequency control DAC 7 phase control DAC 71 voltage control type phase control DAC 8 Low-pass filter (LPF) 9 VCO (voltage controlled oscillator) 10 M division period 12 Clock frequency phase comparator 13 Maximum current generation circuit 131 Maximum voltage generation circuit 14 System controller 15 Conference clock input terminal 16 N divider 17 Selector 18 Wobble signal Filter 19 VCO adjuster 20 DAC 21 Voltage control type DAC 80 Selector (first D / A conversion means) 81 Selector (second D / A conversion means) 82 Adder 83 Maximum current gain adjustment circuit 84 Frequency control DAC output Gain adjustment circuit 85 Phase control DAC Force gain adjusting circuit 1s reproduction signal 2s fixed clock signal 4s digitized reproduction signal 5s frequency control signal 51s frequency control signal 52s phase control signal 6s analog frequency control signal 7s analog phase control signal 8s VCO oscillation control signal 9s oscillation clock 10s output clock signal 11s Output signal of selector 11 12s Frequency control signal 13s Maximum current 15s Wobble signal 16s Output signal of N divider 17s Output signal of selector 18s Output signal of wobble signal filter 19s VCO control signal 20s DAC output signal 21s Voltage control type DAC output signal 82s VCO oscillation control signal 83s Phase control DAC maximum current 84s Gain adjusted frequency control DAC output signal 85s Gain adjusted phase control DAC output signal 121s Maximum current generation circuit control Control signal 122s Phase control DAC maximum current gain adjustment circuit control signal 123s Frequency control DAC output signal Gain adjustment circuit control signal 124s Phase control DAC output signal Gain adjustment circuit control signal 140s VCO adjustment means control signal 141s System controller Frequency control signal 142s of the phase control signal 143s from the system controller switching signal 144s control signal 145s of the maximum current generating circuit from the system controller clock frequency phase comparator control signal 146s frequency division switching control signal 147s switching signal 148s switching signal

Continued front page    F term (reference) 5D044 BC03 CC04 DE32 GM14 GM15                       GM18                 5J106 AA04 BB03 BB04 CC01 CC24                       CC30 CC31 CC41 CC52 DD09                       DD12 DD13 DD34 DD35 DD36                       EE19 FF02 FF05 FF09 GG17                       HH01 HH10 KK03 KK12

Claims (11)

[Claims] 1. A feedback control is applied to an oscillator in a loop so that a phase difference between a signal obtained by digitizing an analog reproduction signal input from the outside and an output from an oscillator in the loop is constant and oscillation is performed. In the PLL circuit for performing the above, the phase of the digital signal obtained by converting the input analog reproduction signal and the phase of the clock signal output from the voltage controlled oscillator (VCO) to the outside are compared, and the frequency and phase of the output clock signal are compared. First phase comparison means for generating a frequency control signal and a phase control signal used for control, and a first D for converting the frequency control signal output from the first phase comparison means into an analog control current signal. / A conversion means, maximum current generation means for generating a maximum current in the first D / A conversion means, and maximum current output from the maximum current generation means Second D / A conversion for converting the phase control signal, which is the output of the first phase comparison means, into an analog control current signal by using the gain adjusting means for adjusting the gain of Means for comparing a fixed clock signal input from the outside with a clock signal output from the voltage controlled oscillator (VCO) to the outside, and the maximum current generating means and the gain adjusting means according to the comparison result. The second phase comparing means for controlling and the adjusting mode for adjusting the oscillator generate a predetermined frequency control signal and a predetermined phase control signal, and use the signals to adjust the oscillator. D of 1
Controlling the A conversion means and the second D / A conversion means,
In the normal operation mode in which the oscillator is not adjusted, the frequency control signal output from the first phase comparison means and the phase control signal output from the first phase comparison means are used. D / A conversion means and control means for controlling the second D / A conversion means are provided, and the voltage controlled oscillator includes the first D / A conversion means and the second D / A conversion means. A PLL circuit, which performs adjustment based on a value obtained by adding output signals and outputs a reproduction clock synchronized with the input analog reproduction signal. 2. The PLL circuit according to claim 1, wherein the control means generates a maximum value of a predetermined frequency control signal and a minimum value of a predetermined phase control signal in the first adjustment mode, These first values are used to adjust the oscillator using these values.
/ A conversion means and the second D / A conversion means are controlled to generate a maximum value of a predetermined frequency control signal and a maximum value of a predetermined phase control signal in the second adjustment mode. To adjust the oscillator using the value of
A PLL circuit for controlling the A / A conversion means and the second D / A conversion means. 3. The oscillator in the loop is oscillated by feedback control so that the phase difference between the signal obtained by digitizing the analog reproduction signal inputted from the outside and the output from the oscillator in the loop becomes constant. In the PLL circuit for performing the above, the phase of the digital signal obtained by converting the input analog reproduction signal and the phase of the clock signal output from the voltage controlled oscillator (VCO) to the outside are compared, and the frequency and phase of the output clock signal are compared. First phase comparison means for generating a frequency control signal and a phase control signal used for control, and a first D for converting the frequency control signal output from the first phase comparison means into an analog control current signal. / A converting means, first gain adjusting means for adjusting the output of the analog control voltage signal output from the first D / A converting means, and the first Second D / A conversion means for converting the phase control signal output from the phase comparison means into an analog control current signal, and adjusting the output of the analog control voltage signal output from the second D / A conversion means. The second gain adjusting means compares the fixed clock signal input from the outside with the clock signal output from the voltage controlled oscillator (VCO) to the outside, and according to the comparison result, the first gain adjusting means. And a second phase comparing means for controlling the second gain adjusting means, and a predetermined frequency control signal and a predetermined phase control signal in the adjustment mode for adjusting the oscillator, and using these signals. To adjust the oscillator by the first D /
Controlling the A conversion means and the second D / A conversion means,
In the normal operation mode in which the oscillator is not adjusted, the frequency control signal which is the output of the first phase comparison means and the phase control signal which is the output of the first phase comparison means are used. D / A conversion means and control means for controlling the second D / A conversion means are provided, and the voltage controlled oscillator includes the first D / A conversion means and the second D / A conversion means. A PLL circuit, which performs adjustment based on a value obtained by adding output signals and outputs a reproduction clock synchronized with the input analog reproduction signal. 4. The PLL circuit according to claim 3, wherein the control means generates a maximum value of a predetermined frequency control signal and a minimum value of a predetermined phase control signal in the first adjustment mode, These first values are used to adjust the oscillator using these values.
/ A conversion means and the second D / A conversion means are controlled to generate a maximum value of a predetermined frequency control signal and a maximum value of a predetermined phase control signal in the second adjustment mode. To adjust the oscillator using the value of
A PLL circuit for controlling the A / A conversion means and the second D / A conversion means. 5. The oscillator in the loop is oscillated by feedback control so that the phase difference between the signal obtained by digitizing the analog reproduction signal input from the outside and the output from the oscillator in the loop becomes constant. In the PLL circuit for performing the above, the phase of the digital signal obtained by converting the input analog reproduction signal and the phase of the clock signal output from the voltage controlled oscillator (VCO) to the outside are compared, and the frequency and phase of the output clock signal are compared. First phase comparison means for generating a frequency control signal used for control and a phase control signal, and a first D for converting the frequency control signal output from the first phase comparison means into an analog control voltage signal. / A converting means, first gain adjusting means for adjusting the output of the analog control voltage signal output from the first D / A converting means, and the first Second D / A converting means for converting the phase control signal output from the phase comparing means into an analog control voltage signal, and adjusting the output of the analog control voltage signal output from the second D / A converting means. The second gain adjusting means compares the fixed clock signal input from the outside with the clock signal output from the voltage controlled oscillator (VCO) to the outside, and according to the comparison result, the first gain adjusting means. And a second phase comparing means for controlling the second gain adjusting means, and a predetermined frequency control signal and a predetermined phase control signal in the adjustment mode for adjusting the oscillator, and using these signals. To adjust the oscillator by the first D /
Controlling the A conversion means and the second D / A conversion means,
In the normal operation mode in which the oscillator is not adjusted, the frequency control signal output from the first phase comparison means and the phase control signal output from the first phase comparison means are used. D / A conversion means and control means for controlling the second D / A conversion means are provided, and the voltage controlled oscillator includes the first D / A conversion means and the second D / A conversion means. A PLL circuit, which performs adjustment based on a value obtained by adding output signals and outputs a reproduction clock synchronized with the input analog reproduction signal. 6. The PLL circuit according to claim 5, wherein the control means generates a maximum value of a predetermined frequency control signal and a minimum value of a predetermined phase control signal in the first adjustment mode, These first values are used to adjust the oscillator using these values.
/ A conversion means and the second D / A conversion means are controlled to generate a maximum value of a predetermined frequency control signal and a maximum value of a predetermined phase control signal in the second adjustment mode. To adjust the oscillator using the value of
A PLL circuit for controlling the A / A conversion means and the second D / A conversion means. 7. The PLL circuit according to claim 3 or 5, wherein the output of the first D / A converter is a control signal of the second D / A converter. PLL circuit to be. 8. The PLL circuit according to claim 1, further comprising a low-pass filter that removes a high-frequency component of a signal input to the oscillator. circuit. 9. The playback clock signal is fed back to the oscillator in the loop so that the phase difference between the signal obtained by digitizing the analog playback signal input from the outside and the output from the oscillator in the loop becomes constant. PL to oscillate
A first phase comparison means for comparing the phases of the digitized signal and the reproduction clock signal in the L circuit and generating a first frequency control signal used for controlling the frequency of the reproduction clock signal; Second phase comparison means for inputting a clock signal from the outside, comparing the input clock signal with the reproduced clock, and generating a second frequency control signal for controlling so that the frequencies match each other; VCO adjusting means for converting either the first frequency control signal or the second frequency control signal into an analog signal for adjusting the oscillator, wherein the VCO adjusting means is the maximum oscillation frequency of the oscillator. In the adjustment mode for adjusting the frequency, the second frequency control signal is controlled to fall within a predetermined range, and the second frequency control signal controlled by Adjusts the maximum oscillation frequency of the oscillator, the normal operation mode, the first frequency control signal and outputs to the oscillator, PLL circuit, characterized in that. 10. The PLL circuit according to claim 9, wherein the external input clock signal input to the second phase comparison means is a fixed reference clock signal or an extracted clock extracted from a reproduction signal of a recording medium. Which is a signal, and the second phase comparison means is in the first adjustment mode,
The fixed reference clock signal is compared with the recovered clock to generate the second frequency control signal,
In the adjusting mode, the extracted clock signal is compared with the reproduced clock to generate the second frequency control signal. The VCO adjusting means includes the first adjusting mode and the second adjusting mode. At this time, the second frequency control signal is controlled to fall within a predetermined first range, and the maximum oscillation frequency of the oscillator is adjusted using the controlled second frequency control signal. A PLL circuit, wherein the maximum oscillation frequency of the oscillator is periodically adjusted in the normal operation mode. 11. The PLL circuit according to claim 10, further comprising a filter that performs noise removal processing on the extracted clock,
A PLL circuit further comprising: an N divider that divides the fixed reference clock signal by N.