WO2021176710A1 - Signal processing device, endoscope system, and signal processing method - Google Patents

Signal processing device, endoscope system, and signal processing method Download PDF

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Publication number
WO2021176710A1
WO2021176710A1 PCT/JP2020/009791 JP2020009791W WO2021176710A1 WO 2021176710 A1 WO2021176710 A1 WO 2021176710A1 JP 2020009791 W JP2020009791 W JP 2020009791W WO 2021176710 A1 WO2021176710 A1 WO 2021176710A1
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Prior art keywords
synchronization signal
signal
generation circuit
synchronization
signal generation
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PCT/JP2020/009791
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French (fr)
Japanese (ja)
Inventor
大樹 山村
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オリンパス株式会社
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Priority to PCT/JP2020/009791 priority Critical patent/WO2021176710A1/en
Publication of WO2021176710A1 publication Critical patent/WO2021176710A1/en
Priority to US17/902,268 priority patent/US20220409009A1/en

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    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B1/00—Instruments for performing medical examinations of the interior of cavities or tubes of the body by visual or photographical inspection, e.g. endoscopes; Illuminating arrangements therefor
    • A61B1/04—Instruments for performing medical examinations of the interior of cavities or tubes of the body by visual or photographical inspection, e.g. endoscopes; Illuminating arrangements therefor combined with photographic or television appliances
    • A61B1/045—Control thereof
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B1/00—Instruments for performing medical examinations of the interior of cavities or tubes of the body by visual or photographical inspection, e.g. endoscopes; Illuminating arrangements therefor
    • A61B1/00002—Operational features of endoscopes
    • A61B1/00004—Operational features of endoscopes characterised by electronic signal processing
    • A61B1/00006—Operational features of endoscopes characterised by electronic signal processing of control signals
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B1/00—Instruments for performing medical examinations of the interior of cavities or tubes of the body by visual or photographical inspection, e.g. endoscopes; Illuminating arrangements therefor
    • A61B1/00002—Operational features of endoscopes
    • A61B1/00004—Operational features of endoscopes characterised by electronic signal processing
    • A61B1/00009—Operational features of endoscopes characterised by electronic signal processing of image signals during a use of endoscope
    • A61B1/000095—Operational features of endoscopes characterised by electronic signal processing of image signals during a use of endoscope for image enhancement
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B1/00—Instruments for performing medical examinations of the interior of cavities or tubes of the body by visual or photographical inspection, e.g. endoscopes; Illuminating arrangements therefor
    • A61B1/06—Instruments for performing medical examinations of the interior of cavities or tubes of the body by visual or photographical inspection, e.g. endoscopes; Illuminating arrangements therefor with illuminating arrangements
    • A61B1/0655—Control therefor
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/60—Control of cameras or camera modules

Definitions

  • the present invention relates to a signal processing device, an endoscope system, and a signal processing method.
  • an endoscope system in which an imaging unit is provided at the tip and an endoscope inserted into a subject and a processor for processing an image signal from the imaging unit are provided.
  • the processor includes a clock signal for operating the imaging unit and a synchronization signal indicating the timing of acquiring an image signal from the imaging unit for each frame (hereinafter, a second synchronization signal). The description) is output to the imaging unit. Then, the imaging unit operates in response to the clock signal and outputs an image signal to the processor at a timing based on the second synchronization signal.
  • Patent Document 1 In order to reduce the size of the imaging unit, a configuration has been proposed in which the function of transmitting and receiving a synchronization signal is removed from the function of the imaging unit (see, for example, Patent Document 1).
  • Patent Document 1 in order to generate a synchronization signal from an image signal in the imaging unit, a change in voltage level is provided in the image signal.
  • a synchronization signal generation unit that generates a first synchronization signal indicating the timing at which the image signal has been transmitted is provided for each frame based on the change in the voltage level, and the synchronization signal generation unit is provided. Is outputting the first synchronization signal to the processor.
  • the first synchronization signal generated by the synchronization signal generation unit and the second synchronization signal generated by the processor are used. Need to be synchronized. Then, in the endoscope system, when a treatment tool such as an electric knife or a snare is used at a high output, the clock signal input to the imaging unit and the image signal output from the imaging unit are affected by the disturbance from the treatment tool. May receive. In such a case, the first synchronization signal generated based on the change in the voltage level in the image signal is affected, and the synchronization shift between the first synchronization signal and the second synchronization signal occurs. That is, it is not possible to properly display an image based on the image signal generated by the imaging unit. Therefore, there is a demand for a technique capable of displaying an appropriate image.
  • the present invention has been made in view of the above, and an object of the present invention is to provide a signal processing device, a signal processing method, and an endoscopic system capable of displaying an appropriate image.
  • the signal processing apparatus includes a processor consisting of at least one hardware, and the processor is input with a clock signal and is first synchronized.
  • the first synchronization signal from the first synchronization signal generation circuit that outputs the signal and the second synchronization signal output from the second synchronization signal generation circuit are not synchronized, the first synchronization signal is not synchronized.
  • the synchronization signal generation circuit of the above is reset, and the frequency of the clock signal is made higher than the other periods in the period in which the first synchronization signal generation circuit is reset.
  • the endoscopic system includes an endoscope inserted into a subject and a processor including at least one piece of hardware, wherein a clock signal is input to the processor, and the first type of processor comprises one or more pieces of hardware.
  • the first synchronization signal from the first synchronization signal generation circuit that outputs the synchronization signal and the second synchronization signal output from the second synchronization signal generation circuit are not synchronized, the first synchronization signal is not synchronized.
  • the synchronization signal generation circuit of 1 is reset, and the frequency of the clock signal is set higher than the other periods in the period in which the first synchronization signal generation circuit is reset.
  • the signal processing method is a signal processing method executed by a processor composed of at least one hardware, and is a first synchronization signal generation circuit in which a clock signal is input and a first synchronization signal is output.
  • the first synchronization signal generation circuit is reset and the first synchronization signal generation circuit is reset. In the period when the synchronization signal generation circuit of 1 is reset, the frequency of the clock signal is made higher than the other periods.
  • the signal processing device According to the signal processing device, the signal processing method, and the endoscope system according to the present invention, it is possible to display an appropriate image.
  • FIG. 1 is a diagram showing a configuration of an endoscope system according to a first embodiment.
  • FIG. 2 is a block diagram showing a configuration of a main part of the endoscope system.
  • FIG. 3 is a time chart showing the operation of the endoscopic system.
  • FIG. 4 is a diagram illustrating the effect of the first embodiment.
  • FIG. 5 is a block diagram showing a configuration of a main part of the endoscope system according to the second embodiment.
  • FIG. 6 is a block diagram showing a configuration of a main part of the endoscope system according to the third embodiment.
  • FIG. 7 is a time chart showing the operation of the endoscopic system.
  • FIG. 1 is a diagram showing a configuration of an endoscope system 1 according to the first embodiment.
  • the endoscope system 1 is used in the medical field, for example, and is a system for observing the inside of a subject (in vivo).
  • the endoscope system 1 includes an endoscope 2, a second synchronization signal generation circuit 3, a display device 4, and a light source device 5.
  • the endoscope 2 is partially inserted into a living body, images a subject image reflected from the living body, and outputs an image signal generated by the imaging.
  • the endoscope 2 includes an insertion portion 21, an operation portion 22, a universal cord 23, and a connector portion 24.
  • the insertion portion 21 is a portion that has at least a part of flexibility and is inserted into the living body.
  • the tip portion 211 (FIG. 1) is provided with an imaging portion 6 (see FIG. 2).
  • the detailed configuration of the imaging unit 6 will be described later in "Configuration of main parts of the endoscope system".
  • the operation unit 22 is connected to the base end portion of the insertion unit 21. Then, the operation unit 22 receives various operations on the endoscope 2.
  • the universal cord 23 extends from the operation unit 22 in a direction different from the extending direction of the insertion unit 21, and guides the cable for transmitting the above-mentioned image signal and the like and the illumination light emitted from the light source device 5. It is a cord in which a fiber or the like is arranged.
  • the connector portion 24 is provided at the end of the universal cord 23, and is detachably connected to the second synchronization signal generation circuit 3 and the light source device 5, respectively.
  • the first synchronous signal generation circuit 7 see FIG. 2
  • the signal processing device 8 see FIG. 2 are provided in the connector portion 24. The detailed configuration of the first synchronization signal generation circuit 7 and the signal processing device 8 will be described in "Configuration of main parts of the endoscope system" described later.
  • the second synchronization signal generation circuit 3 comprehensively controls the operation of the entire endoscope system 1.
  • the second synchronization signal generation circuit 3 performs various image processing on the image signal output from the image pickup unit 6 and after passing through the insertion unit 21, the operation unit 22, the universal cord 23, and the connector unit 24. Run.
  • the detailed configuration of the second synchronization signal generation circuit 3 will be described in "Configuration of main parts of the endoscope system" described later.
  • the display device 4 is an LCD (Liquid Crystal Display), an EL (Electro Luminescence) display, or the like, and displays an image or the like based on an image signal after image processing is executed by the second synchronization signal generation circuit 3.
  • the light source device 5 corresponds to the light source unit according to the present invention.
  • the light source device 5 includes, for example, a halogen lamp, a white LED (Light Emitting Diode), or the like, and emits illumination light. Then, the illumination light emitted from the light source device 5 passes through the connector portion 24, the universal cord 23, the operation portion 22, and the insertion portion 21, and is then irradiated from the tip portion 211 of the insertion portion 21 toward the living body. NS.
  • FIG. 2 is a block diagram showing a configuration of a main part of the endoscope system 1.
  • the imaging unit 6 operates in response to the clock signal CL2 (FIG. 2).
  • the clock signal CL2 is output from the first synchronization signal generation circuit 7 and is input to the imaging unit 6 via the universal code 23, the operation unit 22, and the insertion unit 21. Further, the imaging unit 6 images the illumination light (subject image) that is irradiated from the tip portion 211 of the insertion unit 21 and reflected from the living body.
  • the imaging unit 6 outputs the image signal F1 (FIG. 2) obtained by the imaging.
  • the imaging unit 6 causes the first synchronization signal generation circuit 7 to generate the synchronization signal VS1 (FIG. 2) from the image signal F1 in the same manner as the technique described in Patent Document 1, for example.
  • a change in voltage level is provided in F1.
  • the imaging unit 6 described above includes a CCD (Charge Coupled Device), a CMOS (Complementary Metal Oxide Semiconductor), or the like that converts a subject image into an electric signal (analog signal) by receiving the subject image.
  • the first synchronization signal generation circuit 7 is composed of AFE (Analog Front End). Further, the first synchronization signal generation circuit 7 includes a circuit that converts an analog signal into a digital signal (A / D conversion). Further, the first synchronization signal generation circuit 7 generates the clock signal CL2 based on the clock signal CL12 (FIG. 2) input from the signal processing device 8. Then, the first synchronization signal generation circuit 7 outputs the clock signal CL2 to the imaging unit 6. Further, the image signal F1 that is output from the imaging unit 6 and has passed through the insertion unit 21, the operation unit 22, and the universal code 23 is input to the first synchronization signal generation circuit 7. Then, the first synchronization signal generation circuit 7 generates the image signal F2 (FIG.
  • AFE Analog Front End
  • the synchronization signal VS1 corresponds to the first synchronization signal according to the present invention.
  • the signal processing device 8 includes a processor composed of at least one or more hardware such as an FPGA (Field Programmable Gate Array). As shown in FIG. 2, the signal processing device 8 includes a reset circuit 81, a PLL (Phase Locked Loop) circuit 82, a selector circuit 83, an amplifier circuit 84, and a video processing circuit 85.
  • a reset circuit 81 As shown in FIG. 2, the signal processing device 8 includes a reset circuit 81, a PLL (Phase Locked Loop) circuit 82, a selector circuit 83, an amplifier circuit 84, and a video processing circuit 85.
  • PLL Phase Locked Loop
  • the reset circuit 81 determines whether or not the synchronization signal VS1 output from the first synchronization signal generation circuit 7 and the synchronization signal VS2 generated by the second synchronization signal generation circuit 3 are synchronized. For example, the reset circuit 81 determines that the synchronization signal VS1 and the synchronization signal VS2 are not synchronized when the pulse based on the synchronization signal VS1 and the pulse based on the synchronization signal VS2 rise at different times. Then, when the reset circuit 81 determines that the synchronization signal VS1 and the synchronization signal VS2 are not synchronized, the reset circuit 81 is the first for a certain period from the time when the pulse based on the synchronization signal VS2 first rises after the determination.
  • a high-level reset signal R1 (FIG. 2) is output to the synchronization signal generation circuit 7.
  • the reset circuit 81 outputs a low-level reset signal R1 to the first synchronization signal generation circuit 7.
  • the first synchronization signal generation circuit 7 and the imaging unit 6 start resetting.
  • the reset circuit 81 determines that the synchronization signal VS1 and the synchronization signal VS2 are not synchronized, the reset circuit 81 determines that the synchronization has been achieved from the time when the pulse based on the synchronization signal VS2 first rises after the determination.
  • a high-level select signal SE1 (FIG.
  • the reset circuit 81 is output to the selector circuit 83. In a period other than this period, the reset circuit 81 outputs a low-level select signal SE1 to the selector circuit 83. Further, when the reset circuit 81 determines that the synchronization signal VS1 and the synchronization signal VS2 are not synchronized, the reset circuit 81 is the first synchronization signal generation circuit from the time when the pulse based on the synchronization signal VS2 first rises after the determination. After the 7 is reset, a high-level gain signal G1 (FIG. 2) is output to the amplifier circuit 84 during the period until the image signal F1 for one frame is output from the imaging unit 6. In a period other than this period, the reset circuit 81 outputs a low-level gain signal G1 to the amplifier circuit 84.
  • G1 high-level gain signal
  • the PLL circuit 82 is a frequency synthesizer, and based on the clock signal CL11 (FIG. 2) output from the second synchronization signal generation circuit 3, the clock signal CL121 (FIG. 2) and the clock signal CL122 (FIG. 2) are combined. Generate.
  • the clock signal CL121 is a clock signal having a higher frequency than the clock signal CL122. Then, the PLL circuit 82 outputs the clock signal CL121 and the clock signal CL122 to the selector circuit 83.
  • the selector circuit 83 is provided on a line between the second synchronization signal generation circuit 3 and the first synchronization signal generation circuit 7, and the clock signal is transmitted on the line. Further, the selector circuit 83 selects one of the clock signal CL121 and the clock signal CL122 output from the PLL circuit 82. Specifically, the selector circuit 83 selects the low-frequency clock signal CL122 during the period in which the low-level select signal SE1 is input from the reset circuit 81. Then, the selector circuit 83 outputs the clock signal CL 122 as the clock signal CL 12 to the first synchronization signal generation circuit 7. On the other hand, the selector circuit 83 selects the clock signal CL121 having a high frequency while the high-level select signal SE1 is being input from the reset circuit 81. Then, the selector circuit 83 outputs the clock signal CL121 as the clock signal CL12 to the first synchronization signal generation circuit 7.
  • the amplifier circuit 84 is provided on a line between the first synchronization signal generation circuit 7 and the second synchronization signal generation circuit 3, and the image signal is transmitted on the line. Further, the amplifier circuit 84 adjusts the brightness of the image based on the image signal F2 by multiplying the pixel value of each pixel in the image signal F2 output from the first synchronization signal generation circuit 7 by the gain. do. Specifically, the amplifier circuit 84 multiplies the pixel value of each pixel in the image signal F2 by the first gain during the period in which the low-level gain signal G1 is input from the reset circuit 81 to obtain an image. Generate signal F3.
  • the amplifier circuit 84 obtains a second gain larger than the first gain with respect to the pixel value of each pixel in the image signal F2 during the period in which the high-level gain signal G1 is input from the reset circuit 81.
  • the image signal F3 is generated by multiplying.
  • the image processing circuit 85 generates the image signal F4 by executing various image processing on the image signal F3 output from the amplifier circuit 84.
  • the second synchronization signal generation circuit 3 includes a CPU (Central Processing Unit), an FPGA, and the like.
  • the second synchronization signal generation circuit 3 generates a clock signal CL11 and a synchronization signal VS2 (FIG. 2) indicating the timing of acquiring the image signal F4 for each frame, and generates a signal processing device 8 (PLL circuit 82). And the reset circuit 81) are output respectively.
  • the second synchronization signal generation circuit 3 executes various image processing on the image signal F4 output from the signal processing device 8 (image processing circuit 85). Then, the image based on the image signal after the various image processes are executed is displayed on the display device 4.
  • the clock signal CL11, the clock signal CL121, the clock signal CL122, and the clock signal CL12 described above correspond to the clock signals according to the present invention.
  • the synchronization signal VS2 corresponds to the second synchronization signal according to the present invention.
  • FIG. 3 is a time chart showing the operation of the endoscope system 1.
  • FIGS. 3A to 3K show the clock signal CL11, the synchronization signal VS2, the reset signal R1, the select signal SE1, the clock signal CL12, the synchronization signal VS1, the clock signal CL2, the gain signal G1, and the image.
  • the signal F1, the image signal F2, and the image signal F4 are shown, respectively.
  • the first synchronization signal generation circuit 7 detects the change in the voltage level in the image signal F1 to determine the data number of the image signal F1 in one frame transmitted from the image pickup unit 6. Infer. Then, the first synchronization signal generation circuit 7 raises a pulse based on the synchronization signal VS1 when it is estimated that one frame of the image signal F1 has been transmitted based on the change in the voltage level.
  • the first synchronization signal generation circuit 7 detects a change other than the change in the voltage level generated by the imaging unit 6, so that an erroneous guess is made. Therefore, the pulse based on the synchronization signal VS1 rises at the time P3 (FIG. 3) deviated from the time P2 (FIG. 3) at which the pulse based on the synchronization signal VS2 first rises after the time P1 (FIG. 3 (f)). That is, the reset circuit 81 determines that the synchronization signal VS1 and the synchronization signal VS2 are not synchronized at the time P2.
  • the reset circuit 81 outputs a high-level reset signal R1 to the first synchronization signal generation circuit 7 for a certain period T1 from the time P4 at which the pulse based on the synchronization signal VS2 first rises after the time P2. (Fig. 3 (c)).
  • the period T1 is a period from the start of the reset by the imaging unit 6 to the completion of the reset.
  • the period T2 is a period during which the electric charge is accumulated after the imaging unit 6 is reset.
  • the period T3 is a period from the start of the reset of the first synchronization signal generation circuit 7 to the completion of the reset.
  • the period T3 is a vertical synchronization period (a period between adjacent pulses) based on the synchronization signal VS2. That is, at the time P5 when the pulse based on the synchronization signal VS2 first rises after the time P4, the synchronization signal VS1 and the synchronization signal VS2 can be synchronized.
  • the reset circuit 81 outputs a high-level select signal SE1 to the selector circuit 83 during the period T3 from the time P4 until it is determined that the synchronization signal VS1 and the synchronization signal VS2 have been synchronized (FIG. 3 (d)). )).
  • the selector circuit 83 selects the clock signal CL121 having a higher frequency from the clock signal CL121 and the clock signal CL122 output from the PLL circuit 82. Then, the selector circuit 83 outputs the clock signal CL121 as the clock signal CL12 to the first synchronization signal generation circuit 7 (FIG. 3E). That is, the selector circuit 83 makes the frequency of the clock signal CL12 higher than the other periods in the period T3 in which the first synchronization signal generation circuit 7 is reset.
  • the reset circuit 81 is connected to the amplifier circuit 84 during the period T4 from the time P4 until the image signal F1 for one frame is output from the imaging unit 6 after the first synchronization signal generation circuit 7 is reset.
  • a high-level gain signal G1 is output (FIG. 3 (h)).
  • the amplifier circuit 84 has a second gain larger than the first gain with respect to the pixel value of each pixel in the image signal F21 (F2) for one frame input from the first synchronization signal generation circuit 7. Multiply the gain of 2. That is, the amplifier circuit 84 brightens the image based on the image signal F21 for one frame input in the period T4.
  • FIG. 4 is a diagram illustrating the effect of the first embodiment.
  • FIG. 4 is a time chart corresponding to FIG. 3, and even in the period T3'when the first synchronization signal generation circuit 7 is reset, the low frequency clock signal CL122 is the clock signal CL12 as in the other periods.
  • FIGS. 4A to 4I show the clock signal CL11, the synchronization signal VS2, the reset signal R1, the clock signal CL12, the synchronization signal VS1, the clock signal CL2, the image signal F1, the image signal F2, and The image signals F4 are shown respectively.
  • the signal processing device 8 resets the first synchronization signal generation circuit 7 when the synchronization deviation occurs. Therefore, the synchronization shift can be eliminated. That is, an image based on the image signal F1 generated by the imaging unit 6 can be appropriately displayed.
  • the low frequency clock signal CL122 is used as the clock signal CL12 to generate the first synchronization signal as in the other periods. It is assumed that the input is made to the circuit 7. In this case, since the operation of the first synchronization signal generation circuit 7 cannot be accelerated by the clock signal CL12, the operation from the start of the reset to the completion of the reset is completed.
  • the period T3' becomes longer.
  • the period T3' is a period twice the vertical synchronization period (the period between adjacent pulses) based on the synchronization signal VS2.
  • the image signal F2 is not output from the first synchronization signal generation circuit 7 during the period T3'. That is, when the period T3'is long, the period during which the image is not displayed on the display device 4 becomes long.
  • the signal processing device 8 is a selector circuit 83 that raises the frequency of the clock signal CL12 higher than other periods in the period T3 in which the first synchronization signal generation circuit 7 is reset.
  • the operation of the first synchronization signal generation circuit 7 can be accelerated by the clock signal CL12, and the period T3 for completing the reset after the first synchronization signal generation circuit 7 starts the reset is set.
  • the period T3 is a vertical synchronization period (period between adjacent pulses) based on the synchronization signal VS2. That is, since the period T3 can be shortened, the period during which the image is not displayed on the display device 4 can be shortened.
  • the image signal F2 for one frame is an image signal generated by accumulating electric charges in a vertical synchronization period (a period between adjacent pulses) based on the synchronization signal VS2.
  • the image signal F21 for one frame input to the signal processing device 8 in the period T4 is an image generated by accumulating charges in the short period T2 with respect to the image signal F2 for another frame. It is a signal. Therefore, the brightness of the image based on the image signal F21 is relatively dark.
  • the signal processing device 8 according to the first embodiment provides an amplifier circuit 84 that makes an image based on the image signal F21 for one frame input in the period T4 brighter than an image based on the image signal F2 of another frame. Be prepared. Therefore, the image based on the image signal F21 can be brightened and an appropriate image can be displayed.
  • the imaging unit 6 has a configuration in which the function of transmitting and receiving a synchronization signal is removed. Therefore, the size of the imaging unit 6 can be reduced, and the diameter of the insertion unit 21 provided with the imaging unit 6 can be reduced.
  • FIG. 5 is a diagram corresponding to FIG. 2, and is a block diagram showing a configuration of a main part of the endoscope system 1A according to the second embodiment.
  • the signal processing device 8 is provided with the endoscope system 1 (FIG. 2) described in the above-described first embodiment.
  • the amplifier circuit 84 that has been used is omitted.
  • the endoscope system 1A is provided with an amplifier circuit 84A having the same function as the amplifier circuit 84.
  • the amplifier circuit 84A is provided on a line between the imaging unit 6 and the first synchronization signal generation circuit 7, and an image signal is transmitted on the line. That is, the amplifier circuit 84A amplifies the image signal F1 output from the imaging unit 6 by the first gain during the period in which the low-level gain signal G1 is input from the reset circuit 81. Then, the amplifier circuit 84A outputs the amplified image signal F1 to the first synchronous signal generation circuit 7. On the other hand, the amplifier circuit 84A amplifies the image signal F1 by a second gain larger than the first gain during the period when the high level gain signal G1 is input from the reset circuit 81. Then, the amplifier circuit 84A outputs the amplified image signal F1 to the first synchronous signal generation circuit 7.
  • the image signal F1 is an analog signal and the image signal F2 is a digital signal.
  • the image signal F1 is an analog signal
  • the image signal F2 is a digital signal.
  • FIG. 6 is a diagram corresponding to FIG. 2, and is a block diagram showing a configuration of a main part of the endoscope system 1B according to the third embodiment.
  • FIG. 7 is a time chart corresponding to FIG. 3, which is a time chart showing the operation of the endoscope system 1B. Specifically, FIGS.
  • FIG. 7 (a) to 7 (k) show the clock signal CL11, the synchronization signal VS2, the reset signal R1, the select signal SE1, the clock signal CL12, the synchronization signal VS1, the light amount control signal LC, and the image signal F1.
  • the image signal F2 and the image signal F4 are shown, respectively.
  • the signal processing device 8 is provided with the endoscope system 1 (FIG. 2) described in the above-described first embodiment.
  • the amplifier circuit 84 that has been used is omitted.
  • the reset circuit 81 outputs a high-level light amount control signal LC to the second synchronization signal generation circuit 3 during the period T3 when the first synchronization signal generation circuit 7 is reset (FIG. 6 (h)).
  • the reset circuit 81 outputs a low-level light amount control signal LC to the second synchronization signal generation circuit 3.
  • the second synchronization signal generation circuit 3 controls the operation of the light source device 5 during the period T3 during which the high-level light amount control signal LC is input, and determines the amount of illumination light emitted from the light source device 5. Make it higher than other periods.
  • the amount of illumination light is made higher than other periods in the period T3. That is, since the amount of illumination light is increased even during the period T2 in which the charge can be accumulated for a short period, the image signal F21 for one frame input to the signal processing device 8 in the period T4. It is possible to brighten the image based on the above and display an appropriate image. Further, since it is not necessary to amplify the image signal, the image based on the image signal F21 can be brightened and an appropriate image can be displayed without amplifying the noise.
  • the reset circuit 81 determines whether or not the synchronization signal VS1 and the synchronization signal VS2 are synchronized, and when it is determined that the synchronization signal VS2 is not synchronized, the first synchronization signal.
  • the generation circuit 7 was reset.
  • the reset circuit 81 does not have to execute the determination. For example, when a user such as an operator determines that an appropriate image is not displayed on the display device 4, he / she operates an input unit (not shown) constituting the endoscope systems 1, 1A, 1B. conduct.
  • the reset circuit 81 resets the first synchronization signal generation circuit 7 in response to the operation. That is, the function of determining whether or not the synchronization signal VS1 and the synchronization signal VS2 are synchronized may be removed from the reset circuit 81 (signal processing device 8).
  • the signal processing device 8 is configured separately from the second synchronization signal generation circuit 3, but the present invention is not limited to this, and the signal processing device 8 is included in the second synchronization signal generation circuit 3. It may be installed in. Similarly, the signal processing device 8 is configured separately from the first synchronization signal generation circuit 7, but the present invention is not limited to this, and the signal processing device 8 may be mounted in the first synchronization signal generation circuit 7. ..

Abstract

This signal processing device 8 comprises a processor composed of at least one piece of hardware. The processor resets a first synchronization signal generation circuit 7, which receives the input of a clock signal CL12 and outputs a first synchronization signal VS1, if the first synchronization signal VS1 from the first synchronization signal generation circuit 7 and a second synchronization signal VS2 output from a second synchronization signal generation circuit 3 are not synchronized, and increases the frequency of the clock signal CL12 so as to be higher during the resetting period of the first synchronization signal generation circuit 7 than during other periods.

Description

信号処理装置、内視鏡システム、及び信号処理方法Signal processing equipment, endoscopic systems, and signal processing methods
　本発明は、信号処理装置、内視鏡システム、及び信号処理方法に関する。 The present invention relates to a signal processing device, an endoscope system, and a signal processing method.
　従来、先端に撮像部が設けられ、被検体内に挿入される内視鏡と、当該撮像部からの画像信号を処理するプロセッサとを備えた内視鏡システムが知られている。
　このような内視鏡システムでは、プロセッサは、撮像部を動作させるためのクロック信号と、当該撮像部から１フレーム毎に画像信号を取得するタイミングを示す同期信号（以下、第２の同期信号と記載）とを当該撮像部に対して出力する。そして、撮像部は、クロック信号に応じて動作するとともに、第２の同期信号に基づくタイミングで画像信号をプロセッサに対して出力する。 Conventionally, there is known an endoscope system in which an imaging unit is provided at the tip and an endoscope inserted into a subject and a processor for processing an image signal from the imaging unit are provided.
In such an endoscope system, the processor includes a clock signal for operating the imaging unit and a synchronization signal indicating the timing of acquiring an image signal from the imaging unit for each frame (hereinafter, a second synchronization signal). The description) is output to the imaging unit. Then, the imaging unit operates in response to the clock signal and outputs an image signal to the processor at a timing based on the second synchronization signal.
　ところで、近年では、撮像部を小型化するために、当該撮像部の機能から、同期信号を送受信する機能を取り除いた構成が提案されている（例えば、特許文献１参照）。
　特許文献１に記載の技術では、撮像部において、画像信号から同期信号を生成させるために、当該画像信号に電圧レベルの変化を設ける。そして、当該技術では、当該電圧レベルの変化に基づいて、１フレーム毎に当該画像信号が伝送されてきたタイミングを示す第１の同期信号を生成する同期信号生成部を設け、当該同期信号生成部から当該第１の同期信号をプロセッサに対して出力している。 By the way, in recent years, in order to reduce the size of the imaging unit, a configuration has been proposed in which the function of transmitting and receiving a synchronization signal is removed from the function of the imaging unit (see, for example, Patent Document 1).
In the technique described in Patent Document 1, in order to generate a synchronization signal from an image signal in the imaging unit, a change in voltage level is provided in the image signal. Then, in the present technology, a synchronization signal generation unit that generates a first synchronization signal indicating the timing at which the image signal has been transmitted is provided for each frame based on the change in the voltage level, and the synchronization signal generation unit is provided. Is outputting the first synchronization signal to the processor.
米国特許第９３１９６０３号U.S. Pat. No. 9,319,603
　ここで、撮像部によって生成された画像信号に基づく画像を適切に表示するためには、同期信号生成部によって生成される第１の同期信号と、プロセッサによって生成される第２の同期信号とを同期させる必要がある。
　そして、内視鏡システムでは、電気メスやスネア等の処置具を高出力で使用すると、撮像部に入力されるクロック信号や当該撮像部から出力された画像信号が当該処置具からの外乱の影響を受ける場合がある。このような場合には、画像信号における電圧レベルの変化に基づいて生成される第１の同期信号が影響を受け、当該第１の同期信号と第２の同期信号との同期ずれが発生する。すなわち、撮像部によって生成された画像信号に基づく画像を適切に表示することができない。
　そこで、適切な画像を表示することが可能となる技術が要望されている。 Here, in order to properly display an image based on the image signal generated by the imaging unit, the first synchronization signal generated by the synchronization signal generation unit and the second synchronization signal generated by the processor are used. Need to be synchronized.
Then, in the endoscope system, when a treatment tool such as an electric knife or a snare is used at a high output, the clock signal input to the imaging unit and the image signal output from the imaging unit are affected by the disturbance from the treatment tool. May receive. In such a case, the first synchronization signal generated based on the change in the voltage level in the image signal is affected, and the synchronization shift between the first synchronization signal and the second synchronization signal occurs. That is, it is not possible to properly display an image based on the image signal generated by the imaging unit.
Therefore, there is a demand for a technique capable of displaying an appropriate image.
　本発明は、上記に鑑みてなされたものであって、適切な画像を表示することが可能となる信号処理装置、信号処理方法、及び内視鏡システムを提供することを目的とする。 The present invention has been made in view of the above, and an object of the present invention is to provide a signal processing device, a signal processing method, and an endoscopic system capable of displaying an appropriate image.
　上述した課題を解決し、目的を達成するために、本発明に係る信号処理装置は、少なくとも１つ以上のハードウェアから成るプロセッサを備え、前記プロセッサは、クロック信号が入力され、第１の同期信号を出力する第１の同期信号生成回路からの前記第１の同期信号と、第２の同期信号生成回路から出力された第２の同期信号との同期が取れていない場合に、前記第１の同期信号生成回路をリセットし、前記第１の同期信号生成回路がリセットされる期間において、前記クロック信号の周波数を他の期間よりも高くする。 In order to solve the above-mentioned problems and achieve the object, the signal processing apparatus according to the present invention includes a processor consisting of at least one hardware, and the processor is input with a clock signal and is first synchronized. When the first synchronization signal from the first synchronization signal generation circuit that outputs the signal and the second synchronization signal output from the second synchronization signal generation circuit are not synchronized, the first synchronization signal is not synchronized. The synchronization signal generation circuit of the above is reset, and the frequency of the clock signal is made higher than the other periods in the period in which the first synchronization signal generation circuit is reset.
　本発明に係る内視鏡システムは、被検体内に挿入される内視鏡と、少なくとも１つ以上のハードウェアから成るプロセッサと、を備え、前記プロセッサは、クロック信号が入力され、第１の同期信号を出力する第１の同期信号生成回路からの前記第１の同期信号と、第２の同期信号生成回路から出力された第２の同期信号との同期が取れていない場合に、前記第１の同期信号生成回路をリセットし、前記第１の同期信号生成回路がリセットされる期間において、前記クロック信号の周波数を他の期間よりも高くする。 The endoscopic system according to the present invention includes an endoscope inserted into a subject and a processor including at least one piece of hardware, wherein a clock signal is input to the processor, and the first type of processor comprises one or more pieces of hardware. When the first synchronization signal from the first synchronization signal generation circuit that outputs the synchronization signal and the second synchronization signal output from the second synchronization signal generation circuit are not synchronized, the first synchronization signal is not synchronized. The synchronization signal generation circuit of 1 is reset, and the frequency of the clock signal is set higher than the other periods in the period in which the first synchronization signal generation circuit is reset.
　本発明に係る信号処理方法は、少なくとも１つ以上のハードウェアから成るプロセッサが実行する信号処理方法であって、クロック信号が入力され、第１の同期信号を出力する第１の同期信号生成回路からの前記第１の同期信号と、第２の同期信号生成回路から出力された第２の同期信号との同期が取れていない場合に、前記第１の同期信号生成回路をリセットし、前記第１の同期信号生成回路がリセットされる期間において、前記クロック信号の周波数を他の期間よりも高くする。 The signal processing method according to the present invention is a signal processing method executed by a processor composed of at least one hardware, and is a first synchronization signal generation circuit in which a clock signal is input and a first synchronization signal is output. When the first synchronization signal from the above and the second synchronization signal output from the second synchronization signal generation circuit are not synchronized, the first synchronization signal generation circuit is reset and the first synchronization signal generation circuit is reset. In the period when the synchronization signal generation circuit of 1 is reset, the frequency of the clock signal is made higher than the other periods.
　本発明に係る信号処理装置、信号処理方法、及び内視鏡システムによれば、適切な画像を表示することが可能となる。 According to the signal processing device, the signal processing method, and the endoscope system according to the present invention, it is possible to display an appropriate image.
図１は、実施の形態１に係る内視鏡システムの構成を示す図である。FIG. 1 is a diagram showing a configuration of an endoscope system according to a first embodiment. 図２は、内視鏡システムの要部の構成を示すブロック図である。FIG. 2 is a block diagram showing a configuration of a main part of the endoscope system. 図３は、内視鏡システムの動作を示すタイムチャートである。FIG. 3 is a time chart showing the operation of the endoscopic system. 図４は、実施の形態１の効果を説明する図である。FIG. 4 is a diagram illustrating the effect of the first embodiment. 図５は、実施の形態２に係る内視鏡システムの要部の構成を示すブロック図である。FIG. 5 is a block diagram showing a configuration of a main part of the endoscope system according to the second embodiment. 図６は、実施の形態３に係る内視鏡システムの要部の構成を示すブロック図である。FIG. 6 is a block diagram showing a configuration of a main part of the endoscope system according to the third embodiment. 図７は、内視鏡システムの動作を示すタイムチャートである。FIG. 7 is a time chart showing the operation of the endoscopic system.
　以下に、図面を参照して、本発明を実施するための形態（以下、実施の形態）について説明する。なお、以下に説明する実施の形態によって本発明が限定されるものではない。さらに、図面の記載において、同一の部分には同一の符号を付している。 Hereinafter, embodiments for carrying out the present invention (hereinafter referred to as embodiments) will be described with reference to the drawings. The present invention is not limited to the embodiments described below. Further, in the description of the drawings, the same parts are designated by the same reference numerals.
（実施の形態１）
　〔内視鏡システムの構成〕
　図１は、本実施の形態１に係る内視鏡システム１の構成を示す図である。
　内視鏡システム１は、例えば医療分野において用いられ、被検体内（生体内）を観察するシステムである。この内視鏡システム１は、図１に示すように、内視鏡２と、第２の同期信号生成回路３と、表示装置４と、光源装置５とを備える。 (Embodiment 1)
[Configuration of endoscopy system]
FIG. 1 is a diagram showing a configuration of an endoscope system 1 according to the first embodiment.
The endoscope system 1 is used in the medical field, for example, and is a system for observing the inside of a subject (in vivo). As shown in FIG. 1, the endoscope system 1 includes an endoscope 2, a second synchronization signal generation circuit 3, a display device 4, and a light source device 5.
　内視鏡２は、一部が生体内に挿入され、当該生体内から反射された被写体像を撮像し、当該撮像により生成した画像信号を出力する。この内視鏡２は、図１に示すように、挿入部２１と、操作部２２と、ユニバーサルコード２３と、コネクタ部２４とを備える。
　挿入部２１は、少なくとも一部が可撓性を有し、生体内に挿入される部分である。この挿入部２１において、先端部分２１１（図１）には、撮像部６（図２参照）が設けられている。
　なお、撮像部６の詳細な構成については、後述する「内視鏡システムの要部の構成」において説明する。 The endoscope 2 is partially inserted into a living body, images a subject image reflected from the living body, and outputs an image signal generated by the imaging. As shown in FIG. 1, the endoscope 2 includes an insertion portion 21, an operation portion 22, a universal cord 23, and a connector portion 24.
The insertion portion 21 is a portion that has at least a part of flexibility and is inserted into the living body. In the insertion portion 21, the tip portion 211 (FIG. 1) is provided with an imaging portion 6 (see FIG. 2).
The detailed configuration of the imaging unit 6 will be described later in "Configuration of main parts of the endoscope system".
　操作部２２は、挿入部２１における基端部分に対して接続されている。そして、操作部２２は、内視鏡２に対する各種の操作を受け付ける。
　ユニバーサルコード２３は、操作部２２から挿入部２１の延在方向とは異なる方向に延在し、上述した画像信号等を伝送するケーブルや、光源装置５から出射された照明光を導光する光ファイバ等が配設されたコードである。
　コネクタ部２４は、ユニバーサルコード２３の端部に設けられ、第２の同期信号生成回路３及び光源装置５に対してそれぞれ着脱自在に接続される。本実施の形態１では、コネクタ部２４内には、第１の同期信号生成回路７（図２参照）と、信号処理装置８（図２参照）とが設けられている。
　なお、第１の同期信号生成回路７及び信号処理装置８の詳細な構成については、後述する「内視鏡システムの要部の構成」において説明する。 The operation unit 22 is connected to the base end portion of the insertion unit 21. Then, the operation unit 22 receives various operations on the endoscope 2.
The universal cord 23 extends from the operation unit 22 in a direction different from the extending direction of the insertion unit 21, and guides the cable for transmitting the above-mentioned image signal and the like and the illumination light emitted from the light source device 5. It is a cord in which a fiber or the like is arranged.
The connector portion 24 is provided at the end of the universal cord 23, and is detachably connected to the second synchronization signal generation circuit 3 and the light source device 5, respectively. In the first embodiment, the first synchronous signal generation circuit 7 (see FIG. 2) and the signal processing device 8 (see FIG. 2) are provided in the connector portion 24.
The detailed configuration of the first synchronization signal generation circuit 7 and the signal processing device 8 will be described in "Configuration of main parts of the endoscope system" described later.
　第２の同期信号生成回路３は、内視鏡システム１全体の動作を統括的に制御する。例えば、第２の同期信号生成回路３は、撮像部６から出力され、挿入部２１、操作部２２、ユニバーサルコード２３、及びコネクタ部２４を経由した後の画像信号に対して各種の画像処理を実行する。
　なお、第２の同期信号生成回路３の詳細な構成については、後述する「内視鏡システムの要部の構成」において説明する。
　表示装置４は、ＬＣＤ（Liquid　Crystal　Display）やＥＬ（Electro　Luminescence）ディスプレイ等であり、第２の同期信号生成回路３によって画像処理が実行された後の画像信号に基づく画像等を表示する。
　光源装置５は、本発明に係る光源部に相当する。この光源装置５は、例えばハロゲンランプや白色ＬＥＤ（Light　Emitting　Diode）等を含み、照明光を出射する。そして、光源装置５から出射された照明光は、コネクタ部２４、ユニバーサルコード２３、操作部２２、及び挿入部２１を経由した後、当該挿入部２１の先端部分２１１から生体内に向けて照射される。 The second synchronization signal generation circuit 3 comprehensively controls the operation of the entire endoscope system 1. For example, the second synchronization signal generation circuit 3 performs various image processing on the image signal output from the image pickup unit 6 and after passing through the insertion unit 21, the operation unit 22, the universal cord 23, and the connector unit 24. Run.
The detailed configuration of the second synchronization signal generation circuit 3 will be described in "Configuration of main parts of the endoscope system" described later.
The display device 4 is an LCD (Liquid Crystal Display), an EL (Electro Luminescence) display, or the like, and displays an image or the like based on an image signal after image processing is executed by the second synchronization signal generation circuit 3.
The light source device 5 corresponds to the light source unit according to the present invention. The light source device 5 includes, for example, a halogen lamp, a white LED (Light Emitting Diode), or the like, and emits illumination light. Then, the illumination light emitted from the light source device 5 passes through the connector portion 24, the universal cord 23, the operation portion 22, and the insertion portion 21, and is then irradiated from the tip portion 211 of the insertion portion 21 toward the living body. NS.
　〔内視鏡システムの要部の構成〕
　次に、内視鏡システム１の要部である撮像部６、第１の同期信号生成回路７、信号処理装置８、及び第２の同期信号生成回路３の構成について説明する。
　図２は、内視鏡システム１の要部の構成を示すブロック図である。
　撮像部６は、クロック信号ＣＬ２（図２）に応じて動作する。当該クロック信号ＣＬ２は、第１の同期信号生成回路７から出力され、ユニバーサルコード２３、操作部２２、及び挿入部２１を経由し、撮像部６に対して入力される。また、撮像部６は、挿入部２１の先端部分２１１から照射され、生体内から反射された照明光（被写体像）を撮像する。そして、撮像部６は、当該撮像によって得られた画像信号Ｆ１（図２）を出力する。ここで、撮像部６は、例えば特許文献１に記載の技術と同様に、第１の同期信号生成回路７に当該画像信号Ｆ１から同期信号ＶＳ１（図２）を生成させるために、当該画像信号Ｆ１に電圧レベルの変化を設ける。
　以上説明した撮像部６は、被写体像を受光することによって電気信号（アナログ信号）に変換するＣＣＤ（Charge　Coupled　Device）またはＣＭＯＳ（Complementary　Metal　Oxide　Semiconductor）等を含んで構成されている。 [Structure of the main parts of the endoscope system]
Next, the configurations of the imaging unit 6, the first synchronous signal generation circuit 7, the signal processing device 8, and the second synchronous signal generation circuit 3, which are the main parts of the endoscope system 1, will be described.
FIG. 2 is a block diagram showing a configuration of a main part of the endoscope system 1.
The imaging unit 6 operates in response to the clock signal CL2 (FIG. 2). The clock signal CL2 is output from the first synchronization signal generation circuit 7 and is input to the imaging unit 6 via the universal code 23, the operation unit 22, and the insertion unit 21. Further, the imaging unit 6 images the illumination light (subject image) that is irradiated from the tip portion 211 of the insertion unit 21 and reflected from the living body. Then, the imaging unit 6 outputs the image signal F1 (FIG. 2) obtained by the imaging. Here, the imaging unit 6 causes the first synchronization signal generation circuit 7 to generate the synchronization signal VS1 (FIG. 2) from the image signal F1 in the same manner as the technique described in Patent Document 1, for example. A change in voltage level is provided in F1.
The imaging unit 6 described above includes a CCD (Charge Coupled Device), a CMOS (Complementary Metal Oxide Semiconductor), or the like that converts a subject image into an electric signal (analog signal) by receiving the subject image.
　第１の同期信号生成回路７は、ＡＦＥ（Analog　Front　End）によって構成されている。また、第１の同期信号生成回路７は、アナログ信号をデジタル信号に変換（Ａ／Ｄ変換）する回路を含む。さらに、第１の同期信号生成回路７は、信号処理装置８から入力したクロック信号ＣＬ１２（図２）に基づいて、クロック信号ＣＬ２を生成する。そして、第１の同期信号生成回路７は、撮像部６に対して当該クロック信号ＣＬ２を出力する。また、第１の同期信号生成回路７に対して、撮像部６から出力され、挿入部２１、操作部２２、及びユニバーサルコード２３を経由した後の画像信号Ｆ１が入力される。そして、第１の同期信号生成回路７は、当該画像信号Ｆ１に対して所定の信号処理（例えばＡ／Ｄ変換等）を実行することによって画像信号Ｆ２（図２）を生成する。さらに、第１の同期信号生成回路７は、例えば特許文献１に記載の技術と同様に、入力した画像信号Ｆ１における電圧レベルの変化に基づいて、１フレーム毎に当該画像信号Ｆ１が伝送されてきたタイミングを示す同期信号ＶＳ１（図２）を生成する。当該同期信号ＶＳ１は、本発明に係る第１の同期信号に相当する。 The first synchronization signal generation circuit 7 is composed of AFE (Analog Front End). Further, the first synchronization signal generation circuit 7 includes a circuit that converts an analog signal into a digital signal (A / D conversion). Further, the first synchronization signal generation circuit 7 generates the clock signal CL2 based on the clock signal CL12 (FIG. 2) input from the signal processing device 8. Then, the first synchronization signal generation circuit 7 outputs the clock signal CL2 to the imaging unit 6. Further, the image signal F1 that is output from the imaging unit 6 and has passed through the insertion unit 21, the operation unit 22, and the universal code 23 is input to the first synchronization signal generation circuit 7. Then, the first synchronization signal generation circuit 7 generates the image signal F2 (FIG. 2) by executing a predetermined signal processing (for example, A / D conversion or the like) on the image signal F1. Further, in the first synchronization signal generation circuit 7, the image signal F1 is transmitted every frame based on the change in the voltage level in the input image signal F1, for example, as in the technique described in Patent Document 1. A synchronization signal VS1 (FIG. 2) indicating the timing is generated. The synchronization signal VS1 corresponds to the first synchronization signal according to the present invention.
　信号処理装置８は、ＦＰＧＡ（Field　Programmable　Gate　Array）等の少なくとも１つ以上のハードウェアから成るプロセッサを備える。この信号処理装置８は、図２に示すように、リセット回路８１と、ＰＬＬ（Phase　Locked　Loop）回路８２と、セレクタ回路８３と、増幅回路８４と、映像処理回路８５とを備える。 The signal processing device 8 includes a processor composed of at least one or more hardware such as an FPGA (Field Programmable Gate Array). As shown in FIG. 2, the signal processing device 8 includes a reset circuit 81, a PLL (Phase Locked Loop) circuit 82, a selector circuit 83, an amplifier circuit 84, and a video processing circuit 85.
　リセット回路８１は、第１の同期信号生成回路７から出力された同期信号ＶＳ１と、第２の同期信号生成回路３によって生成された同期信号ＶＳ２との同期が取れているか否かを判定する。例えば、リセット回路８１は、同期信号ＶＳ１に基づくパルスと同期信号ＶＳ２に基づくパルスとが異なる時刻に立ち上がる際に、同期信号ＶＳ１と同期信号ＶＳ２との同期が取れていないと判定する。そして、リセット回路８１は、同期信号ＶＳ１及び同期信号ＶＳ２の同期が取れていないと判定した場合に、当該判定した後に同期信号ＶＳ２に基づくパルスが最初に立ち上がる時点からの一定の期間、第１の同期信号生成回路７に対してハイレベルのリセット信号Ｒ１（図２）を出力する。なお、当該期間以外の期間では、リセット回路８１は、第１の同期信号生成回路７に対してローレベルのリセット信号Ｒ１を出力する。第１の同期信号生成回路７に対してハイレベルのリセット信号Ｒ１が出力されると、当該第１の同期信号生成回路７と撮像部６とは、リセットを開始する。また、リセット回路８１は、同期信号ＶＳ１及び同期信号ＶＳ２の同期が取れていないと判定した場合に、当該判定した後に同期信号ＶＳ２に基づくパルスが最初に立ち上がる時点から同期が取れたと判定するまでの期間、セレクタ回路８３に対してハイレベルのセレクト信号ＳＥ１（図２）を出力する。なお、当該期間以外の期間では、リセット回路８１は、セレクタ回路８３に対してローレベルのセレクト信号ＳＥ１を出力する。さらに、リセット回路８１は、同期信号ＶＳ１及び同期信号ＶＳ２の同期が取れていないと判定した場合に、当該判定した後に同期信号ＶＳ２に基づくパルスが最初に立ち上がる時点から、第１の同期信号生成回路７がリセットされた後、当該撮像部６から１フレーム分の画像信号Ｆ１が出力されるまでの期間、増幅回路８４に対してハイレベルのゲイン信号Ｇ１（図２）を出力する。なお、当該期間以外の期間では、リセット回路８１は、増幅回路８４に対してローレベルのゲイン信号Ｇ１を出力する。 The reset circuit 81 determines whether or not the synchronization signal VS1 output from the first synchronization signal generation circuit 7 and the synchronization signal VS2 generated by the second synchronization signal generation circuit 3 are synchronized. For example, the reset circuit 81 determines that the synchronization signal VS1 and the synchronization signal VS2 are not synchronized when the pulse based on the synchronization signal VS1 and the pulse based on the synchronization signal VS2 rise at different times. Then, when the reset circuit 81 determines that the synchronization signal VS1 and the synchronization signal VS2 are not synchronized, the reset circuit 81 is the first for a certain period from the time when the pulse based on the synchronization signal VS2 first rises after the determination. A high-level reset signal R1 (FIG. 2) is output to the synchronization signal generation circuit 7. In a period other than this period, the reset circuit 81 outputs a low-level reset signal R1 to the first synchronization signal generation circuit 7. When the high-level reset signal R1 is output to the first synchronization signal generation circuit 7, the first synchronization signal generation circuit 7 and the imaging unit 6 start resetting. Further, when the reset circuit 81 determines that the synchronization signal VS1 and the synchronization signal VS2 are not synchronized, the reset circuit 81 determines that the synchronization has been achieved from the time when the pulse based on the synchronization signal VS2 first rises after the determination. During the period, a high-level select signal SE1 (FIG. 2) is output to the selector circuit 83. In a period other than this period, the reset circuit 81 outputs a low-level select signal SE1 to the selector circuit 83. Further, when the reset circuit 81 determines that the synchronization signal VS1 and the synchronization signal VS2 are not synchronized, the reset circuit 81 is the first synchronization signal generation circuit from the time when the pulse based on the synchronization signal VS2 first rises after the determination. After the 7 is reset, a high-level gain signal G1 (FIG. 2) is output to the amplifier circuit 84 during the period until the image signal F1 for one frame is output from the imaging unit 6. In a period other than this period, the reset circuit 81 outputs a low-level gain signal G1 to the amplifier circuit 84.
　ＰＬＬ回路８２は、周波数シンセサイザであり、第２の同期信号生成回路３から出力されたクロック信号ＣＬ１１（図２）に基づいて、クロック信号ＣＬ１２１（図２）とクロック信号ＣＬ１２２（図２）とを生成する。ここで、クロック信号ＣＬ１２１は、クロック信号ＣＬ１２２に対して、周波数が高いクロック信号である。そして、ＰＬＬ回路８２は、クロック信号ＣＬ１２１とクロック信号ＣＬ１２２とをセレクタ回路８３に対して出力する。 The PLL circuit 82 is a frequency synthesizer, and based on the clock signal CL11 (FIG. 2) output from the second synchronization signal generation circuit 3, the clock signal CL121 (FIG. 2) and the clock signal CL122 (FIG. 2) are combined. Generate. Here, the clock signal CL121 is a clock signal having a higher frequency than the clock signal CL122. Then, the PLL circuit 82 outputs the clock signal CL121 and the clock signal CL122 to the selector circuit 83.
　セレクタ回路８３は、第２の同期信号生成回路３と第１の同期信号生成回路７との間のライン上に設けられており、当該ライン上でクロック信号が伝送される。また、セレクタ回路８３は、ＰＬＬ回路８２から出力されたクロック信号ＣＬ１２１とクロック信号ＣＬ１２２とのうち、一方のクロック信号を選択する。具体的に、セレクタ回路８３は、リセット回路８１からローレベルのセレクト信号ＳＥ１を入力している期間には、周波数の低いクロック信号ＣＬ１２２を選択する。そして、セレクタ回路８３は、当該クロック信号ＣＬ１２２をクロック信号ＣＬ１２として第１の同期信号生成回路７に対して出力する。一方、セレクタ回路８３は、リセット回路８１からハイレベルのセレクト信号ＳＥ１を入力している期間には、周波数の高いクロック信号ＣＬ１２１を選択する。そして、セレクタ回路８３は、当該クロック信号ＣＬ１２１をクロック信号ＣＬ１２として第１の同期信号生成回路７に対して出力する。 The selector circuit 83 is provided on a line between the second synchronization signal generation circuit 3 and the first synchronization signal generation circuit 7, and the clock signal is transmitted on the line. Further, the selector circuit 83 selects one of the clock signal CL121 and the clock signal CL122 output from the PLL circuit 82. Specifically, the selector circuit 83 selects the low-frequency clock signal CL122 during the period in which the low-level select signal SE1 is input from the reset circuit 81. Then, the selector circuit 83 outputs the clock signal CL 122 as the clock signal CL 12 to the first synchronization signal generation circuit 7. On the other hand, the selector circuit 83 selects the clock signal CL121 having a high frequency while the high-level select signal SE1 is being input from the reset circuit 81. Then, the selector circuit 83 outputs the clock signal CL121 as the clock signal CL12 to the first synchronization signal generation circuit 7.
　増幅回路８４は、第１の同期信号生成回路７と第２の同期信号生成回路３との間のライン上に設けられており、当該ライン上で画像信号が伝送される。また、増幅回路８４は、第１の同期信号生成回路７から出力された画像信号Ｆ２における各画素の画素値に対してゲインを乗算することによって、当該画像信号Ｆ２に基づく画像の明るさを調整する。具体的に、増幅回路８４は、リセット回路８１からローレベルのゲイン信号Ｇ１を入力している期間には、画像信号Ｆ２における各画素の画素値に対して第１のゲインを乗算することによって画像信号Ｆ３を生成する。一方、増幅回路８４は、リセット回路８１からハイレベルのゲイン信号Ｇ１を入力している期間には、画像信号Ｆ２における各画素の画素値に対して第１のゲインよりも大きい第２のゲインを乗算することによって画像信号Ｆ３を生成する。 The amplifier circuit 84 is provided on a line between the first synchronization signal generation circuit 7 and the second synchronization signal generation circuit 3, and the image signal is transmitted on the line. Further, the amplifier circuit 84 adjusts the brightness of the image based on the image signal F2 by multiplying the pixel value of each pixel in the image signal F2 output from the first synchronization signal generation circuit 7 by the gain. do. Specifically, the amplifier circuit 84 multiplies the pixel value of each pixel in the image signal F2 by the first gain during the period in which the low-level gain signal G1 is input from the reset circuit 81 to obtain an image. Generate signal F3. On the other hand, the amplifier circuit 84 obtains a second gain larger than the first gain with respect to the pixel value of each pixel in the image signal F2 during the period in which the high-level gain signal G1 is input from the reset circuit 81. The image signal F3 is generated by multiplying.
　映像処理回路８５は、増幅回路８４から出力された画像信号Ｆ３に対して各種の画像処理を実行することによって画像信号Ｆ４を生成する。 The image processing circuit 85 generates the image signal F4 by executing various image processing on the image signal F3 output from the amplifier circuit 84.
　第２の同期信号生成回路３は、ＣＰＵ（Central　Processing　Unit）やＦＰＧＡ等を含んで構成されている。この第２の同期信号生成回路３は、クロック信号ＣＬ１１と、１フレーム毎に画像信号Ｆ４を取得するタイミングを示す同期信号ＶＳ２（図２）とをそれぞれ生成し、信号処理装置８（ＰＬＬ回路８２及びリセット回路８１）に対してそれぞれ出力する。また、第２の同期信号生成回路３は、信号処理装置８（映像処理回路８５）から出力された画像信号Ｆ４に対して各種の画像処理を実行する。そして、当該各種の画像処理が実行された後の画像信号に基づく画像は、表示装置４に表示される。
　なお、以上説明したクロック信号ＣＬ１１、クロック信号ＣＬ１２１、クロック信号ＣＬ１２２、及びクロック信号ＣＬ１２は、本発明に係るクロック信号に相当する。また、同期信号ＶＳ２は、本発明に係る第２の同期信号に相当する。 The second synchronization signal generation circuit 3 includes a CPU (Central Processing Unit), an FPGA, and the like. The second synchronization signal generation circuit 3 generates a clock signal CL11 and a synchronization signal VS2 (FIG. 2) indicating the timing of acquiring the image signal F4 for each frame, and generates a signal processing device 8 (PLL circuit 82). And the reset circuit 81) are output respectively. Further, the second synchronization signal generation circuit 3 executes various image processing on the image signal F4 output from the signal processing device 8 (image processing circuit 85). Then, the image based on the image signal after the various image processes are executed is displayed on the display device 4.
The clock signal CL11, the clock signal CL121, the clock signal CL122, and the clock signal CL12 described above correspond to the clock signals according to the present invention. Further, the synchronization signal VS2 corresponds to the second synchronization signal according to the present invention.
　〔内視鏡システムの動作〕
　次に、内視鏡システム１の動作について説明する。なお、以下では、内視鏡システム１の要部である撮像部６、第１の同期信号生成回路７、信号処理装置８、及び第２の同期信号生成回路３の動作を主に説明する。
　図３は、内視鏡システム１の動作を示すタイムチャートである。具体的に、図３（ａ）～図３（ｋ）は、クロック信号ＣＬ１１、同期信号ＶＳ２、リセット信号Ｒ１、セレクト信号ＳＥ１、クロック信号ＣＬ１２、同期信号ＶＳ１、クロック信号ＣＬ２、ゲイン信号Ｇ１、画像信号Ｆ１、画像信号Ｆ２、及び画像信号Ｆ４をそれぞれ示している。 [Operation of endoscopic system]
Next, the operation of the endoscope system 1 will be described. In the following, the operations of the imaging unit 6, the first synchronization signal generation circuit 7, the signal processing device 8, and the second synchronization signal generation circuit 3, which are the main parts of the endoscope system 1, will be mainly described.
FIG. 3 is a time chart showing the operation of the endoscope system 1. Specifically, FIGS. 3A to 3K show the clock signal CL11, the synchronization signal VS2, the reset signal R1, the select signal SE1, the clock signal CL12, the synchronization signal VS1, the clock signal CL2, the gain signal G1, and the image. The signal F1, the image signal F2, and the image signal F4 are shown, respectively.
　以下では、時刻Ｐ１（図３）において、電気メスやスネア等の処置具を高出力で使用し、クロック信号ＣＬ２や画像信号Ｆ１が当該処置具からの外乱の影響を受けた場合を想定する。
　ここで、第１の同期信号生成回路７は、画像信号Ｆ１における電圧レベルの変化を検出することによって、１フレーム分のうち何データ目の画像信号Ｆ１が撮像部６から伝送されてきているかを推測する。そして、第１の同期信号生成回路７は、当該電圧レベルの変化に基づいて、１フレーム分の画像信号Ｆ１が伝送されたと推測したときに、同期信号ＶＳ１に基づくパルスを立ち上げる。上述した場合には、クロック信号ＣＬ２や画像信号Ｆ１が外乱の影響を受けたため、画像信号Ｆ１には、撮像部６によって生成された電圧レベルの変化以外の変化が発生する。そして、第１の同期信号生成回路７は、撮像部６によって生成された電圧レベルの変化以外の変化も検出してしまうため、誤った推測を行うこととなる。このため、同期信号ＶＳ１に基づくパルスは、時刻Ｐ１の後に同期信号ＶＳ２に基づくパルスが最初に立ち上がる時刻Ｐ２（図３）からずれた時刻Ｐ３（図３）に立ち上がる（図３（ｆ））。すなわち、リセット回路８１は、時刻Ｐ２において、同期信号ＶＳ１と同期信号ＶＳ２との同期が取れていないと判定する。 In the following, it is assumed that a treatment tool such as an electric knife or a snare is used at a high output at time P1 (FIG. 3), and the clock signal CL2 and the image signal F1 are affected by the disturbance from the treatment tool.
Here, the first synchronization signal generation circuit 7 detects the change in the voltage level in the image signal F1 to determine the data number of the image signal F1 in one frame transmitted from the image pickup unit 6. Infer. Then, the first synchronization signal generation circuit 7 raises a pulse based on the synchronization signal VS1 when it is estimated that one frame of the image signal F1 has been transmitted based on the change in the voltage level. In the above case, since the clock signal CL2 and the image signal F1 are affected by the disturbance, the image signal F1 undergoes a change other than the change in the voltage level generated by the imaging unit 6. Then, the first synchronization signal generation circuit 7 detects a change other than the change in the voltage level generated by the imaging unit 6, so that an erroneous guess is made. Therefore, the pulse based on the synchronization signal VS1 rises at the time P3 (FIG. 3) deviated from the time P2 (FIG. 3) at which the pulse based on the synchronization signal VS2 first rises after the time P1 (FIG. 3 (f)). That is, the reset circuit 81 determines that the synchronization signal VS1 and the synchronization signal VS2 are not synchronized at the time P2.
　そして、リセット回路８１は、時刻Ｐ２の後に同期信号ＶＳ２に基づくパルスが最初に立ち上がる時刻Ｐ４からの一定の期間Ｔ１、第１の同期信号生成回路７に対してハイレベルのリセット信号Ｒ１を出力する（図３（ｃ））。これによって、第１の同期信号生成回路７と撮像部６とは、リセットを開始する。当該期間Ｔ１は、撮像部６がリセットを開始してから当該リセットを完了するまでの期間である。ここで、図３において、期間Ｔ２は、撮像部６がリセットされた後、電荷を蓄積する期間である。また、期間Ｔ３は、第１の同期信号生成回路７がリセットを開始してから当該リセットを完了するまでの期間である。本実施の形態１では、当該期間Ｔ３は、同期信号ＶＳ２に基づく垂直同期期間（隣接するパルス間の期間）である。すなわち、時刻Ｐ４の後に同期信号ＶＳ２に基づくパルスが最初に立ち上がる時刻Ｐ５において、同期信号ＶＳ１と同期信号ＶＳ２との同期が取れる。 Then, the reset circuit 81 outputs a high-level reset signal R1 to the first synchronization signal generation circuit 7 for a certain period T1 from the time P4 at which the pulse based on the synchronization signal VS2 first rises after the time P2. (Fig. 3 (c)). As a result, the first synchronization signal generation circuit 7 and the imaging unit 6 start resetting. The period T1 is a period from the start of the reset by the imaging unit 6 to the completion of the reset. Here, in FIG. 3, the period T2 is a period during which the electric charge is accumulated after the imaging unit 6 is reset. Further, the period T3 is a period from the start of the reset of the first synchronization signal generation circuit 7 to the completion of the reset. In the first embodiment, the period T3 is a vertical synchronization period (a period between adjacent pulses) based on the synchronization signal VS2. That is, at the time P5 when the pulse based on the synchronization signal VS2 first rises after the time P4, the synchronization signal VS1 and the synchronization signal VS2 can be synchronized.
　また、リセット回路８１は、時刻Ｐ４から同期信号ＶＳ１と同期信号ＶＳ２との同期が取れたと判定するまでの期間Ｔ３、セレクタ回路８３に対してハイレベルのセレクト信号ＳＥ１を出力する（図３（ｄ））。これによって、セレクタ回路８３は、ＰＬＬ回路８２から出力されたクロック信号ＣＬ１２１とクロック信号ＣＬ１２２とのうち、周波数の高いクロック信号ＣＬ１２１を選択する。そして、セレクタ回路８３は、当該クロック信号ＣＬ１２１をクロック信号ＣＬ１２として第１の同期信号生成回路７に対して出力する（図３（ｅ））。すなわち、セレクタ回路８３は、第１の同期信号生成回路７がリセットされる期間Ｔ３において、クロック信号ＣＬ１２の周波数を他の期間よりも高くする。 Further, the reset circuit 81 outputs a high-level select signal SE1 to the selector circuit 83 during the period T3 from the time P4 until it is determined that the synchronization signal VS1 and the synchronization signal VS2 have been synchronized (FIG. 3 (d)). )). As a result, the selector circuit 83 selects the clock signal CL121 having a higher frequency from the clock signal CL121 and the clock signal CL122 output from the PLL circuit 82. Then, the selector circuit 83 outputs the clock signal CL121 as the clock signal CL12 to the first synchronization signal generation circuit 7 (FIG. 3E). That is, the selector circuit 83 makes the frequency of the clock signal CL12 higher than the other periods in the period T3 in which the first synchronization signal generation circuit 7 is reset.
　さらに、リセット回路８１は、時刻Ｐ４から、第１の同期信号生成回路７がリセットされた後、当該撮像部６から１フレーム分の画像信号Ｆ１が出力されるまでの期間Ｔ４、増幅回路８４に対してハイレベルのゲイン信号Ｇ１を出力する（図３（ｈ））。これによって、増幅回路８４は、期間Ｔ４において、第１の同期信号生成回路７から入力した１フレーム分の画像信号Ｆ２１（Ｆ２）における各画素の画素値に対して第１のゲインよりも大きい第２のゲインを乗算する。
　すなわち、増幅回路８４は、期間Ｔ４において入力した１フレーム分の画像信号Ｆ２１に基づく画像を明るくする。 Further, the reset circuit 81 is connected to the amplifier circuit 84 during the period T4 from the time P4 until the image signal F1 for one frame is output from the imaging unit 6 after the first synchronization signal generation circuit 7 is reset. On the other hand, a high-level gain signal G1 is output (FIG. 3 (h)). As a result, in the period T4, the amplifier circuit 84 has a second gain larger than the first gain with respect to the pixel value of each pixel in the image signal F21 (F2) for one frame input from the first synchronization signal generation circuit 7. Multiply the gain of 2.
That is, the amplifier circuit 84 brightens the image based on the image signal F21 for one frame input in the period T4.
　以上説明した本実施の形態１によれば、以下の効果を奏する。
　図４は、本実施の形態１の効果を説明する図である。なお、図４は、図３に対応したタイムチャートであって、第１の同期信号生成回路７がリセットされる期間Ｔ３´においても他の期間と同様に周波数の低いクロック信号ＣＬ１２２がクロック信号ＣＬ１２として第１の同期信号生成回路７に対して入力される場合を示したものである。具体的に、図４（ａ）～図４（ｉ）は、クロック信号ＣＬ１１、同期信号ＶＳ２、リセット信号Ｒ１、クロック信号ＣＬ１２、同期信号ＶＳ１、クロック信号ＣＬ２、画像信号Ｆ１、画像信号Ｆ２、及び画像信号Ｆ４をそれぞれ示している。 According to the first embodiment described above, the following effects are obtained.
FIG. 4 is a diagram illustrating the effect of the first embodiment. Note that FIG. 4 is a time chart corresponding to FIG. 3, and even in the period T3'when the first synchronization signal generation circuit 7 is reset, the low frequency clock signal CL122 is the clock signal CL12 as in the other periods. The case where the signal is input to the first synchronization signal generation circuit 7 is shown. Specifically, FIGS. 4A to 4I show the clock signal CL11, the synchronization signal VS2, the reset signal R1, the clock signal CL12, the synchronization signal VS1, the clock signal CL2, the image signal F1, the image signal F2, and The image signals F4 are shown respectively.
　ところで、上述したように、第１の同期信号生成回路７は、画像信号Ｆ１における電圧レベルの変化のみを基にして１フレーム分のうち何データ目の画像信号Ｆ１が撮像部６から伝送されてきているかを推測する。このため、外乱の影響を受けることによって同期信号ＶＳ１と同期信号ＶＳ２との同期ずれが発生した後、時間の経過によって、当該同期ずれが解消することはない。すなわち、当該同期ずれを解消するためには、第１の同期信号生成回路７と撮像部６とをリセットする必要がある。
　本実施の形態１に係る信号処理装置８は、当該同期ずれが発生した場合に、第１の同期信号生成回路７をリセットする。このため、当該同期ずれを解消することができる。すなわち、撮像部６によって生成された画像信号Ｆ１に基づく画像を適切に表示することができる。 By the way, as described above, in the first synchronization signal generation circuit 7, the image signal F1 of which data in one frame is transmitted from the imaging unit 6 based only on the change in the voltage level in the image signal F1. Guess if it is. Therefore, after a synchronization shift between the synchronization signal VS1 and the synchronization signal VS2 occurs due to the influence of the disturbance, the synchronization shift cannot be eliminated with the passage of time. That is, in order to eliminate the synchronization deviation, it is necessary to reset the first synchronization signal generation circuit 7 and the imaging unit 6.
The signal processing device 8 according to the first embodiment resets the first synchronization signal generation circuit 7 when the synchronization deviation occurs. Therefore, the synchronization shift can be eliminated. That is, an image based on the image signal F1 generated by the imaging unit 6 can be appropriately displayed.
　ここで、図４に示すように、第１の同期信号生成回路７がリセットされる期間Ｔ３´においても他の期間と同様に周波数の低いクロック信号ＣＬ１２２がクロック信号ＣＬ１２として第１の同期信号生成回路７に対して入力された場合を想定する。この場合には、第１の同期信号生成回路７の動作を当該クロック信号ＣＬ１２によって速めることができないため、当該第１の同期信号生成回路７がリセットを開始してから当該リセットを完了するまでの期間Ｔ３´が長くなる。例えば、期間Ｔ３´は、同期信号ＶＳ２に基づく垂直同期期間（隣接するパルス間の期間）の２倍の期間である。ここで、当該期間Ｔ３´には、第１の同期信号生成回路７から画像信号Ｆ２が出力されない。すなわち、当該期間Ｔ３´が長くなると、表示装置４に画像が表示されない期間が長くなることになる。 Here, as shown in FIG. 4, even in the period T3'when the first synchronization signal generation circuit 7 is reset, the low frequency clock signal CL122 is used as the clock signal CL12 to generate the first synchronization signal as in the other periods. It is assumed that the input is made to the circuit 7. In this case, since the operation of the first synchronization signal generation circuit 7 cannot be accelerated by the clock signal CL12, the operation from the start of the reset to the completion of the reset is completed. The period T3'becomes longer. For example, the period T3'is a period twice the vertical synchronization period (the period between adjacent pulses) based on the synchronization signal VS2. Here, the image signal F2 is not output from the first synchronization signal generation circuit 7 during the period T3'. That is, when the period T3'is long, the period during which the image is not displayed on the display device 4 becomes long.
　これに対して、本実施の形態１に係る信号処理装置８は、第１の同期信号生成回路７がリセットされる期間Ｔ３において、クロック信号ＣＬ１２の周波数を他の期間よりも高くするセレクタ回路８３を備える。このため、第１の同期信号生成回路７の動作を当該クロック信号ＣＬ１２によって速めることができ、当該第１の同期信号生成回路７がリセットを開始してから当該リセットを完了するための期間Ｔ３を短くすることができる。例えば、期間Ｔ３は、同期信号ＶＳ２に基づく垂直同期期間（隣接するパルス間の期間）である。すなわち、当該期間Ｔ３を短くすることができるため、表示装置４に画像が表示されない期間を短くすることができる。 On the other hand, the signal processing device 8 according to the first embodiment is a selector circuit 83 that raises the frequency of the clock signal CL12 higher than other periods in the period T3 in which the first synchronization signal generation circuit 7 is reset. To be equipped. Therefore, the operation of the first synchronization signal generation circuit 7 can be accelerated by the clock signal CL12, and the period T3 for completing the reset after the first synchronization signal generation circuit 7 starts the reset is set. Can be shortened. For example, the period T3 is a vertical synchronization period (period between adjacent pulses) based on the synchronization signal VS2. That is, since the period T3 can be shortened, the period during which the image is not displayed on the display device 4 can be shortened.
　ところで、１フレーム分の画像信号Ｆ２は、同期信号ＶＳ２に基づく垂直同期期間（隣接するパルス間の期間）において電荷を蓄積することによって生成された画像信号である。一方、期間Ｔ４において信号処理装置８に対して入力される１フレーム分の画像信号Ｆ２１は、他の１フレーム分の画像信号Ｆ２に対して短い期間Ｔ２において電荷を蓄積することによって生成された画像信号である。このため、当該画像信号Ｆ２１に基づく画像は、明るさが比較的に暗いものとなる。
　ここで、本実施の形態１に係る信号処理装置８は、期間Ｔ４において入力した１フレーム分の画像信号Ｆ２１に基づく画像を他のフレームの画像信号Ｆ２に基づく画像よりも明るくする増幅回路８４を備える。このため、当該画像信号Ｆ２１に基づく画像を明るくし、適切な画像を表示することができる。 By the way, the image signal F2 for one frame is an image signal generated by accumulating electric charges in a vertical synchronization period (a period between adjacent pulses) based on the synchronization signal VS2. On the other hand, the image signal F21 for one frame input to the signal processing device 8 in the period T4 is an image generated by accumulating charges in the short period T2 with respect to the image signal F2 for another frame. It is a signal. Therefore, the brightness of the image based on the image signal F21 is relatively dark.
Here, the signal processing device 8 according to the first embodiment provides an amplifier circuit 84 that makes an image based on the image signal F21 for one frame input in the period T4 brighter than an image based on the image signal F2 of another frame. Be prepared. Therefore, the image based on the image signal F21 can be brightened and an appropriate image can be displayed.
　また、撮像部６は、同期信号を送受信する機能を取り除いた構成である。このため、撮像部６を小型化し、これによって、当該撮像部６が設けられる挿入部２１を細径化することができる。 Further, the imaging unit 6 has a configuration in which the function of transmitting and receiving a synchronization signal is removed. Therefore, the size of the imaging unit 6 can be reduced, and the diameter of the insertion unit 21 provided with the imaging unit 6 can be reduced.
（実施の形態２）
　次に、本実施の形態２について説明する。
　以下の説明では、上述した実施の形態１と同様の構成には同一符号を付し、その詳細な構成は省略または簡略化する。
　図５は、図２に対応した図であって、本実施の形態２に係る内視鏡システム１Ａの要部の構成を示すブロック図である。
　本実施の形態２に係る内視鏡システム１Ａでは、図５に示すように、上述した実施の形態１において説明した内視鏡システム１（図２）に対して、信号処理装置８に設けられていた増幅回路８４を省略している。そして、当該内視鏡システム１Ａでは、当該増幅回路８４と同一の機能を有する増幅回路８４Ａが設けられている。当該増幅回路８４Ａは、撮像部６と第１の同期信号生成回路７との間のライン上に設けられており、当該ライン上で画像信号が伝送される。すなわち、増幅回路８４Ａは、リセット回路８１からローレベルのゲイン信号Ｇ１を入力している期間には、撮像部６から出力された画像信号Ｆ１を第１のゲインによって増幅する。そして、増幅回路８４Ａは、増幅した後の画像信号Ｆ１を第１の同期信号生成回路７に出力する。一方、増幅回路８４Ａは、リセット回路８１からハイレベルのゲイン信号Ｇ１を入力している期間には、画像信号Ｆ１を第１のゲインよりも大きい第２のゲインによって増幅する。そして、増幅回路８４Ａは、増幅した後の画像信号Ｆ１を第１の同期信号生成回路７に出力する。 (Embodiment 2)
Next, the second embodiment will be described.
In the following description, the same components as those in the first embodiment will be designated by the same reference numerals, and the detailed configurations thereof will be omitted or simplified.
FIG. 5 is a diagram corresponding to FIG. 2, and is a block diagram showing a configuration of a main part of the endoscope system 1A according to the second embodiment.
In the endoscope system 1A according to the second embodiment, as shown in FIG. 5, the signal processing device 8 is provided with the endoscope system 1 (FIG. 2) described in the above-described first embodiment. The amplifier circuit 84 that has been used is omitted. The endoscope system 1A is provided with an amplifier circuit 84A having the same function as the amplifier circuit 84. The amplifier circuit 84A is provided on a line between the imaging unit 6 and the first synchronization signal generation circuit 7, and an image signal is transmitted on the line. That is, the amplifier circuit 84A amplifies the image signal F1 output from the imaging unit 6 by the first gain during the period in which the low-level gain signal G1 is input from the reset circuit 81. Then, the amplifier circuit 84A outputs the amplified image signal F1 to the first synchronous signal generation circuit 7. On the other hand, the amplifier circuit 84A amplifies the image signal F1 by a second gain larger than the first gain during the period when the high level gain signal G1 is input from the reset circuit 81. Then, the amplifier circuit 84A outputs the amplified image signal F1 to the first synchronous signal generation circuit 7.
　以上説明した本実施の形態２によれば、上述した実施の形態１と同様の効果の他、以下の効果がある。
　ところで、第１の同期信号生成回路７がアナログ信号をデジタル信号に変換するため、画像信号Ｆ１はアナログ信号であり、画像信号Ｆ２はデジタル信号である。
　アナログ信号である画像信号Ｆ１を増幅することで、デジタル信号である画像信号Ｆ２を増幅する場合と比べて、色と明るさのコントラストを維持した画像を表示することができる。 According to the second embodiment described above, in addition to the same effects as those of the first embodiment described above, there are the following effects.
By the way, since the first synchronization signal generation circuit 7 converts an analog signal into a digital signal, the image signal F1 is an analog signal and the image signal F2 is a digital signal.
By amplifying the image signal F1 which is an analog signal, it is possible to display an image in which the contrast between color and brightness is maintained as compared with the case where the image signal F2 which is a digital signal is amplified.
（実施の形態３）
　次に、本実施の形態３について説明する。
　以下の説明では、上述した実施の形態１と同様の構成には同一符号を付し、その詳細な構成は省略または簡略化する。
　図６は、図２に対応した図であって、本実施の形態３に係る内視鏡システム１Ｂの要部の構成を示すブロック図である。図７は、図３に対応したタイムチャートであって、内視鏡システム１Ｂの動作を示すタイムチャートである。具体的に、図７（ａ）～図７（ｋ）は、クロック信号ＣＬ１１、同期信号ＶＳ２、リセット信号Ｒ１、セレクト信号ＳＥ１、クロック信号ＣＬ１２、同期信号ＶＳ１、光量制御信号ＬＣ、画像信号Ｆ１、画像信号Ｆ２、及び画像信号Ｆ４をそれぞれ示している。 (Embodiment 3)
Next, the third embodiment will be described.
In the following description, the same components as those in the first embodiment will be designated by the same reference numerals, and the detailed configurations thereof will be omitted or simplified.
FIG. 6 is a diagram corresponding to FIG. 2, and is a block diagram showing a configuration of a main part of the endoscope system 1B according to the third embodiment. FIG. 7 is a time chart corresponding to FIG. 3, which is a time chart showing the operation of the endoscope system 1B. Specifically, FIGS. 7 (a) to 7 (k) show the clock signal CL11, the synchronization signal VS2, the reset signal R1, the select signal SE1, the clock signal CL12, the synchronization signal VS1, the light amount control signal LC, and the image signal F1. The image signal F2 and the image signal F4 are shown, respectively.
　本実施の形態３に係る内視鏡システム１Ｂでは、図６に示すように、上述した実施の形態１において説明した内視鏡システム１（図２）に対して、信号処理装置８に設けられていた増幅回路８４を省略している。また、リセット回路８１は、第１の同期信号生成回路７がリセットされる期間Ｔ３において、第２の同期信号生成回路３に対してハイレベルの光量制御信号ＬＣを出力する（図６（ｈ））。なお、期間Ｔ３以外の期間では、リセット回路８１は、第２の同期信号生成回路３に対してローレベルの光量制御信号ＬＣを出力する。そして、第２の同期信号生成回路３は、ハイレベルの光量制御信号ＬＣを入力している期間Ｔ３において、光源装置５の動作を制御し、当該光源装置５から出射される照明光の光量を他の期間よりも高くする。 In the endoscope system 1B according to the third embodiment, as shown in FIG. 6, the signal processing device 8 is provided with the endoscope system 1 (FIG. 2) described in the above-described first embodiment. The amplifier circuit 84 that has been used is omitted. Further, the reset circuit 81 outputs a high-level light amount control signal LC to the second synchronization signal generation circuit 3 during the period T3 when the first synchronization signal generation circuit 7 is reset (FIG. 6 (h)). ). In a period other than the period T3, the reset circuit 81 outputs a low-level light amount control signal LC to the second synchronization signal generation circuit 3. Then, the second synchronization signal generation circuit 3 controls the operation of the light source device 5 during the period T3 during which the high-level light amount control signal LC is input, and determines the amount of illumination light emitted from the light source device 5. Make it higher than other periods.
　以上説明した本実施の形態３によれば、上述した実施の形態１と同様の効果の他、以下の効果を奏する。
　本実施の形態３に係る内視鏡システム１Ｂでは、期間Ｔ３において、照明光の光量を他の期間よりも高くする。すなわち、電荷を蓄積することができる期間が短い期間Ｔ２であっても、照明光の光量が高められているため、期間Ｔ４において信号処理装置８に対して入力される１フレーム分の画像信号Ｆ２１に基づく画像を明るくし、適切な画像を表示することができる。
　また、画像信号を増幅させる必要がないため、ノイズを増幅させることなく、画像信号Ｆ２１に基づく画像を明るくし、適切な画像を表示することができる。 According to the third embodiment described above, in addition to the same effects as those of the first embodiment described above, the following effects are exhibited.
In the endoscope system 1B according to the third embodiment, the amount of illumination light is made higher than other periods in the period T3. That is, since the amount of illumination light is increased even during the period T2 in which the charge can be accumulated for a short period, the image signal F21 for one frame input to the signal processing device 8 in the period T4. It is possible to brighten the image based on the above and display an appropriate image.
Further, since it is not necessary to amplify the image signal, the image based on the image signal F21 can be brightened and an appropriate image can be displayed without amplifying the noise.
（その他の実施の形態）
　ここまで、本発明を実施するための形態を説明してきたが、本発明は上述した実施の形態１～３によってのみ限定されるべきものではない。
　上述した実施の形態１～３では、リセット回路８１は、同期信号ＶＳ１と同期信号ＶＳ２との同期が取れているか否かを判定し、同期が取れていないと判定した場合に第１の同期信号生成回路７をリセットしていた。しかしながら、当該判定をリセット回路８１が実行しなくても構わない。
　例えば、術者等のユーザは、表示装置４に適切な画像が表示されていないと判断した場合に、内視鏡システム１，１Ａ，１Ｂを構成する入力部（図示略）に対して操作を行う。そして、リセット回路８１は、当該操作に応じて、第１の同期信号生成回路７をリセットする。
　すなわち、同期信号ＶＳ１と同期信号ＶＳ２との同期が取れているか否かを判定する機能をリセット回路８１（信号処理装置８）から取り除いても構わない。 (Other embodiments)
Although the embodiments for carrying out the present invention have been described so far, the present invention should not be limited only to the above-described embodiments 1 to 3.
In the above-described first to third embodiments, the reset circuit 81 determines whether or not the synchronization signal VS1 and the synchronization signal VS2 are synchronized, and when it is determined that the synchronization signal VS2 is not synchronized, the first synchronization signal. The generation circuit 7 was reset. However, the reset circuit 81 does not have to execute the determination.
For example, when a user such as an operator determines that an appropriate image is not displayed on the display device 4, he / she operates an input unit (not shown) constituting the endoscope systems 1, 1A, 1B. conduct. Then, the reset circuit 81 resets the first synchronization signal generation circuit 7 in response to the operation.
That is, the function of determining whether or not the synchronization signal VS1 and the synchronization signal VS2 are synchronized may be removed from the reset circuit 81 (signal processing device 8).
　上述した実施の形態１～３では、信号処理装置８は、第２の同期信号生成回路３とは別体で構成されていたが、これに限らず、当該第２の同期信号生成回路３内に搭載されても構わない。同様に、信号処理装置８は、第１の同期信号生成回路７とは別体で構成されていたが、これに限らず、当該第１の同期信号生成回路７内に搭載されても構わない。 In the above-described first to third embodiments, the signal processing device 8 is configured separately from the second synchronization signal generation circuit 3, but the present invention is not limited to this, and the signal processing device 8 is included in the second synchronization signal generation circuit 3. It may be installed in. Similarly, the signal processing device 8 is configured separately from the first synchronization signal generation circuit 7, but the present invention is not limited to this, and the signal processing device 8 may be mounted in the first synchronization signal generation circuit 7. ..
　１，１Ａ，１Ｂ　内視鏡システム
　２　内視鏡
　３　第２の同期信号生成回路
　４　表示装置
　５　光源装置
　６　撮像部
　７　第１の同期信号生成回路
　８　信号処理装置
　２１　挿入部
　２２　操作部
　２３　ユニバーサルコード
　２４　コネクタ部
　８１　リセット回路
　８２　ＰＬＬ回路
　８３　セレクタ回路
　８４，８４Ａ　増幅回路
　８５　映像処理回路
　２１１　先端部分
　ＣＬ１１，ＣＬ１２，ＣＬ１２１，ＣＬ１２２，ＣＬ２　クロック信号
　Ｆ１～Ｆ４，Ｆ２１　画像信号
　Ｇ１　ゲイン信号
　ＬＣ　光量制御信号
　Ｐ１～Ｐ５　時刻
　Ｒ１　リセット信号
　ＳＥ１　セレクト信号
　Ｔ１～Ｔ４，Ｔ３´　期間
　ＶＳ１，ＶＳ２　同期信号 1,1A, 1B Endoscope system 2 Endoscope 3 Second synchronization signal generation circuit 4 Display device 5 Light source device 6 Imaging unit 7 First synchronization signal generation circuit 8 Signal processing device 21 Insertion unit 22 Operation unit 23 Universal Code 24 Connector part 81 Reset circuit 82 PLL circuit 83 Selector circuit 84, 84A Amplifier circuit 85 Video processing circuit 211 Tip part CL11, CL12, CL121, CL122, CL2 Clock signal F1 to F4, F21 Image signal G1 Gain signal LC Light amount control signal P1 to P5 Time R1 Reset signal SE1 Select signal T1 to T4, T3'Period VS1, VS2 Synchronous signal

Claims (11)

  1. 　少なくとも１つ以上のハードウェアから成るプロセッサを備え、
    　前記プロセッサは、
    　クロック信号が入力され、第１の同期信号を出力する第１の同期信号生成回路からの前記第１の同期信号と、第２の同期信号生成回路から出力された第２の同期信号との同期が取れていない場合に、前記第１の同期信号生成回路をリセットし、
    　前記第１の同期信号生成回路がリセットされる期間において、前記クロック信号の周波数を他の期間よりも高くする信号処理装置。     With a processor consisting of at least one piece of hardware
    The processor
    Synchronization between the first synchronization signal from the first synchronization signal generation circuit to which the clock signal is input and output the first synchronization signal and the second synchronization signal output from the second synchronization signal generation circuit. If the above is not obtained, the first synchronization signal generation circuit is reset.
    A signal processing device that raises the frequency of the clock signal higher than other periods during the period when the first synchronization signal generation circuit is reset.
  2. 　前記プロセッサは、
    　前記第１の同期信号と前記第２の同期信号との同期が取れているか否かを判定し、同期が取れていないと判定した場合に、前記第１の同期信号生成回路をリセットする、請求項１に記載の信号処理装置。     The processor
    A claim for determining whether or not the first synchronization signal and the second synchronization signal are synchronized, and resetting the first synchronization signal generation circuit when it is determined that the first synchronization signal is not synchronized. Item 1. The signal processing apparatus according to item 1.
  3. 　前記プロセッサは、
    　前記第１の同期信号に基づくパルスと前記第２の同期信号に基づくパルスとが異なる時刻に立ち上がる際に、前記第１の同期信号と前記第２の同期信号との同期が取れていないと判定する、請求項２に記載の信号処理装置。     The processor
    When the pulse based on the first synchronization signal and the pulse based on the second synchronization signal rise at different times, it is determined that the first synchronization signal and the second synchronization signal are not synchronized. The signal processing apparatus according to claim 2.
  4. 　前記プロセッサは、
    　前記第１の同期信号生成回路がリセットされた後に撮像部から出力される少なくとも１フレーム分の画像信号に基づく画像を明るくする、請求項１に記載の信号処理装置。     The processor
    The signal processing device according to claim 1, wherein the image based on the image signal for at least one frame output from the imaging unit after the first synchronization signal generation circuit is reset is brightened.
  5. 　前記プロセッサは、
    　前記画像信号に乗算する２つのゲインのうち、
    　一方のゲインよりも大きいゲインを前記画像信号に対して乗算する、請求項４に記載の信号処理装置。     The processor
    Of the two gains to multiply the image signal
    The signal processing apparatus according to claim 4, wherein a gain larger than one gain is multiplied by the image signal.
  6. 　前記プロセッサは、
    　前記画像信号に乗算する前記２つのゲインのうち、
    　前記一方のゲインよりも大きいゲインを、前記第１の同期信号生成回路から出力される画像信号に対して乗算する、請求項５に記載の信号処理装置。     The processor
    Of the two gains to be multiplied by the image signal
    The signal processing apparatus according to claim 5, wherein a gain larger than one of the gains is multiplied by the image signal output from the first synchronization signal generation circuit.
  7. 　前記プロセッサは、
    　前記画像信号に乗算する前記２つのゲインのうち、
    　前記一方のゲインよりも大きいゲインを、前記撮像部から出力され、前記第１の同期信号生成回路に入力される画像信号に対して乗算する、請求項５に記載の信号処理装置。     The processor
    Of the two gains to be multiplied by the image signal
    The signal processing device according to claim 5, wherein a gain larger than one of the gains is multiplied by an image signal output from the imaging unit and input to the first synchronization signal generation circuit.
  8. 　前記プロセッサは、
    　２つのクロック信号を生成し、
    　前記第１の同期信号生成回路がリセットされる期間において、前記２つのクロック信号のうち周波数の高いクロック信号を、前記クロック信号として前記第１の同期信号生成回路に入力する、請求項１に記載の信号処理装置。     The processor
    Generate two clock signals,
    The first aspect of claim 1, wherein a clock signal having a higher frequency among the two clock signals is input to the first synchronization signal generation circuit as the clock signal during the period in which the first synchronization signal generation circuit is reset. Signal processing device.
  9. 　被検体内に挿入される内視鏡と、
    　少なくとも１つ以上のハードウェアから成るプロセッサと、を備え、
    　前記プロセッサは、
    　クロック信号が入力され、第１の同期信号を出力する第１の同期信号生成回路からの前記第１の同期信号と、第２の同期信号生成回路から出力された第２の同期信号との同期が取れていない場合に、前記第１の同期信号生成回路をリセットし、
    　前記第１の同期信号生成回路がリセットされる期間において、前記クロック信号の周波数を他の期間よりも高くする内視鏡システム。     The endoscope inserted into the subject and
    With a processor consisting of at least one piece of hardware,
    The processor
    Synchronization between the first synchronization signal from the first synchronization signal generation circuit to which the clock signal is input and output the first synchronization signal and the second synchronization signal output from the second synchronization signal generation circuit. If the above is not obtained, the first synchronization signal generation circuit is reset.
    An endoscope system that raises the frequency of the clock signal higher than the other periods during the period when the first synchronization signal generation circuit is reset.
  10. 　前記被検体に照射する照明光を出射する光源部をさらに備え、
    　前記プロセッサは、
    　前記第１の同期信号生成回路がリセットされる期間において、前記光源部の動作を制御し、前記照明光の光量を他の期間よりも高くする、請求項９に記載の内視鏡システム。     A light source unit that emits illumination light to irradiate the subject is further provided.
    The processor
    The endoscope system according to claim 9, wherein the operation of the light source unit is controlled during a period in which the first synchronization signal generation circuit is reset, and the amount of illumination light is increased as compared with other periods.
  11. 　少なくとも１つ以上のハードウェアから成るプロセッサが実行する信号処理方法であって、
    　クロック信号が入力され、第１の同期信号を出力する第１の同期信号生成回路からの前記第１の同期信号と、第２の同期信号生成回路から出力された第２の同期信号との同期が取れていない場合に、前記第１の同期信号生成回路をリセットし、
    　前記第１の同期信号生成回路がリセットされる期間において、前記クロック信号の周波数を他の期間よりも高くする信号処理方法。     A signal processing method performed by a processor consisting of at least one piece of hardware.
    Synchronization between the first synchronization signal from the first synchronization signal generation circuit to which the clock signal is input and output the first synchronization signal and the second synchronization signal output from the second synchronization signal generation circuit. If the above is not obtained, the first synchronization signal generation circuit is reset.
    A signal processing method in which the frequency of the clock signal is made higher than other periods during the period when the first synchronization signal generation circuit is reset.
PCT/JP2020/009791 2020-03-06 2020-03-06 Signal processing device, endoscope system, and signal processing method WO2021176710A1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0594226A (en) * 1991-09-30 1993-04-16 Toshiba Corp Clock switching system
JP2003234652A (en) * 2001-10-05 2003-08-22 Matsushita Electric Ind Co Ltd Pll circuit
WO2017002437A1 (en) * 2015-06-30 2017-01-05 オリンパス株式会社 Processing device and processing system
JP2019028651A (en) * 2017-07-28 2019-02-21 キヤノン株式会社 Synchronous reset circuit and control method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0594226A (en) * 1991-09-30 1993-04-16 Toshiba Corp Clock switching system
JP2003234652A (en) * 2001-10-05 2003-08-22 Matsushita Electric Ind Co Ltd Pll circuit
WO2017002437A1 (en) * 2015-06-30 2017-01-05 オリンパス株式会社 Processing device and processing system
JP2019028651A (en) * 2017-07-28 2019-02-21 キヤノン株式会社 Synchronous reset circuit and control method thereof

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