WO1998048514A2

WO1998048514A2 - Frequency synthesizer, particularly for use in a channel ic for hard disks

Info

Publication number: WO1998048514A2
Application number: PCT/IB1998/000327
Authority: WO
Inventors: Johannes Otto Voorman
Original assignee: Koninklijke Philips Electronics N.V.; Philips Ab
Priority date: 1997-04-24
Filing date: 1998-03-12
Publication date: 1998-10-29
Also published as: WO1998048514A3; EP0914716A2

Abstract

In a channel IC for a hard disk it is desirable that the write oscillator, but preferably also the read oscillator and the equalizer, can rapidly change their frequencies upon a change of zone on the hard disk while the stability and accuracy are maintained. The phase-locked loops in which such oscillators are included inherently respond slowly to a new frequency setting. According to the invention a rapid change in frequency is obtained, while the accuracy and stability are retained, in that by means of an analog multiplier/divider a substantial part of the control signal necessary to set the oscillators to a new frequency is derived from a control signal available in a second PLL loop, preferably the PLL loop of the servo circuit for controlling the read/write heads. The PLL loop of the write oscillator now merely has to provide the fine control.

Description

Frequency synthesizer, particularly for use in a channel IC for hard disks

The invention relates to a frequency synthesizer comprising an input for receiving a reference frequency signal, a first frequency divider and a phase-locked loop circuit including a first controlled oscillator, a low-pass filter, a phase detector and a second frequency divider, the first frequency divider being coupled between the reference frequency input and an input of the phase detector.

Such a frequency synthesizer is well-known and is used particularly in a channel IC for hard-disks, intended for processing the read/write signals in disk drives. Such a channel IC is described in, for example, "A Single-Chip 9-32 Mb/s Read/Write Channel for Disk-Drive Applications" by M. Zuffada et al. in IEEE-SSC, vol. 30, no. 6, June 1995, pp. 650-659. The oscillator therein serves for generating the write signal frequency and its oscillation frequency should be very high and should preferably also be very stable and free from noise. In addition, such an IC includes a second controlled oscillator for synchronizing a read signal and an oscillator used in the servo demodulator to control the position of the write/read heads. On hard disks the data is recorded in zones and during reading/writing it is often necessary to jump from one zone to another. The data rates in the various zones are different and, to ensure that the passage from one zone to another proceeds as rapidly as possible, it is desirable that the write and read oscillator adapt their frequencies as rapidly as possible to that of the data stream to be processed. The frequency can be changed rapidly in a PLL circuit but this is effected at the expense of the frequency accuracy and the noise. Particularly in the write oscillator, however, stringent requirements are imposed on these two characteristics, as a result of which a slow change of the frequency had to be accepted until now.

It is an object of the invention to solve this problem by providing a frequency synthesizer which enables a rapid change of frequency in conjunction with a high stability and a good signal-to-noise ratio.

To this end, the invention provides a frequency synthesizer of the type defined in the opening paragraph, which is characterized by a second phase-locked loop circuit coupled to the reference frequency signal, an analog multiplier/divider for converting the control signal from the second PLL circuit into a control signal which is substantially similar to the control signal needed to cause the first controlled oscillator to supply the desired frequency, and an analog subtractor circuit coupled between the output of the low- pass filter and the control input of the first controlled oscillator and having a first input arranged to receive the output signal of the multiplier/divider, having a second input arranged to receive the output signal of the low-pass filter, and having an output coupled to the control input of the first oscillator.

The invention is based on the recognition of the fact that a rapid frequency change of the write oscillator is possible while maintaining a high stability and a good signal-to-noise ratio in that a substantial part of the control signal necessary to obtain the required frequency step is derived by means of an analog circuit, i.e. rapidly, from a control signal that is already available and in that the rest is derived by means of the phase- locked loop of the write oscillator, the required accuracy being obtained by means of the last-mentioned control loop without the signal-to-noise ratio or the stability being adversely affected thereby.

Preferably, the PLL circuit of the servo control system is used for the second PLL, which circuit is anyway present in the channel IC and can be used for the synchronization of the servo low-pass filter or for the servo signal detection.

In a further preferred embodiment of invention the output signal of the subtractor circuit, which forms a satisfactory measure of the desired write oscillator frequency, can also be coupled to the read frequency oscillator and/or the equalizer circuit present in the IC. In this way it is achieved that these circuits can also be set very rapidly to a new frequency necessary for correctly reading the data stream in a new zone.

An embodiment of the invention will now be described in more detail, by way of example, with reference to the drawing, in which the sole Figure shows a block diagram of a preferred embodiment of the invention.

In the frequency synthesizer shown in the Figure the signal from a reference frequency oscillator 1 is coupled to two PLL circuits. The first PLL circuit comprises a frequency/phase detector 2, a low-pass filter 3 and a current-controlled oscillator 4. A first input of the detector 2 receives the reference frequency and another input receives the output signal of the oscillator 4. The detector 2 has its output coupled to the input of the oscillator 4.

Preferably, the PLL circuit, which comprises the detector 2, the filter 3 and the oscillator 4, is a circuit which is used anyway in the servo demodulator. A PLL circuit for such a servo signal is necessary at any rate in such an IC and can therefore be used advantageously for the invention. The output signal f_servo of the controlled oscillator in the servo circuit is independent of the position of the read/write head with respect to the write surface and is equal to f_ref (or f_ref/2). If the PLL circuit belongs to the servo control circuit the output signal of the low-pass filter 3 , which is a measure of the oscillator frequency, can be used for controlling the bandwidth of a servo low-pass filter 14, if necessary after further filtering in a low-pass filter 12 and/or multiplication and division in a circuit 13. The servo control circuit is known per se and falls beyond the scope of the invention. The second PLL circuit in the frequency synthesizer in accordance with the invention is adapted to supply the channel IC with a write signal having a frequency (M/N)f_ref, where M and N are positive integers. To this end, the second PLL circuit includes a current-controlled write signal oscillator 5, a digital 1/M divider 6, a phase detector 7 and a low-pass filter 8. In the divider 6 the output signal of the oscillator 5 is divided by M and in the phase detector 7 it is compared with the reference frequency f_ref, which has been reduced to f_ref/N in a 1/N divider 9. The output signal of the phase detector 7 is coupled to the input of the oscillator 5 via a low-pass filter 8. The PLL loop attempts make the output signal f_wr of the oscillator 5, which has been reduced to f_wr/M in the divider 7, equal to f_ref/N, so that f_wr = f_ref<M/N) once the PLL loop has reached the stable state. It is obvious that instead of the single reference frequency source 1 and the 1/N divider 9 it is also possible to use a second reference source supplying the frequency f_ref/N.

The divisors M and N are externally adjustable and are dictated by the desired data rate for a zone of the hard disk in which data is to be recorded. A change of zone may require a frequency change of some tens of per cent and the new frequency is reached comparatively slowly if this frequency change is effected only by changing the values of M and N in the respective dividers 6 and 9 and a satisfactory signal-to-noise ratio is given the highest priority.

According to the invention the control signal of the PLL loop for the write oscillator in the case that a change is required is influenced externally by applying the output signal of the low-pass filter 3, or the filter 12 if present, of the first PLL circuit to an input of a subtractor circuit 11 via an externally adjustable analog M/N divider 10, the other input of the subtractor circuit 10 receiving the output signal of the low-pass filter 8. The output signal of the subtractor circuit is a measure of the desired frequency change and is applied to the write oscillator. Since the analog M/N divider responds very rapidly to a newly set multiplier/divisor M7N', the control signal of the second PLL is adapted very rapidly to the desired situation in that the control signal of the oscillator 5 is changed stepwise. As a result, the oscillator frequency is rapidly made to approximate to the desired frequency f_refM7N\ after which the second PLL loop itself can provide the correction by the last few per cent. On the one hand, this results in a very rapid frequency change ⁴s obtained and, on the other hand, the desired stability and good signal-to-noise ratio of the write oscillator frequency can be maintained.

One of the advantages obtained by means of the invention is that the requirements to be imposed on the low-pass filter 8 can be considerably less stringent. Conventional circuits often require a third-order filter in order to achieve the desired accuracy of the oscillator frequency f_wr, = 0.1 %. Such a filter gives rise to either additional noise and jitter, or a slower response of the control loop. The invention enables a much simpler filter to be used while the accuracy is maintained. It is to be noted that for a correct operation of the circuit in accordance with the invention it is necessary that the oscillators 4 and 5 produce a similar frequency variation for a similar change in bias current but in an integrated circuit this can be achieved without any problem.

In a further embodiment of the invention the output signal of the subtractor circuit 11, which is a measure of the desired change, can also be used advantageously for controlling a PLL loop, shown diagrammatically in the Figure, which includes an oscillator 15 for the read frequency signal f_r, a phase detector 16 and a low-pass filter 17, and also for adjusting the bandwidth of an equalizer circuit 18 present in the channel IC. In order to enable the bandwidth of the servo low-pass filter and/or of an equalizer to be adjusted by means of a control current in a manner similar to that of the write/read oscillators it is necessary to use filters whose bandwidth is current dependent. Such current-controlled filters as well as current-controlled oscillators can be realized with the aid of current-dependent transconductances and fixed capacitors by the use of conventional techniques. Although the frequency synthesizer in accordance with the invention has been described for use in a channel IC for a hard disk, it will be evident to those skilled in the art that the principle of the invention can be used particularly in those cases where a rapid stepwise change of the frequency of a controlled oscillator included in a phase-locked loop is required.

Claims

1. A frequency synthesizer comprising an input for receiving a reference frequency signal, a first frequency divider and a phase-locked loop circuit including a first controlled oscillator, a low-pass filter, a phase detector and a second frequency divider, the first frequency divider being coupled between the reference frequency input and an input of the phase detector, characterized by a second phase-locked loop circuit coupled to the reference frequency signal, an analog multiplier/divider for converting the control signal from the second PLL circuit into a control signal which is substantially similar to the control signal needed to cause the first controlled oscillator to supply the desired frequency, and an analog subtractor circuit coupled between the output of the low-pass filter and the control input of the first controlled oscillator and having a first input arranged to receive the output signal of the multiplier/divider, having a second input arranged to receive the output signal of the low-pass filter, and having an output coupled to the control input of the first oscillator.

2. A as claimed in Claim 1, characterized in that the first controlled oscillator is the write signal oscillator for the write head of a hard disk.

3. A frequency synthesizer as claimed in Claim 2, characterized in that the second phase-locked loop circuit forms part of a servo circuit for controlling the write head of a hard disk.

4. A frequency synthesizer as claimed in Claim 2 or 3, characterized in that the analog subtractor circuit has its output also coupled to the control input of a controlled oscillator for supplying the read frequency signal for the read head of a hard disk.

5. A frequency synthesizer as claimed in Claim 2, 3 or 4, characterized in that the analog subtractor circuit has its output also coupled to the control input of an equalizer circuit.

6. A channel IC for a hard disk, including a frequency synthesizer as claimed in at least one of the Claims 1-5.