JPH0738584B2 - Phase locked loop circuit - Google Patents

Phase locked loop circuit

Info

Publication number
JPH0738584B2
JPH0738584B2 JP4109454A JP10945492A JPH0738584B2 JP H0738584 B2 JPH0738584 B2 JP H0738584B2 JP 4109454 A JP4109454 A JP 4109454A JP 10945492 A JP10945492 A JP 10945492A JP H0738584 B2 JPH0738584 B2 JP H0738584B2
Authority
JP
Japan
Prior art keywords
frequency
output
input signal
phase comparator
locked loop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP4109454A
Other languages
Japanese (ja)
Other versions
JPH05183433A (en
Inventor
凡夫 広瀬
伸一 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP4109454A priority Critical patent/JPH0738584B2/en
Publication of JPH05183433A publication Critical patent/JPH05183433A/en
Publication of JPH0738584B2 publication Critical patent/JPH0738584B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は入力信号に異常が生じた
時にも正確に出力信号を出すようにした位相ロックルー
プ回路(以下、PLL回路と称する)に関するものであ
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop circuit (hereinafter referred to as a PLL circuit) which outputs an output signal accurately even when an abnormality occurs in an input signal.

【0002】[0002]

【従来の技術】従来から位相ロックループ(PLL)技
術が広く用いられている。位相ロックループは、本来入
力周波数の高周波のジッタ成分を除去するものである。
従って、多少の入力信号の異常に対しても出力信号は急
激に変化しない特性を有する。
2. Description of the Related Art Conventionally, phase locked loop (PLL) technology has been widely used. The phase lock loop originally removes a high frequency jitter component of the input frequency.
Therefore, the output signal has a characteristic that it does not change abruptly even if the input signal is somewhat abnormal.

【0003】近年、記録媒体から信号を抽出する時に信
号からクロックを抽出し、このクロックでもって情報信
号を読み取る、いわゆるセルフクロック抽出にPLL技
術が用いられている。このような場合には、非常に正確
なクロック抽出が行なわれなければ情報に大きなバース
トエラーを付加してしまう。
In recent years, a PLL technique has been used for so-called self-clock extraction, in which a clock is extracted from a signal when a signal is extracted from a recording medium and an information signal is read by this clock. In such a case, a large burst error will be added to the information unless very accurate clock extraction is performed.

【0004】このように、近年、PLL回路も高性能な
ものが要求されている。(図5)に基本的なPLL回路
の一例を示す。(図5)において、1は入力信号fiと
出力信号foの位相を比較する位相比較器であり、その
出力は増幅器2に接続され、増幅器2の出力は電圧−周
波数変換器である電圧制御型発振器3を制御する。この
電圧制御型発振器の出力がPLL回路の出力であり、こ
の出力はまた位相比較器1にフィードバックされてい
る。
As described above, in recent years, a high performance PLL circuit has been required. FIG. 5 shows an example of a basic PLL circuit. In FIG. 5, reference numeral 1 is a phase comparator for comparing the phases of the input signal fi and the output signal fo, the output of which is connected to the amplifier 2 and the output of the amplifier 2 is a voltage-frequency converter, which is a voltage control type. The oscillator 3 is controlled. The output of this voltage controlled oscillator is the output of the PLL circuit, and this output is also fed back to the phase comparator 1.

【0005】(図6)は増幅器2の周波数特性図であ
る。増幅器2は(図6)に示すように、一般にローパス
フィルタとなっている。系の開ループ利得をGとする
と、fnがゲイン交点周波数である。fnは系の応答速
度を決定する。これは、入力信号のジッタを除去するた
めに入力周波数よりも十分低く選ばれる。しかし、あま
り低くすると、系の応答速度が低くなってしまう。例え
ば、高密度記録媒体では入力信号の周波数は1MHz程
度であり、一方、高速アドレスサーチ等の必要からfn
は1KHz以上に選ばれる。すなわち、fnには上述の
ような制限が加えられ、自由に決定できない。fn=1
KHzとした時、(図5)において、入力信号fiに異
常が起こった場合を考える。なお、入力信号fiの変動
周波数は5〜30Hz程度の場合が多い。例えば、この
変動周波数を10Hzとする。
FIG. 6 is a frequency characteristic diagram of the amplifier 2. The amplifier 2 is generally a low pass filter as shown in FIG. When the open loop gain of the system is G, fn is the gain intersection frequency. fn determines the response speed of the system. It is chosen well below the input frequency to eliminate jitter in the input signal. However, if it is too low, the response speed of the system will be low. For example, in a high-density recording medium, the frequency of the input signal is about 1 MHz, while fn is required due to the need for high-speed address search.
Is selected above 1 KHz. That is, fn is subject to the above-mentioned restrictions and cannot be freely determined. fn = 1
Consider the case where an abnormality occurs in the input signal fi at KHz (FIG. 5). Note that the fluctuation frequency of the input signal fi is often about 5 to 30 Hz. For example, this fluctuating frequency is set to 10 Hz.

【0006】(図7)は、入力信号fiに雑音等の異常
がない場合の位相比較器1の出力である。入力信号fi
の変動周波数が10Hzであるから、この位相比較器の
出力の基本周波数は10Hzである。
FIG. 7 shows the output of the phase comparator 1 when the input signal fi has no abnormality such as noise. Input signal fi
The fundamental frequency of the output of this phase comparator is 10 Hz because the fluctuating frequency of 10 Hz is 10 Hz.

【0007】[0007]

【発明が解決しようとする課題】しかしながら、入力信
号に異常が発生すると位相比較器の出力は乱れ、特に、
入力信号が非常に高い周波数の場合には、位相比較器の
出力が零となる場合が生じる。この場合には、系のゲイ
ン交点周波数が1KHzであり、変動周波数10Hzよ
り十分大きいことから、この間に電圧制御型発振器3の
出力周波数は大きくずれてしまう。もし、fnを変動周
波数10Hzに合わせることができれば、このようなず
れを補う補間が可能である。しかしながら、fnは前述
したように系の応答からそのような低い値に設定するこ
とはできない。
However, when an abnormality occurs in the input signal, the output of the phase comparator is disturbed.
When the input signal has a very high frequency, the output of the phase comparator may become zero. In this case, the gain crossover frequency of the system is 1 KHz, which is sufficiently higher than the fluctuation frequency of 10 Hz, so that the output frequency of the voltage controlled oscillator 3 largely deviates during this period. If fn can be adjusted to the fluctuating frequency of 10 Hz, interpolation that compensates for such a shift is possible. However, fn cannot be set to such a low value from the system response as described above.

【0008】本発明は、上述のように入力信号に異常が
起こった時も出力信号に異常が現われないようにしたP
LL回路を提供することを目的とする。
According to the present invention, as described above, even when an abnormality occurs in the input signal, the abnormality does not appear in the output signal.
It is an object to provide an LL circuit.

【0009】[0009]

【課題を解決するための手段】本発明は上記課題を解決
するために、入力信号と出力信号の位相を比較する位相
比較器と、前記位相比較器の出力側に接続された共振周
波数が前記位相比較器の入力信号の変動成分周波数とほ
ぼ一致したローパスフィルタと、前記ローパスフィルタ
の出力に応じて出力信号発振周波数が制御される発振器
とを具備したことを特徴とするものである。なお、前記
発振器には一般に電圧制御型発振器が用いられる。
SUMMARY OF THE INVENTION In order to solve the above problems, the present invention provides a phase comparator for comparing the phases of an input signal and an output signal, and a resonance circuit connected to the output side of the phase comparator.
It is characterized by including a low-pass filter whose wave number substantially matches the fluctuation component frequency of the input signal of the phase comparator, and an oscillator whose output signal oscillation frequency is controlled according to the output of the low-pass filter. . A voltage-controlled oscillator is generally used as the oscillator.

【0010】[0010]

【作用】本発明は、非常に簡単な構成で、位相比較器か
らの出力が得られない異常時にも、入力成分の変動に極
めて正確に発振周波数を入力信号の変動周波数成分に追
随させることができる。
According to the present invention, the oscillation frequency can be made to follow the fluctuation frequency component of the input signal extremely accurately in accordance with the fluctuation of the input component even when the output from the phase comparator cannot be obtained. it can.

【0011】[0011]

【実施例】以下、本発明の実施例を図面に基づいて説明
する。
Embodiments of the present invention will be described below with reference to the drawings.

【0012】(図1)は本発明の一実施例のブロック図
を示し、(図5)で説明したものと同様の部分は同一の
符号を付している。この(図1)において、位相比較器
1はループスイッチ51の入力側に接続され、かつ、位
相比較器1の出力端は位相異常検出器52に接続されて
いる。ループスイッチ51の出力端は共振回路53に接
続され、その出力は電圧制御型発振器3を制御する。
FIG. 1 shows a block diagram of an embodiment of the present invention, and the same parts as those described in FIG. 5 are designated by the same reference numerals. In this (FIG. 1), the phase comparator 1 is connected to the input side of the loop switch 51, and the output end of the phase comparator 1 is connected to the phase abnormality detector 52. The output terminal of the loop switch 51 is connected to the resonance circuit 53, and the output thereof controls the voltage controlled oscillator 3.

【0013】共振回路53は(図2)に示すような2次
系のローパスフィルタとする。この共振周波数f0を入
力信号の変動成分周波数にほぼ一致させる。ループが閉
じている時の系の応答周波数はゲイン交点周波数fnで
決まる。今、高周波の入力信号に異常が発生し、これに
起因して位相比較器1の出力が零になると、この期間は
等価的にループが切断されたこととなる。この際には位
相異常検出器52は不要となる。開ループ時の系の共振
は、共振回路53のf0になるから、共振回路53の出
力は入力信号の変動成分周波数と丁度一致して変化す
る。従って、共振回路53の出力は(図7)と同様の変
化をし、電圧制御型発振器3の出力はほとんど傷がない
場合と同じように変化する。
The resonance circuit 53 is a secondary low-pass filter as shown in FIG. This resonance frequency f 0 is made to substantially match the fluctuation component frequency of the input signal. The response frequency of the system when the loop is closed is determined by the gain intersection frequency fn. Now, when an abnormality occurs in the high frequency input signal and the output of the phase comparator 1 becomes zero due to this, the loop is equivalently cut during this period. In this case, the phase abnormality detector 52 becomes unnecessary. Since the resonance of the system at the time of open loop is f 0 of the resonance circuit 53, the output of the resonance circuit 53 changes just in agreement with the fluctuation component frequency of the input signal. Therefore, the output of the resonance circuit 53 changes in the same manner as in FIG. 7, and the output of the voltage controlled oscillator 3 changes in the same manner as in the case where there is almost no damage.

【0014】(図3)は、本発明の他の実施例を示すブ
ロック図である。この(図3)において、(図1)で説
明したものと同様のものは同一の符号を付している。
(図3)においては(図2)に示した特性の共振回路5
3の代わりに、縦続接続した1次のローパスフィルタ6
1とバンドパスフィルタ62からなる共振回路53’を
用いている。(図4)の曲線81が1次のローパスフィ
ルタ61の特性であり、曲線82が2次の共振回路の特
性である。この2次のバンドパスフィルタの共振周波数
を入力信号の変動成分の周波数に合わせておくと、ほぼ
(図2)の場合と同様の動作をする。
FIG. 3 is a block diagram showing another embodiment of the present invention. In this (FIG. 3), the same components as those described in (FIG. 1) are designated by the same reference numerals.
In FIG. 3, the resonance circuit 5 having the characteristics shown in FIG.
Instead of 3, first-order low-pass filter 6 connected in cascade
A resonance circuit 53 'composed of 1 and a bandpass filter 62 is used. A curve 81 in FIG. 4 shows the characteristic of the first-order low-pass filter 61, and a curve 82 shows the characteristic of the second-order resonant circuit. If the resonance frequency of the second-order bandpass filter is adjusted to the frequency of the fluctuation component of the input signal, the same operation as in the case of (FIG. 2) is performed.

【0015】[0015]

【発明の効果】以上のように本発明によれば、非常に簡
単な構成で、入力信号に異常が発生しかつ位相比較器か
らの出力が得られない異常時にも、入力成分の変動に極
めて正確に発振周波数を入力信号の変動周波数成分に追
随させることができる。
As described above, according to the present invention, with a very simple structure, even when an abnormality occurs in the input signal and the output from the phase comparator cannot be obtained, the fluctuation of the input component is extremely small. The oscillation frequency can be accurately followed by the fluctuation frequency component of the input signal.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例のブロック図FIG. 1 is a block diagram of a first embodiment of the present invention.

【図2】本発明の第1の実施例に係る共振回路の利得対
周波数特性図
FIG. 2 is a gain vs. frequency characteristic diagram of the resonance circuit according to the first embodiment of the present invention.

【図3】本発明の第2の実施例のブロック図FIG. 3 is a block diagram of a second embodiment of the present invention.

【図4】本発明の第2の実施例に係る共振回路の利得対
周波数特性図
FIG. 4 is a gain vs. frequency characteristic diagram of the resonance circuit according to the second embodiment of the present invention.

【図5】従来のPLL回路の一例を示すブロック図FIG. 5 is a block diagram showing an example of a conventional PLL circuit.

【図6】従来のPLL回路の増幅度対周波数特性図FIG. 6 is a diagram showing the amplification factor vs. frequency characteristic of a conventional PLL circuit.

【図7】(図5)のPLL回路の動作説明図FIG. 7 is an operation explanatory diagram of the PLL circuit of FIG. 5;

【符号の説明】[Explanation of symbols]

1 位相比較器 3 電圧制御型発振器 53、53’ 共振回路 61 ローパスフィルタ 62 バンドパスフィルタ 1 Phase Comparator 3 Voltage Controlled Oscillator 53, 53 'Resonant Circuit 61 Low Pass Filter 62 Band Pass Filter

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 入力信号と出力信号の位相を比較する位
相比較器と、前記位相比較器の出力側に接続された共振
周波数が前記位相比較器の入力信号の変動成分周波数と
ほぼ一致したローパスフィルタと、前記ローパスフィル
タの出力に応じて出力信号発振周波数が制御される発振
器とを具備したことを特徴とする位相ロックループ回
路。
1. A phase comparator for comparing the phases of an input signal and an output signal, and a resonance connected to the output side of the phase comparator.
A phase-locked loop comprising: a low-pass filter whose frequency is substantially equal to a variation component frequency of the input signal of the phase comparator; and an oscillator whose output signal oscillation frequency is controlled according to the output of the low-pass filter. circuit.
JP4109454A 1992-04-28 1992-04-28 Phase locked loop circuit Expired - Lifetime JPH0738584B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4109454A JPH0738584B2 (en) 1992-04-28 1992-04-28 Phase locked loop circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4109454A JPH0738584B2 (en) 1992-04-28 1992-04-28 Phase locked loop circuit

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP57177207A Division JPS5966229A (en) 1982-10-07 1982-10-07 Phase locked loop circuit

Publications (2)

Publication Number Publication Date
JPH05183433A JPH05183433A (en) 1993-07-23
JPH0738584B2 true JPH0738584B2 (en) 1995-04-26

Family

ID=14510649

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4109454A Expired - Lifetime JPH0738584B2 (en) 1992-04-28 1992-04-28 Phase locked loop circuit

Country Status (1)

Country Link
JP (1) JPH0738584B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10215175A (en) * 1996-11-29 1998-08-11 Sony Corp Pll circuit and signal reproducing device

Also Published As

Publication number Publication date
JPH05183433A (en) 1993-07-23

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