JPS60220627A - Phase locked loop - Google Patents

Abstract

PURPOSE:To follow up a wide-range input by controlling a VCO with a voltage obtained by adding the output of a loop filter and a bias control signal from the external. CONSTITUTION:An input signal (a) is inputted to a phase comparator PC1 and a synchronous detecting circuit 6. The PC1 compares the phase of the signal (a) with that of an output signal (e) from a frequency divider 4 and inputs the output to a bias adding circuit 5 after allowing this output to pass an LPF2. The circuit 6 detects step-out of synchronism between signals (a) and (e) and inputs a detection signal l to a bias control circuit 7. The circuit 7 to which the signal lis inputted generates a bias control signal (k) and inputs it to the circuit 5. The circuit 5 controls a VCO3 by a signal (c) resulting from addition of signals (j) and (k), and the signal (e) obtained by dividing an output signal (d) of the VCO3 by the frequency divider 4 is inputted to the PC1, thus constituting a PLL circuit. If the output frequency of the VCO3 is lower than the input frequency, the circuit 7 raises the bias voltage to raise the output frequency of the VCO; but otherwise, the circuit 7 reduces the bias voltage to approximate the input frequency and the frequency of the VCO to each other.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a phase locked loop (hereinafter referred to as PLL) used in a PCM signal reproducing device to extract clock information from a reproduced signal.

2. Description of the Related Art Structures of Conventional Examples and Their Problems In recent years, PCM signal reproducing devices such as digital audio disks (DAD) have come into widespread use. Generally, when reproducing a digital signal such as a PCM signal, stable reproduction is possible by extracting 0x information from the signal on the reproducing side and determining the signal using the clock. Furthermore, in order to achieve accurate reproduction, it is necessary to have a reference clock with very high accuracy and to control the reproduction clock so that it is synchronized with this reference clock. A PLL is usually used to achieve this purpose.

The conventional PLLK will be explained below with reference to the drawings. FIG. 1 is a block diagram of a conventional PLL, in which 1 is a phase comparator (PC), 2 is a loop filter (LPF), 3 is a voltage control 'Am gain (VCO), and 4 is a divider.

The operation of the PLL configured as above will be explained below. The reproduced signal a input to the PLL is the PCI
It is compared with the signal e obtained by dividing the output d of the VCO 3 by the frequency divider 4. The output of PCl is input to LPF 2, excess harmonic components are removed, and it becomes a control voltage C of vcos, which controls the oscillation frequency of VCO 3. Therefore, when the input signal has a higher frequency than the output e of the dividing period, the control voltage C of vCO changes by the output of PCl, which works to increase the oscillation frequency of VCo.
Eventually, the 9PLL in which the input frequency and the output frequency of the frequency divider are equal becomes stable in a periodic state. Conversely, when the human input frequency is low, the oscillation frequency of the VCO decreases, resulting in a synchronized state. However, if the change in input frequency is P
If the synchronizable box of LL is exceeded, the PLL cannot be synchronized, and therefore becomes unrelated to the VCO output power and is switched off.

FIG. 2 shows a block diagram of an example in which this conventional PLL is applied to a clock extraction circuit of a PCM signal regenerator. In FIG. 2, 2o is a waveform conversion circuit, 21 is a PLL circuit similar to that shown in FIG. 1, and 22 is a reference clock oscillation circuit (OS
C), 23 is a phase comparator (PC), 24 is a switching circuit, 25 is a motor control circuit (MC), 26 is a signal processing circuit, and 27 is a coarse servo circuit. A reproduced signal J reproduced from a disk, etc. is amplified and equalized by a waveform conversion circuit 20.
After receiving the action of
1 and is input to the coarse servo circuit 27 and signal processing circuit 26. Under normal operating conditions, the PLL is in a synchronous state;
The extracted clock d is outputted at the output of . This extracted clock d and the output q of the DSC 22 are connected to a comparator 23.
The error signal output is compared with the switching circuit 2.
4. Input all the information to MC25. The MC 25 uses this signal to precisely control the rotational speed of the motor, to maintain the correct rotational speed of the disk, and to control the frequency of the reproduction signal to a certain constant value. However, when the motor starts up or if the input is interrupted for some reason, the frequency of the reproduced signal changes and the PLL goes out of synchronization, making it impossible to extract the clock. cormorant. Therefore, in these cases, the switching circuit 24 inputs the output iiMc2g of the coarse servo circuit 27 to control the motor rotation speed.
The configuration is such that control is switched to the extracted clock after the reproduced signal frequency enters the synchronizable range of the PLL. Note that FIG. 2 shows a normal operating state. and,
As this coarse servo circuit, a circuit that detects the longest cycle of the human input signal and brings it closer to a predetermined value is used. I'm putting it on.

Then, the extracted clock d and the input signal ail are further input to the signal processing circuit 26, where various processes are performed to demodulate the PCM.

Since it is necessary to use the servo circuit and the PLL circuit while switching between them, there are problems in that the circuit becomes complicated and it is difficult to deal with cases where it is desired to change the reference clock.

OBJECTS OF THE INVENTION It is an object of the present invention to eliminate the need for a coarse servo circuit from conventional circuits and to provide a countermeasure for changes in the reference clock.

Structure of the Invention The phase locked circuit of the present invention has a bias addition circuit that adds the output of the loop filter and an external bias voltage, and a control circuit for the bias voltage, and the output of the bias addition circuit and the control voltage of the VT pressure control oscillator. This configuration allows a wide range of synchronization to be achieved.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 3 shows a block diagram of a PLL in one embodiment of the present invention. In FIG. 3, 6 is a bias addition circuit, θ is a synchronization detection circuit, and 0 is a bias control circuit, and the other parts are the same as in FIG.

The operation of the PLL of this embodiment constructed as described above will be explained below. Human power signal a is PCI, LPF
2′i and becomes one of the human power i of the bias addition circuit 6. 44, the other input of the bias addition circuit 6 is the bias voltage from the bias control circuit 7, and the sum of these two becomes the control voltage C of the VCO 3. Then, this bias voltage is the output JV of the synchronization detection circuit 6, (as i7 manual power,
The bias control circuit 7 increases the bias voltage when the vCO output frequency is lower than the input frequency.
The output frequency is increased, and in the opposite case, the bias voltage is decreased to bring the input and VCO output closer together. By doing this, it is possible to always follow a wide range of inputs, even to the PLL (i7 synchronized state).For example, the block diagram when applied to the clock extraction circuit of the PLL1PCIV1 signal regeneration device of the present invention is shown Shown in Figure 4.

In FIG. 4, 41 is the PLL circuit section of the present invention, 42 is a variable reference clock oscillator (VO8CL and others are the same as in FIG. 2, and the operation thereof will be explained below. In the normal state, it is the same as in FIG. The adder circuit is in a steady state as it passes through, but when the PL is started up, etc.
Even when the frequency of the signal input to L41 is very low, the bias voltage is reduced in the bias control circuit by the output 2 of the synchronization detection circuit, and the synchronization range of PLL41 is shifted to the lower frequency side, and PLL41 f synchronization is performed. You can bring it to the state. Furthermore, even if the frequency of the output n of the variable reference clock oscillator 42 changes, the amount of change mf is input to the bias control circuit 7 and the bias voltage is increased or decreased according to the amount of change m, so that the PLL (i7 synchronized state) is always maintained. It is possible to change the reference clock without changing the clock.Also, even if the input signal is interrupted for some reason and it becomes impossible to extract the clock, the bias voltage allows the reference clock to be changed.
By controlling the control voltage of O, it is possible to prevent the output frequency of the PLL from changing significantly and resynchronizing to take a long time. If the bias control circuit 7 is simple, it can be realized by an operational amplifier or the like, but if complicated control is to be performed, a microcomputer can be used. For example, if only the reference clock is changed as described above, if the amount of change m is output as a voltage, then n can be realized by an operational amplifier with appropriately determined amplification degree and output potential. Therefore, complex control such as detecting the difference between the PLL center frequency and the reference clock frequency and automatically moving the PLL synchronization range to the vicinity of the reference clock frequency can also be performed using a microcomputer. It can be easily achieved by using it. In the above embodiment, the output of the synchronization detection circuit 6 and VO are connected to the input of the bias control circuit 7.
Although the variation output m of the 3C42 is used, the input of the bias control circuit 7 is not limited to these; for example,
It is possible to use a sense signal proportional to the speed or rotational speed of the motor, or a signal obtained by dividing the input signal, the reference clock signal itself, or a frequency thereof.

Effects of the Invention As is clear from the second explanation, the present invention includes a bias addition circuit that adds the output of a loop filter and an externally applied addition bias voltage, and a control circuit that controls the bias voltage. Since the output of the adder circuit is configured to be used as the control voltage of the voltage controlled oscillator, an excellent effect of having a wide synchronizable range can be obtained. As a result, when applied to a PCM signal reproducing device, a coarse servo circuit is not required, and the present invention can also be used for purposes such as changing a reference clock. Furthermore, when the control circuit is realized using a microcomputer, it is possible to simplify the adjustment of the PLL, and to perform control that compensates for temperature characteristics and changes over time, as well as ease of design and flexibility. Effects can be obtained.

[Brief explanation of drawings]

Figure 1 is a block diagram of a conventional phase-locked circuit, and Figure 2 is a PC that applies the conventional phase-locked circuit to an extraction circuit.
FIG. 3 is a block diagram of a phase synchronization circuit according to an embodiment of the present invention, and FIG. 4 is a block diagram of a PCM signal reproducing device in which the present invention is applied to a clock extraction circuit. 1.23... Phase comparator, 2. Paloop filter,
3... Voltage controlled oscillator, 4... Frequency divider, 6...
...Bias addition circuit, 6...Synchronization detection circuit, 7...
...Bias control circuit, 20... Waveform conversion circuit, 21 Tar control circuit, 26 Signal processing circuit, 2 End...
... Coarse servo circuit, 41 ... PLL circuit in one embodiment of the present invention, 42. Variable reference clock excavator. Name of agent: Patent attorney Toshio Nakao, 1st person, 2nd person
Figure π

Claims (1)

[Claims] a phase comparator that compares the phase of the input signal and the frequency divider output;
A loop filter that generates a low frequency F wave from the output of this phase comparator, a voltage controlled oscillator whose oscillation output is varied according to the output voltage of this loop filter, and the frequency divider that divides the output of this voltage controlled oscillator. and a bias addition circuit that adds the output of the loop filter and an external bias voltage, and a bias control circuit that controls the bias voltage, and the output of the bias addition circuit is used as the control voltage of the voltage controlled oscillator. A phase-locked circuit characterized by: