JP3240683B2 - Magnetic disk system and waveform equalizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a magnetic disk system and, more particularly, to a transversal circuit or a programmable filter for performing an optimum waveform shaping process for an arbitrary transfer speed in a read channel and improving a reproduction margin. And a waveform equalizer.

[0002]

2. Description of the Related Art As a method of increasing the storage capacity of a magnetic disk, there is a method of increasing the bit density. Conventionally, data is read and written at the same transfer speed between the inner circumference and the outer circumference of a disk rotating at a constant speed. As a result, the bit density becomes smaller toward the outer periphery and the recording margin becomes larger, but it is disadvantageous in terms of increasing the capacity. Therefore, as a new recording method, CDR (Constant Density Recor)
ding) has been devised. This method is to increase the recording capacity of the magnetic disk by changing the data transfer speed between the inner and outer circumferences of the disk so that the bit density becomes as large as the inner circumference of the disk even at the outer circumference of the disk. CD
In the R system, the transfer speed changes between the inner circumference and the outer circumference of the disk, and the frequency components of the read data are different. Therefore, it is necessary to make the characteristics of the waveform shaping circuit that processes the read data variable according to the transfer speed. Therefore, when a transversal circuit is used, a need has arisen for a waveform equalization circuit for changing a delay time according to a transfer rate and performing optimal waveform equalization. In addition, a need has arisen for a programmable filter capable of arbitrarily setting a cutoff frequency.

A cosine equalization circuit which is a waveform equalization circuit using a conventional variable delay circuit will be described with reference to FIG.
Registers 101 and 1401, external control signal generation circuit 14
02, a frequency synthesizer 102, and a transversal circuit 104. The transversal circuit 104 includes variable delay circuits 111 to 114 and an amplifier 105
To 109, and an adder 115. In the magnetic disk, the value of the register 101 is determined according to the transfer speed, and the frequency synthesizer 102 outputs a write clock signal 110 of a specific frequency according to the set value of the register 101. The delay time of the transversal circuit 104 is set by the register 1401, and the external control signal generation circuit 14
02 outputs a control signal according to the set value of the register 1401, and controls the delay time of the transversal circuit 104 with the control signal. This operating principle is shown in FIG. Delay circuit 1
11 and the amplifier 106 generate signals such as 2301, 2302, and 2303 from the input signal according to the delay time and the amplification degree. These signals are added by the adder 115 and equalized to a signal indicated by 2304.

Further, a conventional programmable filter will be described with reference to FIGS. FIG. 21 is a block diagram schematically showing a conventional programmable filter system, and includes a register B2101 and a register A10.
1, DAC 2103, programmable filter 160
1. It comprises a synthesizer 102. In the magnetic disk device, the value of the register A101 is determined according to the transfer speed, and the synthesizer 102 outputs a write clock 110 having a specific frequency according to the value of the register A101.
Further, the cutoff frequency of the filter is set by the register B2101, a control signal 1602 corresponding to the set value of the register B2101 is generated by the DAC 2103, and the cutoff frequency of the programmable filter 1601 is controlled by the control signal 1602. FIG. 22 shows the system of FIG.
1 is a conventional programmable filter system accompanied by a reference numeral 1. The DAC 2103 generates a control signal 1602 according to the set value of the register B 2101 and monitors the output signal of the reference oscillator 2201, and controls the cutoff frequency of the filter 1601, thereby compensating for variations in the capacitance of the filter. FIG. 24 shows a configuration example of the programmable filter 1601. Programmable filter 1
601 is a low-pass filter 2401, a second-order high-pass filter 2
402, an adder 2403 and a low-pass filter 2404. Filters 2401, 2402, 2404
Are controlled by control signals 1602, respectively. With this configuration, the signal 2301 shown in FIG.
And signals similar to the signals 2302 and 2303 are generated. The signals are added by the adder 2403, and the input signal is equalized.

The prior art relating to the waveform equalizer is disclosed in JP-A-1-80116 and JP-A-1-801.
No. 17, JP-A-63-122061, JP-A-62-102481, and the like.

[0006]

In a transversal circuit constituted by the above-described system, the delay time varies due to variations in the resistance value of the resistance element and the capacitance value of the capacitance element constituting the delay circuit. Since this variation depends on the process parameters of the IC to be manufactured, there is a considerable problem in the delay accuracy. Further, in the conventional method, a microprocessor (MPU) needs to set a register value for a frequency synthesizer for a certain transfer rate and further set a register value for a delay time setting register of a delay circuit. One register needs to be set, and the processing amount of the MPU increases.

On the other hand, even with a conventional programmable filter, a microprocessor (MP
U) sets the value of the register for the frequency synthesizer,
Furthermore, since it is necessary to set the value of the cutoff frequency setting register of the filter, it is necessary to set two registers, which increases the processing amount of the MPU. Further, since the circuit has two independent registers and a DAC, the circuit scale of the entire system is increased.

A first object of the present invention is to provide a high-precision magnetic disk system in which the processing amount of HDC is reduced and the circuit scale of the entire system is reduced.

A second object of the present invention is to provide a transversal waveform equalizer having a highly accurate delay circuit independent of process parameters.

[0010]

In order to achieve the first object, a magnetic disk system according to the present invention has a mechanism for reading / writing data on / from a magnetic disk, a control circuit therefor, and a data transfer speed. The first of the corresponding frequency
A frequency synthesizer for generating a clock signal, a phase locked loop circuit for generating a control signal according to the frequency of the first clock signal, and a waveform for equalizing the waveform of the original signal according to the control signal and outputting an equalized signal An equalizing circuit, a waveform shaping circuit that generates a code pulse from the equalized signal, a data separator that generates a second clock signal synchronized with the code pulse, and decoding that decodes the code pulse using the second clock signal. And a coding circuit for coding the recording data by the first clock signal.

In order to achieve the second object, a waveform equalizer according to the present invention includes a frequency synthesizer for generating a signal of an arbitrary frequency in accordance with the transfer rate of an original signal, and a frequency synthesizer for generating a signal of an output signal of the frequency synthesizer. A phase synchronizing circuit for generating a control signal in response thereto and a waveform equalizing circuit for equalizing and outputting a waveform of an original signal in accordance with the control signal are provided on the same semiconductor integrated circuit.

[0012]

In the magnetic disk system according to the present invention, the set value is determined according to the transfer speed of the magnetic disk.
The frequency synthesizer generates a signal having a frequency corresponding to the set value, and becomes a Write Clock signal. The phase locked loop monitors the output signal of the frequency synthesizer and generates a control signal based on the frequency.

In the waveform equalizer according to the present invention, the frequency synthesizer generates a signal having a frequency according to the set value.
The phase locked loop monitors the output signal of the frequency synthesizer and generates a control signal for the variable delay circuit according to the frequency. Thus, the variation in the delay time due to the variation in the elements is absorbed by the phase locked loop circuit formed on the same chip.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will now be described with reference to FIGS.
3 and FIG.

FIG. 1 schematically shows a transversal type waveform equalizing circuit according to the present invention. 1 includes a register 101, a frequency synthesizer 102, a phase locked loop (PLL) 103, and a transversal circuit 104. The transversal circuit 104 includes variable delay circuits 111 to 114 and variable gain amplifiers 105 to
9. It comprises an adder 115.

The register 101 is set in accordance with the transfer speed of the magnetic disk, and the frequency synthesizer 102 is adapted to write clock of a specific frequency in accordance with the set value of the register 101.
The signal 110 is output. The PLL circuit 103 formed on the same chip as the delay circuits 111 to 114 monitors the output Write Clock 110 of the frequency synthesizer 102 and outputs a delay circuit control signal according to the frequency. The delay circuits 111 to 114 make the delay time variable by the output control signal of the PLL 103.

FIG. 2 shows a configuration of a delay circuit, which is a primary or secondary APF (All Pass Filter) 201-203.
Are connected in cascade to have a Bessel characteristic, whereby a delay circuit having a flat delay characteristic is formed.

FIG. 3 shows an example of the configuration of a primary APF, which includes variable Gm amplifiers 301 and 302 and capacitors 303 and 304. The transfer function T (s) of this circuit is

[0019]

(Equation 1)

Ω = 2 × Gm / C and the phase is delayed by 90 degrees.

FIG. 4 shows an example of the configuration of the secondary APF, in which the variable Gm
It comprises amplifiers 401 to 404 and capacitors 405 to 408. The transfer function T (s) of this circuit is

[0022]

(Equation 2)

[0023]

(Equation 3)

[0024]

(Equation 4)

Ω = ωt, the phase is delayed by 180 degrees.

FIG. 5 shows a variable Gm amplifier. Bipolar transistors 501 to 506 and current sources 507 to 506 are shown.
508 and a resistor 509. The conductance Gm of this circuit is

[0027]

(Equation 5)

The current I of the current source 509 can be expressed as
Gm can be adjusted by controlling the current I1 of the current source 2 or the current sources 507 and 508.

FIG. 6 is a diagram showing the configuration of the PLL circuit 103. The PLL circuit includes a primary APF 601 for reference, a multiplier 602, and a loop filter 603, and is formed on the same chip as the APF 604 for signal processing. The reference primary APF 601 inputs the Write Clock signal 110, and the multiplier 602 outputs the output of the reference primary APF 601 and the Write Cloc.
The k signal 110 is input. The output of the multiplier 602 is Write
When the phase difference between the ClocK signal 110 and the output signal of the reference primary APF 601 becomes 90 degrees, the DC component becomes zero. The loop filter 603 receives the output of the multiplier 602 as an input, extracts the DC component of the output signal of the multiplier 602 and outputs it as a control signal.
01 and the ω of the signal processing APF 604 are controlled. PL
Due to such an operation of the L circuit 103, ω becomes equal to 2π times the frequency of the write clock signal 110 even if the elements constituting the reference primary APF 601 and the signal processing APF 604 vary, and the phase characteristic of the APF Is no longer affected by element variations. Further, in the delay circuit constructed as shown in FIG. 2, each APF is controlled by controlling the APF constituting the delay circuit by the PLL circuit shown in FIG.
The phase characteristic of the write clock signal 1 is not affected by the element variation, and the delay characteristic of the delay circuit is not affected by the element variation.
It is determined by 10 frequencies f.

FIG. 7 is a diagram showing another configuration of the PLL circuit 103. In FIG. The PLL circuit 103 is a secondary APF for reference.
701, inverter 702, comparators 703 to 70
4, frequency phase comparator 705, charge pump 706,
APF 6 for signal processing, which is composed of a loop filter 707
04 on the same chip. The reference secondary APF 701 and the inverter 702 receive the Write Clock signal 110 as an input, and the frequency / phase comparator 705 outputs the reference secondary APF 701.
Is output to the comparator 703 and the output signal of the inverter 702 is output to the comparator 704.
The input signal is a pulsed signal. Write Clock
When the phase difference between the signal 110 and the output signal of the reference secondary APF 701 is shifted by 180 degrees, the phase difference between the output signal of the inverter 702 and the output signal of the reference secondary APF 701 becomes zero. The frequency / phase comparator 705 outputs an INC signal indicating a phase advance state or a DEC signal indicating a phase delay state for a time corresponding to a phase difference between two input signals. Upon receiving the INC signal, the charge pump 706 performs a charge operation on the loop filter 707 with a constant current for that time. Conversely, when the DEC signal is received, a discharge operation of a constant current is performed on the loop filter 707 for that time. The loop filter 707 calculates the charge,
The control signal is output by integrating the discharge operation, and the control signal controls the ω of the reference secondary APF 701 and the signal processing APF 604. By performing such an operation, the PLL circuit 103 sets ω of the reference secondary APF 701 to 2π times the frequency of the write clock signal 110 irrespective of the variation in the elements constituting the APF. Further, since the signal processing APF 604 and the PLL circuit 103 are formed on the same chip, the reference APF 701 and the signal processing AP
Since the element variation of F604 is the same, ω of the signal processing APF 604 is not affected by the element variation.

FIG. 8 shows a configuration diagram of the frequency synthesizer 102. The frequency synthesizer 102 includes an oscillator 801, frequency dividers 802 to 803, a phase comparator 80
4. Low-pass filter 805, VCO 806, register 10
It is composed of 1.

The frequency divider 802 divides the frequency of the clock signal f1 generated by the oscillator 801 by M in accordance with the value set in the register 101, and outputs a signal of frequency f1 / M. The frequency divider 803 divides the signal of the frequency f0 output from the VCO 806 by N according to the set value of the register 101, and
/ N is output. The phase comparator 804 has the frequency f1
The phase of the signal of / M is compared with the phase of the signal of frequency f0 / N, and a signal corresponding to the phase difference is output. The low-pass filter 805 receives the output signal of the phase comparator 804 as an input and outputs a control signal. The VCO 806 changes the frequency f0 of the output Write Clock signal 110 according to the control signal.
By operating the frequency synthesizer circuit 102 in this manner, the signal of the frequency f0 / N and the signal of the frequency f1 / M are synchronized, and the Write Cloc of the frequency f0 = (N / M) f1
The k signal 110 is obtained.

FIG. 9 shows the circuit of FIG.
04, with DACs 905-908. This circuit controls a control signal, which is an output signal of the PLL 103, by setting values of a plurality of independent registers.
The delay times of the delay circuits 111 to 114 can be independently set.

FIG. 10 shows a configuration diagram of a waveform shaping circuit in which a programmable filter 1001 for harmonic noise is added to the circuit of FIG. In the magnetic disk, the value of the register 101 is set according to the transfer speed, and the frequency synthesizer 10 is set according to the set value of the register 101.
2 outputs a Write Clock signal 110 of a specific frequency. The PLL 103 monitors the Write Clock signal 110 and outputs a control signal. The control signal controls the delay characteristic of the transversal circuit 104 and the cutoff frequency of the filter 1001. In this circuit, the filter 1001 is also a PLL 103 and a transversal circuit 104.
And the filter 100 on the same chip.
The cutoff frequency of 1 is determined by the frequency of the write clock signal 110 irrespective of the variation in the elements constituting the filter 1001.

FIG. 11 is a circuit diagram of a primary programmable LPF. FIG. 11 shows a variable Gm amplifier 11.
01 to 1102, and capacitors 1103 to 1104,
The cutoff frequency is

[0036]

(Equation 6)

## EQU3 ##

FIG. 12 is a circuit diagram of a secondary programmable LPF. FIG. 12 shows a variable Gm amplifier 12.
01 to 1204, capacity 1205 to 1208,
The cutoff frequency is

[0039]

(Equation 7)

## EQU4 ##

FIG. 13 shows the system of FIG.
301 to 1302 and DACs 1303 to 1304 are attached, and the delay time of the transversal circuit and the cutoff frequency of the filter are independently controlled.

FIG. 15 shows a configuration of a magnetic disk system using the transversal type waveform equalizing circuit 1510 of the present invention.
501, a read / write amplifier 1502 for amplifying a signal,
Signal processing unit 1511, VCM (Voice Coil Motor) 151
3. Mechanical control unit 1514, HDC (hard disk controller) 1505 for controlling data, I / O
CPU 1506 for controlling F1507, I / F (interface) 1507 for exchanging data, host 1508 for processing data, and PLL1 described above.
515 and a synthesizer 1516. The signal processing unit 1511 performs a waveform shaping circuit 1509 that generates a code pulse from the read signal, a waveform equalization circuit 1510, a data separator 1503 that generates a clock synchronized with the code pulse, and performs encoding / decoding to a recording code. It comprises an encoder / decoder 1504.

Hereinafter, a second embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIGS.

FIG. 16 shows an outline of a second embodiment of the present invention. 16 includes a register A101, a programmable filter 1601, a synthesizer 102,
This is a CDR compatible programmable filter system in a magnetic disk device, which is configured by a phase locked loop (PLL) 1603.

The register A101 is set to a certain value in accordance with the transfer speed of the magnetic disk, and the synthesizer 102 reads the value set in the register A101, and reads the frequency f0.
, A Write Clock signal 110 is generated. PLL1603
Inputs the Write Clock signal 110 and the filter 1601
A control signal 7 for controlling the cutoff frequency of the filter 1601 is output, and the cutoff frequency of the filter 1601 is controlled by the control signal 7. The frequency synthesizer 102 can be configured similarly to the one shown in FIG.

FIG. 17 shows a configuration example of the PLL 1603 in FIG. The circuit of FIG.
1, a multiplier 1702 and a loop filter 1705. The reference secondary filter 1701 is configured by a programmable filter whose cut-off frequency is variable similarly to the signal processing filter 1601.

The reference secondary filter 1701 is a Write Clo
The ck signal 110 is input, and a signal 1703 having a phase shifted by θ from the signal 110 is output. The multiplication circuit 1702 outputs the signal 11
The signal 1704 is multiplied by 0 to output a signal 1704.
The DC component of the signal 1704 becomes 0 only when the phase difference θ between the signal 1703 and the signal 110 is 90 °. In other cases, the DC component exists. The loop filter 1705 outputs the signal 1
The DC component 704 is extracted, and a control signal 1602 is output. The reference second-order filter 1701 receives the control signal 1602
The cutoff frequency is changed according to With the operation of the PLL circuit in this manner, the cutoff frequency of the reference secondary filter becomes equal to the frequency f0 of the write clock signal 110. The PLL circuit 1603 outputs a control signal 1602,
A control signal 1602 controls a cutoff frequency of the signal processing filter 1601.

FIG. 18 shows another configuration example of the PLL 1603 in FIG. The circuit in FIG. 18 includes a multiplier 1702, a loop filter 1705, a first-order reference filter 1801, an attenuator 26, and an adder 27. Reference 1
The next filter 1801 is configured by a programmable filter having a variable cutoff frequency, like the filter 1601 for signal processing.

The reference primary filter 1801 is a Write Clo
The ck signal 110 is input, and a signal 1804 whose phase is delayed by θ from the signal 110 is output. Attenuator 1806 is Writ
The e-clock signal 110 is input, the signal 110 is halved and output. The adder 1802 adds the signal 1703 and the output of the attenuator 1806. The multiplier 1803 multiplies the output of the adder 1802 by the Write Clock signal 110 and outputs a signal 1807. The DC component of the signal 1807 becomes 0 only when the phase difference θ between the signal 1804 and the signal 110 is 45 °. In other cases, the DC component exists. Loop filter 1805 extracts the DC component of signal 1807 and outputs control signal 1602. The primary filter for reference 1801 changes the cutoff frequency according to the control signal 1602. With the operation of the PLL circuit in this manner, the cutoff frequency of the primary filter for reference is changed to the write clock signal 11.
0 is equal to the frequency f0. The PLL circuit 1603 outputs a control signal 1602, and the cutoff frequency of the signal processing filter 1601 is controlled by the control signal 1602.

FIG. 19 shows an example in which an amplifier 1901 is added to the filter system shown in FIG. The amplifier 1901 multiplies the control signal 1602 output from the PLL 1603 by K times, and outputs the signal
601 is controlled. The cutoff frequency of the signal processing filter 1601 is increased by multiplying the control signal 1602 by K by the amplifier 1901 so that the frequency synthesizer 102
Can be set to K times the output signal frequency.

FIG. 20 shows the filter system of FIG.
AC2001 has been added. The DAC 2001 monitors a control signal 1602 which is an output of the PLL 1603, and controls the control signal 2002 according to the setting of the register A101.
Is output. Filter 1 for signal processing by control signal 2002
601 is controlled. In order for the DAC 2001 to make the control signal 1602 a magnification according to the setting of the register A101, the cutoff frequency of the signal processing filter 1601 is made a magnification corresponding to the transfer speed of the output signal frequency of the frequency synthesizer 102.

If the programmable filter of the present invention is used instead of the transversal type waveform equalizing circuit 1510 shown in FIG. 15, a magnetic disk system can be similarly constructed.

[0053]

According to the present invention, the write clock and the delay time of the transversal circuit can be set to desired values in the CDR-compatible magnetic disk device from the minimum register setting for a change in transfer speed. .

Further, since the delay circuit is controlled by the PLL circuit formed on the same chip as the transversal circuit, it is possible to suppress a variation in delay time due to a variation in elements.

Further, according to the present invention, it is possible to reduce the circuit scale of the CDR-compatible waveform equalizing circuit.

[Brief description of the drawings]

FIG. 1 is a system configuration diagram of a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a delay circuit of FIG. 1;

FIG. 3 is a configuration diagram of an example of the APF of FIG. 2;

FIG. 4 is a configuration diagram of another example of the APF of FIG. 2;

FIG. 5 is a Gm amplifier configuration diagram of FIGS.

FIG. 6 is a configuration diagram of an example of the PLL circuit of FIG. 1;

FIG. 7 is a configuration diagram of another example of the PLL circuit of FIG. 1;

FIG. 8 is a configuration diagram of the frequency synthesizer of FIG. 1;

FIG. 9 is a system configuration diagram to which the first embodiment of the present invention is applied.

FIG. 10 is a system configuration diagram to which the first embodiment of the present invention is applied.

FIG. 11 is a configuration diagram of a primary LPF of FIG. 10;

FIG. 12 is a configuration diagram of the secondary LPF of FIG. 10;

FIG. 13 is a system configuration diagram to which the first embodiment of the present invention is applied.

FIG. 14 is a configuration diagram of a conventional system.

FIG. 15 is a configuration diagram of a magnetic disk system according to the first embodiment of the present invention.

FIG. 16 is a system configuration diagram of a second embodiment of the present invention.

FIG. 17 is a configuration diagram of an example of the PLL of FIG. 16;

18 is a configuration diagram of another example of the PLL of FIG.

FIG. 19 is a system configuration diagram to which the second embodiment of the present invention is applied.

FIG. 20 is a system configuration diagram to which the second embodiment of the present invention is applied.

FIG. 21 is a configuration diagram of a conventional filter system.

FIG. 22 is a configuration diagram of a conventional filter system.

FIG. 23 illustrates the operation principle of the transversal circuit.

FIG. 24 is a diagram illustrating a configuration example of a programmable filter.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 ... Register, 102 ... Frequency synthesizer, 103 ... PLL, 104 ... Transversal circuit, 105-109 ... Variable gain amplifier, 110 ... Write Clock, 111-114 ... Delay circuit, 115 ... Adder, 1601 ... Filter for signal processing 1602 ... cut-off frequency control signal 1603 ... PLL.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Ryutaro Hotta 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Microelectronics Device Development Laboratory, Hitachi, Ltd. (72) Inventor Kenichi Hase Totsuka-ku, Yokohama-shi, Kanagawa 292 Yoshidacho Co., Ltd.Microelectronics Device Development Laboratory, Hitachi, Ltd. (72) Inventor Akihiko Hirano 292 Yoshidacho, Totsuka-ku, Yokohama, Kanagawa Prefecture, Japan Microelectronics Device Development Laboratory (72) Inventor Ken Urakami 5-20-1, Kamizuhoncho, Kodaira-shi, Tokyo Semiconductor Design & Development Center, Hitachi, Ltd. (56) References JP-A-2-7203 (JP, A) JP-A-3-219403 ( JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) G11B 5/09

Claims (7)

(57) [Claims] 1. A mechanism for reading / writing data on a magnetic disk and a control circuit therefor, a frequency synthesizer for generating a first clock signal having a frequency corresponding to the data transfer speed, and a first clock A phase synchronization circuit that generates a control signal in accordance with the frequency of the signal, a plurality of variable delay circuits each including a register and a DAC that independently set a delay time by the control signal and each independently set the delay time, An adder for adding and outputting the outputs of the plurality of variable delay circuits, and for equalizing the waveform of the original signal according to the control signal to output an equalized signal
A waveform equalization circuit , a waveform shaping circuit that generates a code pulse from the equalized signal, a data separator that generates a second clock signal synchronized with the code pulse, and a data separator that generates the code pulse by the second clock signal. A magnetic disk system comprising: a decoding circuit that performs decoding; and an encoding circuit that encodes recording data using the first clock signal. 2. The magnetic disk system according to claim 1, wherein a programmable filter whose cut-off frequency is controlled by said first clock signal is attached to said waveform equalizing circuit. 3. A second control circuit for independently controlling a delay time of the waveform equalizing circuit and a cutoff frequency of the programmable filter.
3. The magnetic disk system according to claim 2, wherein said control signal is accompanied by a DAC which is generated in accordance with a monitor of said control signal and a set value. 4. The magnetic disk system according to claim 1, wherein said waveform equalizing circuit is a programmable filter whose cutoff frequency is arbitrarily set by said control signal. 5. The magnetic disk system according to claim 4, further comprising an amplifier for setting the cutoff frequency to K times the frequency of the first clock signal. 6. A magnetic disk system according to claim 4, further comprising a DAC for setting said cutoff frequency to a magnification corresponding to a transfer rate of said first clock signal. 7. A frequency synthesizer for generating a signal of an arbitrary frequency in accordance with a transfer rate of an original signal; a phase synchronizing circuit for generating a control signal in accordance with a frequency of an output signal of the frequency synthesizer; A plurality of variable delay circuits each having a register and a DAC each of which delays the original signal by an arbitrary delay time and independently sets the delay time; and an adder for adding and outputting the outputs of the plurality of variable delay circuits. A waveform equalizer comprising: a semiconductor integrated circuit.