JP3559914B2 - Clock generation circuit - Google Patents

Description

[0001]
[Industrial applications]
The present invention relates to a clock generation circuit for generating a master clock serving as a reference when digital signal processing is performed in, for example, audio and video equipment.
[0002]
[Prior art]
In recent years, with the development of digital technology, it has become possible to record and reproduce sound very close to the original sound using PCM sound based on the sampling theorem. With respect to high-quality sound reproduction, with the advent of compact discs (hereinafter referred to as CDs), it has become possible to reproduce PCM sound having a sampling frequency of 44.1 kHz and a quantization bit number of 16 bits. For high-quality recording, a digital audio tape recorder (hereinafter referred to as "DAT") uses a sampling method of 48 kHz and a quantization bit number of 16 bits for standard recording, and a sampling frequency of 32 kHz and a quantization bit number of 12 for long-time recording. Depending on the bit recording method, high-quality recording and reproduction can be achieved.
[0003]
Currently, three main sampling frequencies used for recording and reproducing digital audio are 48 kHz and 32 kHz, and 44.1 kHz for recording and reproducing CD audio. The clock necessary for signal processing for recording and reproducing digital audio using these three frequencies is always a frequency synchronized with the sampling frequency, that is, the sampling frequency f._SIs set to an integral multiple of. The master clock currently used for digital audio signal processing has a sampling frequency f_S256f which is 256 times_SIs 384 times 384f_SWhich is 512 times 512f_SA clock necessary for signal processing can be generated by appropriately dividing the frequency of the master clock.
[0004]
To simply generate a clock, an LC oscillator using a coil and a capacitor is sufficient, but there are problems in terms of oscillation accuracy, frequency stability, and the like. A clock oscillation circuit using a crystal oscillator for generating a master clock and an inverting amplifier is used. This crystal oscillator also differs in the oscillation frequency and oscillation accuracy required by audio equipment. For example, in the case of a CD, the sampling frequency f_SIs 44.1 kHz only, so that 256 f_SWhen one is used, one crystal oscillator of 256 × 44.1 kHz = 11.289 MHz is required.
[0005]
In the case of DAT, the sampling frequency f_SAre three types, so the master clock has 256f_SIs used, a total of three crystal oscillators having different oscillation frequencies of 256 × 32 kHz = 8.192 MHz, 256 × 48 kHz = 12.288 MHz, 256 × 44.1 kHz = 11.289 MHz are required.
[0006]
An example of the use of such a crystal oscillator is described in, for example, the radio technology magazine “Radio Technology”, April 1991, issued by AI Publishing Co., Ltd. FIG. 14 shows “Sony TCD-D3, DAT Walkman”. FIG. 3 is a block diagram of a signal processing circuit of DAT shown in “Searching for Attractiveness”. At the time of recording, the audio signals input to the recording audio input terminals 100, 100 are amplified by the line amplifiers 103, 103. The amplified signal is input to an AD converter 104, and the AD converted digital signal is input to a digital signal processor (hereinafter referred to as DSP) 105, which performs signal processing in accordance with a recording format, and then inputs the RF signal to an RF amplifier 107. Then, after being amplified to a signal level sufficient for recording on the magnetic tape 121, it is recorded on the magnetic tape 121 via the recording / reproducing head 108.
[0007]
On the other hand, at the time of reproduction, reproduction data from the magnetic tape 121 is taken out as a reproduction signal by the magnetic head 108, then amplified by the RF amplifier 107, and the amplified reproduction signal is input to the DSP 105 to perform reproduction signal processing. The output signal of the DSP 105 generates a digital output by the digital I / O controller 116, is input to the digital filter 110, limits the band, and performs DA conversion by the DA converter 111. Then, the reproduction signals passed through the high-frequency cutoff amplifiers 112, 112 are output to line output terminals 115, 115 and reproduced as analog audio signals.
[0008]
The signal processing of the DSP 105 usually has a sampling frequency f_SIs used as the frequency of the reference clock, and here, three sampling frequencies f of 32 kHz, 44.1 kHz and 48 kHz are used._SIn correspondence with each of them, a clock is generated by using three crystal oscillators 122a, 122b, and 122c in the sampling frequency oscillation circuit 106.
Also, with respect to a recording medium during reproduction, for example, a DAT using a magnetic tape and a rotary head, vibrations are generated in the magnetic tape due to friction between the tape and the rotary head and other disturbances due to the recording structure, and reproduced audio data, Clock jitter occurs. In this state, the audio data is interrupted or an abnormal sound is generated even if the reproduction data processing is performed. Therefore, usually, a PLL (Phase (Phase)) for synchronizing the reproduced audio data with a reference clock and obtaining stable audio data is used. Lock Loop) circuit is provided.
[0009]
FIG. 15 is a block diagram of a general PLL circuit.
The input clock 5 at the time of reproduction including jitter and the output clock 6 not including jitter are input to the phase comparator 1 and compared in phase. The output of the phase comparator 1 is normally set to a predetermined voltage when the phase difference between the two inputs is 0. For example, the voltage value is shifted in the positive direction in the case of the leading phase, and in the negative direction in the case of the lagging phase. Change in proportion to the phase difference. The output of the phase comparator 1 is input to a VCO (Voltage Controlled Oscillator) 3 after removing high frequency components by a low-pass filter 2. The VCO 3 can change its oscillation frequency in accordance with a change in the input voltage, and outputs a clock having an oscillation frequency corresponding to the input voltage. When the oscillation frequency of the VCO 3 is higher than the frequency of the input clock 5, the frequency divider 4 outputs the output clock 6, which is a fraction of an integer, and feeds it back to the phase comparator 1. The output clock 6 is used as a clock having extremely high frequency stability by the VCO 3 for subsequent signal processing.
[0010]
In the recording and reproduction of the digital audio signal, a frequency 256 times the normal sampling clock is set as the reference frequency of the VCO 3. For example, sampling frequency f_SIs 48 kHz × 256 = 12.288 MHz when the frequency is 48 kHz, and 11.289 MHz when the frequency is 44.1 kHz, and 8.192 MHz when the frequency is 32 kHz. Accordingly, when performing the recording / reproducing process of the audio signal corresponding to the three kinds of sampling frequencies, it is necessary to use the VCO 3 corresponding to each of these three kinds of frequencies in the PLL circuit.
[0011]
[Problems to be solved by the invention]
Since the conventional clock oscillation circuit is configured as described above, when recording and reproducing digital audio signals using a plurality of types of sampling frequencies, each of the sampling frequencies is expensive and has a large component mounting area. However, it is necessary to provide a crystal oscillator or a coil having a large width, which causes a problem of increasing the product cost. In addition, there is a problem that a large component mounting area is required, and the product cannot be reduced in size and weight.
In view of the above problems, it is an object of the present invention to provide a clock generation circuit that generates a master clock using a small number of crystal oscillators or coils for digital processing of an audio signal using a plurality of types of sampling frequencies. I do.
[0012]
[Means for Solving the Problems]
A clock generation circuit according to a first aspect of the present invention includes a reference clock generation circuit that generates a reference clock signal, and a 6n (n is a positive integer) frequency-divided reference clock signal generated by the reference clock generation circuit. And a delay circuit that delays and outputs the clock signal output by the 6n frequency divider using the period of the reference clock signal as a unit of delay time,The delay circuit is configured to output a clock signal obtained by delaying the clock signal output by the 6n frequency divider by 周期 cycle of the clock signal, and to output the clock signal output by the delay circuit and the 6n The reference clock signal is frequency-divided by 3n (n is a positive integer) using an exclusive OR operation with the clock signal output from the frequency dividerIt is characterized by outputting a clock signal.
[0014]
No.2The clock generation circuit according to the invention further includes a 2n frequency divider for dividing the reference clock signal by 2n (n is a positive integer), and the 2n frequency divider outputs a clock signal divided by 2n. It is characterized by.
[0015]
No.3A clock generation circuit according to the present invention includes a reference clock generation circuit that generates a reference clock signal, and an n divider that divides the reference clock signal output by the reference clock generation circuit by n (n is a positive integer) and outputs the result. , A ternary counter for counting the clock signal output from the n-frequency divider.By inverting the upper bit signal,The reference clock signalAnd the reference clock signal is frequency-divided by 3n.It is characterized by outputting a clock signal.
[0016]
No.4A clock generation circuit according to the present invention includes: a reference clock generation circuit for generating a reference clock signal; and a 3n frequency divider for dividing the reference clock signal generated by the reference clock generation circuit by 3n (n is a positive integer) and outputting the result. And a delay circuit that delays and outputs the clock signal output by the 3n frequency divider using the period of the reference clock signal as a unit of delay time, wherein the clock signal output by the 3n frequency divider and the delay Clock signal output by the circuitUsing the exclusive OR operation of, Wherein a clock signal obtained by dividing the reference clock signal by (3/2) n is output.
[0017]
No.5The clock generation circuit according to the invention includes a clock signal output from the n frequency divider.When,The ternary counter outputBy the logical product of the upper bit signal and the inverted signal, Wherein a clock signal obtained by dividing the reference clock signal by (3/2) n is output.
[0018]
No.6A clock generation circuit according to the present invention includes: a reference clock generation circuit that generates a reference clock signal; and an m divider that divides and outputs the reference clock signal generated by the reference clock generation circuit by m (m is a positive integer). A voltage-controlled oscillator that selectively oscillates and outputs a plurality of types of clock signals, and a clock that is output by the m-divider according to the clock signal that is selectively output by the voltage-controlled oscillator. A programmable frequency divider that divides and outputs the frequency of the signal to a frequency of the signal; and a phase comparator that compares the phases of the clock signal output by the m frequency divider and the clock signal output by the programmable frequency divider; Comparison result of phase comparatorSo that the phase difference, Wherein the frequency of the clock signal output from the voltage controlled oscillator is controlled.
[0027]
[Action]
In the clock generation circuit according to the first invention, the reference clock generation circuit generates a reference clock signal, and the 6n frequency divider divides the reference clock signal by 6n (n is a positive integer) and outputs the result. The delay circuitA clock signal obtained by delaying the clock signal output by the 6n frequency divider by one-fourth cycle of the clock signal is output, and an exclusive logic of the clock signal output by the delay circuit and the clock signal output by the 6n frequency divider is output. A clock signal obtained by dividing the reference clock signal by 3n (n is a positive integer) using the sum is output.
[0029]
No.2In the clock generation circuit according to the present invention, the 2n frequency divider divides the reference clock signal by 2n (n is a positive integer), and the 2n frequency divider outputs a 2n frequency-divided clock signal.
[0030]
No.3In the clock generation circuit according to the present invention, the reference clock generation circuit generates a reference clock signal, and the n frequency divider divides the reference clock signal by n (n is a positive integer) and outputs it. The ternary counter counts the clock signal output by the n divider, and the ternary counter outputsBy inverting the upper bit signal,Reference clock signalAnd the reference clock signal is frequency-divided by 3n.Outputs a clock signal.
[0031]
No.4In the clock generation circuit according to the invention, the reference clock generation circuit generates a reference clock signal, and the 3n frequency divider divides the reference clock signal by 3n (n is a positive integer) and outputs the result. The delay circuit delays and outputs the clock signal output from the 3n frequency divider using the period of the reference clock signal as a unit of the delay time. Based on the clock signal output from the 3n frequency divider and the clock signal output from the delay circuit, a clock signal obtained by dividing the reference clock signal by (3/2) n is output.
[0032]
No.5In the clock generation circuit according to the present invention, the clock signal output by the n frequency dividerWhen,Ternary counter outputBy the logical product of the upper bit signal and the inverted signal, And outputs a clock signal obtained by dividing the reference clock signal by (3/2) n.
[0033]
No.6In the clock generation circuit according to the invention, the reference clock generation circuit generates a reference clock signal, and the m frequency divider divides the reference clock signal by m (m is a positive integer) and outputs the result. A voltage controlled oscillator selectively oscillates and outputs a plurality of types of clock signals, and a programmable frequency divider generates the clock signal according to the clock signal selectively output by the voltage controlled oscillator. The frequency is divided into the frequency of the output clock signal and output. The phase comparator compares the phases of the clock signal output from the m frequency divider and the clock signal output from the programmable frequency divider, and the comparison result of the phase comparatorSo that the phase differenceControls the frequency of the clock signal output by the voltage controlled oscillator.
[0042]
【Example】
Hereinafter, the present invention will be described in detail with reference to the drawings showing examples.
FIG. 1 is a block diagram of a reference clock generation circuit which is a part of the clock generation circuit according to the present invention. An inverting amplifier 23 and a resistor 24 are connected in parallel to the crystal oscillator 22. One terminal and the other terminal of the crystal oscillator 22 are grounded via capacitors 25 and 25. A reference clock generation circuit 41 is configured by the crystal oscillator 22, the inverting amplifier 23, the resistor 24, and the capacitors 25 and 25. Since the oscillation frequency of the reference clock generation circuit 41 is determined by the inductance value of the crystal oscillator 22 and the capacitance of the capacitors 25 and 25, the use of the crystal oscillator 22 having the same circuit configuration and different inductances enables Sampling frequency f_S, A master clock required for digital audio signal processing corresponding to the clock can be generated.
[0043]
In FIG. 1, a reference clock is generated by using a crystal oscillator 22 of 24.576 × n MHz (48 k × 512 nHz) (n is a positive integer).(Reference clock signal)40 is generated. FIG. 2 shows a case where n = 1 and a clock of 48 k × 256 Hz and a clock of 32 k × 256 Hz from a reference clock of 24.576 × n MHz (48 k × 512 nHz).(Clock signal)FIG. 2 is a block diagram of a first embodiment of a clock generation circuit according to the present invention for generating a clock. The reference clock 40 of 24.576 × n MHz is input to the 2n frequency divider 26, 6n frequency divider 27 and n frequency divider 28. The output clock of the 6n frequency divider 27 is input to one input terminal of a D flip-flop circuit 29 and an exclusive OR circuit (hereinafter referred to as an EXOR circuit) 31. The output of the D flip-flop circuit 29 is input to the D flip-flop circuit 30, and the output is input to the other input terminal of the EXOR circuit 31. The output clock of the n frequency divider 28 is input to each clock terminal of the D flip-flop circuits 29 and 30 via the inverter circuit 33. The 6n frequency divider 27, the n frequency divider 28, the D flip-flop circuits 29 and 30, the inverter circuit 33, and the EXOR circuit 31 constitute a three frequency divider 34.
[0044]
Next, the operation of the clock generation circuit will be described with reference to FIG.
The reference clock 40 shown in FIG. 3A of 24.576 MHz (48 k × 512 MHz) generated by the reference clock generation circuit 41 shown in FIG. 1 is divided by 2 by the 2n frequency divider 26 (n = 1). Then, the sampling frequency f shown in FIG._S  = Master clock for 48kHz(Master clock signal)  256f_S    (48 k × 256 MHz) can be generated. The reference clock 40 is frequency-divided by 6 (n = 1) by the 6n frequency divider 27, and the output clock of the 6n frequency divider 27 is output.(Output clock signal)A is as shown in FIG. Then, the output clock A is input to the D flip-flop circuit 29 and the EXOR circuit 31.
[0045]
On the other hand, an inverted clock obtained by inverting the output clock obtained by dividing the reference clock 40 by n by the n divider 28 by the inverter circuit 33 is input to the clock terminals of the D flip-flops 29 and 30, and the inverted clock of the inverted clock is output from the D flip-flop 29. 0.5 clocks of the clock divided by n in synchronization with the rising edge(Period)The delayed clock B shown in FIG. 3D is output. The clock B is input to the D flip-flop circuit 30 and is one clock of the clock divided by n by the D flip-flop circuit 30.(Period)As shown in FIG. 3E, the D flip-flop circuit 30291/4 clock of this clock from the clock input to( Period )The delayed clock C is output. When this clock C is input to the EXOR circuit 31 and the exclusive OR of the clock A and the clock C is established, the EXOR circuit 31 outputs a master clock having a frequency of 32 k × 256 Hz and a duty of 50% as shown in FIG. Can occur.
[0046]
In the case of n = 1, the output clock of the n frequency divider 28 is the same as the input clock. Therefore, it is not necessary to provide a frequency divider. That is, the clock 256f_SCan be generated.
Also, in the case of n ≧ 2, since the respective frequency division ratios of the n frequency divider 28, the 2n frequency divider 26, the 6n frequency divider 27, and the 3n frequency divider 34 correspond to the change of n, Similarly, a master clock having a frequency of 32 k × 256 Hz and a duty of 50% can be generated. In this embodiment, the clock divided by 6n is delayed by 1/4 clock by the inverter circuit 33 and the D flip-flop circuits 29 and 30. Instead, the delay circuit can be delayed by 1/4 clock. The same effect can be obtained by using.
[0047]
It should be noted that the reference clock 40 is generated in the same manner as described above by using the coil 50 having inductance as shown in FIG. be able to.
[0048]
FIG. 5 is a block diagram of a second embodiment of the clock generation circuit according to the present invention.
In this case, n = 1, and a clock of 32 k × 256 Hz is realized by a synchronous clock from a reference clock of 24.576 × n MHz (48 k × 512 nHz). The 48 k × 512 nHz reference clock 40 is input to the 2n frequency divider 26 and the n frequency divider 28. The output clock of the n frequency divider 28 is input to the ternary counter 32. Upper bit COUNT of output of ternary counter 32_a[1] is input to the inverter circuit 33.
[0049]
Next, the operation of the clock generation circuit will be described with reference to FIG.
The 24.576 MHz (48 k × 512 Hz) reference clock 40 shown in FIG. 6A generated by the above-described reference clock generation circuit 41 is frequency-divided by 2n by the 2n frequency divider 26 to output a 12.288 MHz clock. . The reference clock 40 is input to the ternary counter 32 which divides the frequency by 1 (n = 1) by the n frequency divider 28, that is, obtains a 2-bit output without performing the frequency division processing. Upper bit, lower bit COUNT of the output of the ternary counter 32_a[1: 0] is generated. This upper bit COUNT_aBy inverting [1] by the inverter circuit 33, a synchronous clock of 32 k × 256 Hz shown in FIG. 6D synchronized with the reference clock 40 can be generated.
[0050]
In the case of n ≧ 2, the output clock of the n frequency divider 28 is a clock having a constant cycle regardless of the change of n, so that a 32k × 256 Hz synchronous clock can be generated as in the case of n = 1.
Also, as described above, the reference clock 40 can be generated by the coil 50 and the capacitor 25 using the coil 50 instead of the crystal oscillator 22.
[0051]
FIG. 7 is a block diagram of a third embodiment of the clock generation circuit according to the present invention, where n = 1 and the reference clock 40 is 12.288 × n MHz (48 k × 256 nHz). The reference clock 40 is input to the n-divider 28 and the 3n-divider 35, and a clock of 12.288 MHz is output from the n-divider 28. The output clock of the 3n frequency divider 35 is input to one input terminal of the D flip-flop circuit 42 and the EXOR circuit 36. The output of the D flip-flop circuit 42 is input to another input terminal of the EXOR circuit 36.
[0052]
Next, the operation of the clock generation circuit will be described with reference to FIG. The reference clock 40 of 12.288 MHz shown in FIG. 8A generated by the reference clock generation circuit 41 shown in FIG. 1 is inputted to the 3n divider 35, divided by 3 (n = 1), and divided by 3n. The output clock of the unit 35 is the clock D shown in FIG. The clock D is input to the D flip-flop 42 and the EXOR circuit 36, and the D flip-flop 42 outputs a clock E shown in FIG. The clock E is input to the EXOR circuit 36, and the EXOR circuit 36 can generate a clock of 8.192 MHz (32 k × 256 Hz) shown in FIG. 8D by exclusive OR of the clocks D and E.
[0053]
In the case of n ≧ 2, the 3n divider 35 generates a predetermined signal D in response to the change of n, so that, as in the case of n = 1, 8.192 MHz (32 k × 256 Hz). A clock can be generated.
Further, the reference clock 40 similar to that of the crystal oscillator 22 can be generated by the coil 50 and the capacitor 25 using the coil 50 instead of the crystal oscillator 22.
[0054]
FIG. 9 is a block diagram of a clock generating circuit according to a fourth embodiment of the present invention, where n = 1 and the reference clock 40 is 12.288 MHz × n MHz (48 k × 256 nHz). The reference clock 40 is input to the n frequency divider 28a and the n frequency divider 28b, and a clock of 12.288 MHz is output from the n frequency divider 28a. The output clock of the n frequency divider 28b is input to the ternary counter 32 and one input terminal of the AND circuit 45. Upper bit COUNT of output of ternary counter 32_b[1] and lower bit COUNT_bOf [0], upper bits COUNT_b[1] is input to the other input terminal of the AND circuit 45 via the inverter circuit 33.
[0055]
Next, the operation of this clock generation circuit will be described with reference to FIG. A reference clock 40 of 12.288 MHz (48 k × 256 nHz) generated by the reference clock generation circuit 41 shown in FIG. 1 is input to the n frequency divider 28 a and divided by 1 (n = 1) to generate a clock of 12.288 MHz. Output. In addition, a clock F shown in FIG. 10A is input to the ternary counter 32 and the AND circuit 45 without dividing the frequency by n by the n frequency divider 28b. As shown in FIG. 10B, the ternary counter 32 outputs the upper bit and the lower bit COUNT of the output of the ternary counter._b[1, 0] is generated. And the upper bits COUNT_bThe signal G of [1] is inverted by the inverter circuit 44, and the inverted signal H shown in FIG. 10D is input to the AND circuit 45. Then, the AND circuit 45 can generate a clock of 8.192 MHz (32 k × 256 Hz) shown in FIG. 10E by ANDing the clock F and the signal H.
[0056]
When n ≧ 2, the clock of 12.288 × n MHz is frequency-divided by n by the n frequency divider 52, so that, as in the case of n = 1, 8.192 MHz (32 k × 256 Hz) Clock can be generated.
Further, the same reference clock 40 as in the case where the crystal oscillator 22 is used can be generated by the coil 50 and the capacitor 25 using the coil 50 instead of the crystal oscillator 22.
[0057]
FIG. 11 is a block diagram of a clock generating circuit according to a fifth embodiment of the present invention, where n = 1, and the reference clock 40 is 12.288 MHz.times.n (48 k.times.256.times.nHz) to reproduce digital audio. FIG. 3 is a block diagram for generating a reference clock at the time of recording using a PLL circuit used at the time.
[0058]
The 12.288 × n MHz reference clock 40 generated by the reference clock generation circuit 41 shown in FIG. 1 is divided by the 122880 (48 × 256 × 10n) frequency divider 37 into a 100 Hz clock J. Sampling frequency f_SIs input to the VCO 3 and the programmable frequency divider 38 to become "1" when the frequency is 44.1 kHz and "0" when the frequency is 32 kHz. When the mode signal 39 is “1”, the output frequency of the VCO 3 is set to 44.1 k × 256 Hz, and the frequency division ratio of the programmable frequency divider 38 is set to 112896 (44.1 × 256 × 10n). As a result, the clock P output from the programmable frequency divider 38 is frequency-divided into a 100 Hz clock P, similarly to the output clock J of the 122880n frequency divider 37. FIG. 12 is a timing chart of the clock J and the clock P.
[0059]
Although the frequency of the clocks J and P is set to 100 Hz, since the frequency actually becomes 100 ± αHz, the phase difference θ between the two clocks J and P is detected. The phase is input to the device 1 and the phases are compared. FIG. 13 is a characteristic diagram showing the relationship between the ideal input / output characteristics of the phase comparator 1 and the output frequency of the VCO 3. The vertical axis represents the output voltage V of the phase comparator 1, and the horizontal axis represents the clock J. The phase difference θ of the clock P is assumed.
[0060]
Figure12In the clock timing chart shown in FIG._a2, The phase difference of clock P2 with respect to clock J is θ_b2, The phase difference of clock P3 with respect to clock J is θ_a1, The phase difference of clock P4 with respect to clock J is θ_b1(Θ_a1, Θ_a2> 0, θ_a1<Θ_a2, Θ_b1, Θ_b2<0, θ_b1<Θ_b2<0). Then, as is clear from FIG._a1, Θ_a2, Θ_b1, Θ_b2Output voltages of the phase comparator 1 with respect to_a1, V_a2  (V_a1, V_a2> 0), V_b1, V_b2  (V_b1, V_b2<0), and the output voltage V shows a linear characteristic with respect to the phase difference θ. Then, the output voltage of the phase comparator 1 is input to the VCO 3 via the low-pass filter 2, and controls the oscillation frequency in a direction in which the phase difference θ approaches 0.
[0061]
The operation of the PLL circuit is such that the phase difference θ between the clocks J and P input to the phase comparator 1 is within a predetermined range, for example, the phase difference θ in FIG._b1From θ_a1Is within the range, the output voltage of the phase comparator 1 has a substantially constant value. Since this output voltage is input to a voltage control terminal (not shown) of the VCO 3 through the low-pass filter 2, the output frequency of the VCO 3 becomes a predetermined value, and the clocks J and P maintain a synchronous relationship.
[0062]
The output frequency of VCO 3 at this time is frequency f₂To f₃And a clock (44.1k × 256 Hz) which is stable in the above frequency range and has a stable frequency can be obtained. Note that the phase difference is θ> θ_a1, Θ <θ_b1In this case, the synchronization state is broken, and the output voltage of the VCO 3 changes the output frequency in a direction to maintain a stable state.
When the mode signal 39 is “1” as described above, the VCO 3 generates a clock having a frequency of 44.1 k × 256 Hz. However, by setting the mode signal 39 to “0”, the VCO 3 A clock having a frequency of 32 k × 256 Hz is generated, and a clock having a stable frequency is output as in the case where the mode signal 39 is “1”.
[0063]
Also, in the case of n ≧ 2, since the frequency division ratio of the 122880n frequency divider 37 and the programmable frequency divider 38 corresponds to the change of n, the frequency of the clocks J and P input to the phase comparator 1 is In each case, the frequency is 100 Hz, and a stable clock of 44.1 k × 256 Hz or 32 k × 256 Hz can be obtained as in the case of n = 1.
[0064]
In this embodiment, an oscillator whose reference clock 40 oscillates at 48 k × 256 nHz is used, and the voltage and frequency are controlled by the VCO 3 to obtain a clock of 32 k × 256 Hz or 44.1 k × 256 Hz. However, the present invention is not limited to these frequencies, and the same applies to a configuration using an oscillation circuit having a reference clock of 32 reference × 256 nHz (8.192 × n MHz) or 44.1 k × 256 nHz (11.2896 × n MHz). The effect is obtained.
[0065]
Further, since the configuration itself of the PLL circuit is also used for reproducing digital audio, it can be easily implemented without adding any circuit.
Furthermore, the reference clock 40 can be generated by using the coil 50 instead of the crystal oscillator 22 in the reference clock generation circuit 41 and using the coil 50 and the capacitor 25 as in the case where the crystal oscillator 22 is used.
[0066]
【The invention's effect】
As described in detail above, according to the present invention, the number of oscillation elements or coils for generating a reference clock corresponding to a required sampling frequency can be reduced, and the circuit area of a clock generation circuit can be reduced. At the same time, the manufacturing cost of the clock generation circuit can be reduced. Also, since the number of oscillation elements or coils for generating the reference clock corresponding to the required sampling frequency can be reduced, the mounting area of other circuits mounted on the product mounting the clock generation circuit can be increased, and the clock can be increased. The product on which the generator circuit is mounted can be reduced in size and weight.
[0067]
In addition, since a sampling clock for recording is created by using a PLL circuit for digital audio reproduction signal processing, there is no increase in the number of circuits, and a small number of oscillation elements or coils are used. Can be generated stably.
In addition, it is easy to use a normal binary counter for the frequency divider itself, and in the case of making an LSI, the amplification of the circuit is slight and the realization is easy. Therefore, in the clock generation circuit of the present invention, in which a frequency divider needs to be added, excellent effects such as a greater effect of reducing the number of circuit components such as oscillation elements can be obtained.
[Brief description of the drawings]
FIG. 1 is a block diagram of a reference clock oscillation circuit using a crystal oscillator.
FIG. 2 is a block diagram of a first embodiment of a clock generation circuit according to the present invention.
FIG. 3 is a timing chart of clocks of respective units.
FIG. 4 is a block diagram showing another configuration of the reference clock oscillation circuit.
FIG. 5 is a block diagram of a clock generating circuit according to a second embodiment of the present invention.
FIG. 6 is a timing chart of clocks of respective units.
FIG. 7 is a block diagram of a third embodiment of the clock generation circuit according to the present invention.
FIG. 8 is a timing chart of clocks of respective units.
FIG. 9 is a block diagram of a clock generating circuit according to a fourth embodiment of the present invention.
FIG. 10 is a timing chart of clocks of respective units.
FIG. 11 is a block diagram of a clock generating circuit according to a fifth embodiment of the present invention.
FIG. 12 is a timing chart of clocks of respective units.
FIG. 13 is a characteristic diagram showing a relationship between input / output characteristics of a phase comparator, a phase difference, and an output frequency of a VCO.
FIG. 14 is a block diagram of a PLL circuit in a conventional clock generation circuit.
FIG. 15 is a block diagram of a conventional DAT signal processing circuit.
[Explanation of symbols]
1 phase comparator, 3 VCO (voltage controlled oscillator), 22 crystal oscillator, 25 capacitor, 26 2n frequency divider, 276n frequency divider, 28, 28a, 28b n frequency divider, 29, 30D flip-flop, 31 EXOR circuit, 32 ternary counter, 33 inverter circuit, 35 3n frequency divider, 36 EXOR circuit, 37 122880n frequency divider, 38 programmable frequency divider, 41 reference clock generation circuit, 42 D flip-flop, 45 AND circuit, 50 coils.

Claims (6)

A reference clock generation circuit for generating a reference clock signal, a 6n frequency divider for dividing and outputting the reference clock signal generated by the reference clock generation circuit by 6n (n is a positive integer), and a period of the reference clock signal as the unit of delay time, and a delay circuit for delaying and outputting the clock signal the 6n divider is output, the delay circuit 1 a clock signal the 6n divider is an output of the clock signal A clock signal delayed by / 4 cycle, and using the exclusive OR operation of the clock signal output by the delay circuit and the clock signal output by the 6n frequency divider, A clock generating circuit for outputting a clock signal obtained by dividing a signal by 3n (n is a positive integer) . 2. The clock generation circuit according to claim 1 , further comprising a 2n frequency divider for dividing the reference clock signal by 2n (n is a positive integer), wherein the 2n frequency divider outputs a clock signal divided by 2n . A reference clock generation circuit for generating a reference clock signal, an n frequency divider for dividing the reference clock signal output by the reference clock generation circuit by n (n is a positive integer) and outputting the same, and an output of the n frequency divider A ternary counter that counts the clock signal that has been converted, and inverts the higher-order bit signal output by the ternary counter, thereby synchronizing with the reference clock signal and outputting a clock signal obtained by dividing the reference clock signal by 3n. A clock generation circuit characterized by what it does . A reference clock generating circuit for generating a reference clock signal, the reference clock generation circuit 3 n a reference clock signal generated is (n is a positive integer) and 3 n divider to output divider to the reference clock signal A delay circuit that delays and outputs the clock signal output by the 3n frequency divider using the period of the above as a unit of delay time, the clock signal output by the 3n frequency divider and the clock signal output by the delay circuit A clock signal obtained by dividing the reference clock signal by (3/2) n using the exclusive OR operation of the above . In order to output a clock signal obtained by dividing the reference clock signal by (3/2) n by ANDing a clock signal output from the n-frequency divider and an inverted signal of an upper bit signal output from the ternary counter. 4. The clock generation circuit according to claim 3, wherein the clock generation circuit is provided. A reference clock generation circuit for generating a reference clock signal; an m frequency divider for dividing the reference clock signal generated by the reference clock generation circuit by m (m is a positive integer) and outputting the divided frequency; A voltage-controlled oscillator that oscillates and outputs a clock signal; and divides the clock signal into a frequency of the clock signal output by the m-divider according to a clock signal selectively output by the voltage-controlled oscillator. A programmable frequency divider for outputting the clock signal; and a phase comparator for comparing the phase of the clock signal output from the m frequency divider with the phase of the clock signal output from the programmable frequency divider. A clock generation circuit for controlling a frequency of a clock signal output from the voltage-controlled oscillator so that a phase difference becomes zero .

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