JPH06237146A - Filter system - Google Patents

Abstract

PURPOSE:To provide the filter system coping with a low voltage processing system by correcting the fluctuation of a filter gain caused by a cut-off frequency change in the filter in the signal processing filter system in a read channel of a magnetic disk or the like. CONSTITUTION:This system is made up of a cut-off frequency variable filter 1, a VGA(variable gain amplifier) 2, a register 3 and a D/A converter 4, and a means generating a gain control signal 6 in response to the filter cut-off frequency, which generates the control signal 6 to control the gain of the VGA (variable gain amplifier) 2. Thus, the fluctuation of the gain attended with a change in the filter cut-off frequency is corrected by the VGA (variable gain amplifier) 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a filter circuit capable of setting an arbitrary cutoff frequency, and more particularly to a signal processing filter system in a read channel such as a magnetic disk.

[0002]

2. Description of the Related Art Conventionally, filters include passive filters composed of passive elements such as resistors, capacitors, and coils, and active filters using OP amplifiers. These filters have filter characteristics, particularly cutoff frequency, depending on the application. The cutoff frequency was fixed. 2. Description of the Related Art In recent years, along with the trend toward smaller size and larger capacity of systems, a method of changing the frequency of a signal to be used in a system using a filter has begun to be used.

Particularly in magnetic disks, CDR (Constant) is a new recording method for increasing the storage capacity.
Density Recording) has been devised. In the CDR system, the transfer speed is changed between the inner circumference and the outer circumference of the disc, and the frequency component of the read data changes. Therefore, it is necessary to make the cutoff frequency of the filter circuit that performs signal processing variable according to the transfer speed. There is.

In a system in which the signal frequency handled in this way changes, a cutoff frequency variable filter that makes the cutoff frequency of the filter variable is required.

A conventional filter system will be described with reference to FIGS. 6, 12 and 13.

A conventional cutoff frequency variable filter system will be described with reference to FIG. A conventional filter system is described in the SSI 32F8011 data sheet.

FIG. 13 shows an outline of a conventional filter system, which comprises a variable cutoff frequency filter 1 and a fixed gain amplifier 52.

The cutoff frequency of the variable cutoff frequency filter 1 is controlled by the filter control signal 5 according to the set value of the filter cutoff frequency.

FIG. 6 is a cut-off frequency variable first-order LPF.
The structure of a (low-pass filter) 15 is shown, in which variable transconductance amplifiers 11 and 12 and capacitors 13 and 14 are shown.
Composed of. The cut-off frequency of the LPF (low-pass filter) 15 is the variable transconductance amplifier 1
It can be made variable by controlling the conductances Gm of 1 and 12. At this time, the gain A of the LPF (low pass filter) is set to the variable transconductance amplifier 1
Using the output impedance Zo of 1 and 12,

[0010]

[Equation 1]

Therefore, if Gm is changed, LP
The gain A of F (low pass filter) fluctuates.

Therefore, in the conventional filter system as shown in FIG. 13, there is a problem that the gain of the filter also changes with the change of the cutoff frequency of the filter.

FIG. 12 is a system configuration diagram of a magnetic disk. A signal processing block 38 includes an AGC (Automatic Gain Control) amplifier 45 for keeping the signal amplitude constant, and an AGC control circuit 4 for controlling the AGC amplifier 45.
6. Equalizer 47 for pulse slimming, LPF (low-pass filter) 48 for removing noise, HPF (high-pass filter) 49 for peak detection, data separator 50 for generating clock synchronized with data, encoding and decoding of recording code It is composed of an ENDEC (encoder, decoder) 51 for performing. When the LPF 48 is configured with a conventional filter system, the gain of the LPF 48 varies with the change in the cutoff frequency of the LPF 48.
The C control circuit 46 detects the output signal level of the LPF 48 and controls the AG so that the output signal amplitude of the LPF 48 becomes constant.
The gain of the C amplifier 45 is controlled. In this case, LPF4
If the input signal level of 8 fluctuates and the fluctuation of the input signal level becomes larger than the input dynamic range of the LPF 48, the problem that the output signal is distorted occurs.

[0014]

In the above-mentioned prior art, the gain of the filter also fluctuates as the cutoff frequency of the filter changes. Therefore, there is a problem that the variable range of the filter cutoff frequency is limited in order to suppress the variation of the filter gain within an allowable range.

Further, in the filter circuit, in order to suppress the gain variation, the circuit structure becomes complicated, which makes it difficult to reduce the voltage of the circuit.

Further, in the prior art, the filter Q value (Qua
There was also a problem that the lity factor) varied.

Furthermore, in the case of a high band active filter, as the cutoff frequency of the active filter changes,
There is also a problem that the Q value fluctuates.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a filter system capable of compensating for the variation of the filter gain due to the change of the cutoff frequency of the filter in a filter having a variable cutoff frequency and corresponding to the low voltage circuit system. It is to be realized.

Further, another object of the present invention is to eliminate the variation of the Q value due to the characteristic variation of the elements constituting the filter, and to change the Q of the active filter along with the variation of the cutoff frequency.
It is to suppress the fluctuation of the value of. This allows a wide band,
Realizes a highly accurate active filter.

[0020]

FIG. 1 is a block diagram of a filter system according to the present invention for achieving the above object.
Shown in.

As shown in FIG. 1, the present system includes a cutoff frequency variable filter 1 and a VGA (variable gain amplifier).
2, register 3, and D / A converter 4.

Other means described below are also conceivable.

As shown in FIG. 14, this system includes a microcomputer 100, a register 200, a synthesizer 300, and a D.
It is configured to have an AC 400, an active filter 500, and a Q control signal automatic generation circuit 600. Further, the Q control signal automatic generation circuit 600 includes a synthesizer 700, a DA
A C900, a low-pass filter 800, an active filter 1000, and an amplitude detection circuit 1100 are included.

[0024]

The operation of the present invention will be described with reference to FIG.

The cutoff frequency of the variable cutoff frequency filter 1 is controlled by the filter control signal 5 according to the set value of the cutoff frequency of the filter. Further, a means for generating a gain control signal 6 according to the filter cutoff frequency is used to generate the gain control signal 6, and the gain control signal 6 generates VG.
The gain of A (variable gain amplifier) 2 is controlled. This makes it possible to correct the gain variation due to the change in the filter cutoff frequency by the VGA (variable gain amplifier) 2 and keep the gain of the filter system constant regardless of the filter cutoff frequency.

Further, since the gain variation of the cutoff frequency variable filter 1 is corrected by the VGA (variable gain amplifier) 2, the variable range of the cutoff frequency can be widened and the circuit structure can be further simplified. Therefore, it becomes possible to support the low voltage system.

Next, the operation of the other means will be described with reference to FIG.
This will be described with reference to FIG.

The microcomputer 100 sets a digital value in the register 200 according to the transfer speed for writing data to the magnetic disk device, and the DAC 400
The f0 control signal 1200 is generated according to the set value in the register 200, and the cutoff frequencies of the active filters 500 and 1000 are controlled by the control signal.

The synthesizer 300 outputs an oscillation frequency clock according to the set value in the register 200.
The synthesizer 700 included in the Q control signal automatic generation circuit 600 divides the output clock of the synthesizer 300 and inputs the signal passed through the low-pass filter 800 to the active filter 1000.

Amplitude detection circuit 1100 receives the input signal and output signal of active filter 1000 and outputs Q control signal 1300. The Q value of the active filters 500 and 1000 is controlled by the Q control signal 1300.

A more detailed description will be given.

The amplitude detection circuit 1100 provided in the Q control signal automatic generation circuit 600 includes an active filter 100.
A Q control signal 1300 is output according to the amplitude difference between the input signal of 0 and the output signal, and the active filter 1 is output by the control signal.
Active filter 10 to control the Q value of 000.
The Q value of 00 does not depend on variations in element characteristics.

When the active filter 1000 and the active filter 500 are formed on the same chip, the characteristic variations of the active filter 1000 and the active filter 500 are about the same.

By controlling the Q value of the active filter 500 by the Q control signal 1300, the Q value of the active filter 500 does not depend on variations in element characteristics. Furthermore, it becomes possible to suppress the fluctuation of the Q value due to the change of the cutoff frequency.

[0035]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 12 is a system configuration diagram when the present invention is applied to a magnetic disk. The system of FIG. 12 is
A disk disk 36 for recording data, an R / W amplifier 37 for amplifying signals, a signal processing block 38 for performing signal processing, an HDC (hard disk controller) 39 for controlling data, and I for exchanging data.
/ F (interface) 40, HDC39, I / F4
CPU 41 for controlling 0, VCM (voice coil motor) 42, VCM control circuit 4 for controlling VCM 42
3 and a host 44 for processing data.

The signal processing block 38 includes an AGC (Automatic Gain Control) amplifier 45 for keeping the signal amplitude constant, an AGC control circuit 46 for controlling the AGC amplifier 45, an equalizer 47 for performing pulse slimming,
LP comprising a filter system according to the present invention
An F (low-pass filter) 48, an HPF (high-pass filter) 49 for peak detection, a data separator 50 that generates a clock synchronized with data, and an ENDEC (encoder, decoder) 51 that encodes and decodes a recording code are provided. Constitute.

FIG. 1 shows the outline of the present invention.
The circuit shown in FIG. 1 includes a cutoff frequency variable filter 1,
It has a VGA (variable gain amplifier) 2, a register 3, and a D / A converter 4.

The variable cutoff frequency filter 1 changes the filter cutoff frequency according to the filter control signal 5. The register 3 is set to a value according to the set value of the filter cutoff frequency, and the D / A converter 4
The gain control signal 6 corresponding to the set value of the register 3 is output. The VGA (variable gain amplifier) 2 changes the gain by the gain control signal 6. With such a system configuration, a VGA (variable gain amplifier) with respect to the gain variation by the cutoff frequency variable filter 1
However, since the gain variation of the filter is corrected, the gain of the filter system can be made constant.

Specifically, the control is performed as follows.
It is assumed that the cutoff frequency of the variable cutoff frequency filter 1 is set to “5 (MHZ)”, for example. At this time, it is assumed that the amplitude of the input signal to the cutoff frequency variable filter 1 becomes “½ times” and is output from the cutoff frequency variable filter 1. In this case, VGA
(Variable gain amplifier) To make the gain of 2 double,
A predetermined value is set in the register 3. Therefore, the amplitude of the output signal from the filter system will be constant.
That is, the gain control signal 6 for setting the gain of the VGA (variable gain amplifier) 2 is generated so as to compensate the attenuation of the input signal in the cutoff frequency variable filter 1 (the generation of the signal is set in the register 3). The digital value is converted from digital to analog by the DAC 4), and the amplitude of the output signal from the filter system becomes constant.

FIG. 2 shows a system configuration in which the gain of the VGA (variable gain amplifier) 2 is controlled by the filter control signal 5 in the filter system of FIG. In this method, a gain control signal is not particularly required, a register for generating the gain control signal and a D / A converter are unnecessary, and the circuit scale can be reduced.

That is, in the present configuration, for example, parameters for changing the characteristics (cutoff frequency and gain) of the filter and the VGA by the same control signal,
It is designed to change the current value at a predetermined location in the filter and VGA to give a desired cutoff frequency and gain.

FIG. 3 shows a VGA of the filter system of FIG.
(Variable gain amplifier) A control circuit 7 is additionally provided. A VGA (variable gain amplifier) control circuit 7 receives the input signal and the output signal of the cutoff frequency variable filter 1 as an input, and outputs a gain control signal 6 according to the difference in the amplitude level of the two signals. The gain of the VGA (variable gain amplifier) 2 is controlled by.

The gain control is performed, for example, when the amplitude of the input signal of the cutoff frequency variable filter 1 is equal to the amplitude of the output signal, the VGA (variable gain amplifier) control circuit 7
The gain signal 6 for increasing the gain of the VGA (variable gain amplifier) 2 to 1 is output. Further, when the amplitude of the output signal of the cutoff frequency variable filter 1 is “½ times” the amplitude of the input signal, the VGA (variable gain amplifier) control circuit 7 controls the gain of the VGA (variable gain amplifier) 2. The gain signal 6 for doubling is output.

In this way, VGA (variable gain amplifier)
The control circuit 7 generates a gain signal according to the attenuation of the input signal to the filter 1, and generates the gain control signal 6 so that the amplitude of the signal output from the filter system has a constant value.

In this system, the VGA (variable gain amplifier) control circuit 7 for generating the gain control signal 6 is provided so that the gain control signal 6 does not need to be externally supplied and the gain of the filter system is automatically adjusted. Can be kept constant.

FIG. 4 shows the input of the VGA (variable gain amplifier) control circuit 7 in the filter system of FIG.
Input signal of cutoff frequency variable filter 1 and VGA
The output signal of the (variable gain amplifier) 2 is used.
The VGA (variable gain amplifier) control circuit 7 receives the input signal of the cutoff frequency variable filter 1 and the output signal of the VGA (variable gain amplifier) 2 as input and controls the gain control signal 6 according to the difference between the amplitude levels of the two signals. Is output and VGA
By constructing a feedback loop that controls the gain of the (variable gain amplifier), the gain of the filter system can be stabilized.

That is, the VGA (variable gain amplifier) control circuit 7 sets the initial setting value of the gain of the VGA (variable gain amplifier) 2 to "a times", and, for example, the amplitude of the output signal of the VGA (variable gain amplifier) 2 is When the amplitude of the input signal of the cutoff frequency variable filter 1 becomes "1/2 times", the VGA (variable gain amplifier) control circuit 7 causes the VGA
(Variable gain amplifier) 2 has a function of generating a gain control signal 6 that makes the gain “2 × a times”, whereby the amplitude value output from the filter system becomes constant.

FIG. 5 is a system in which the system of FIG. 4 is applied to a signal processing circuit of a magnetic disk. The system shown in FIG. 5 includes an equalizer 8 that performs so-called pulse slimming, an LPF (low pass filter) 15 for removing noise, and an HPF (high pass filter) for peak detection.
9, a VGA (variable gain amplifier) 2 and 10, and a VGA (variable gain amplifier) control circuit 7.

VGA (variable gain amplifier) control circuit 7
Receives the input signal of the equalizer 8 and the output signal of the VGA (variable gain amplifier) 2 and outputs the gain control signal 6 according to the difference in the amplitude level of the two signals. (Amplifier) Controls the gain of 2 and 10. VGA (variable gain amplifier) control circuit 7
By monitoring the input signal of the equalizer 8, the gain of the signal processing filter system including the equalizer 8 can be stabilized.

FIG. 6 is a first-order LPF with a variable cutoff frequency.
The configuration example of the (low-pass filter) 15 is shown, and variable transconductance amplifiers 11 and 12 and capacitors 13 and 14 are shown.
Is configured. The filter cutoff frequency fc of this circuit is the variable transconductance amplifiers 11 and 12
Using the conductance Gm of and the capacitance value C of the capacitances 13 and 14,

[0052]

[Equation 2]

Can be expressed as

By controlling the conductance Gm of the variable transconductance amplifiers 11 and 12 with the filter control signal 5, the cutoff frequency of the cutoff frequency variable LPF 15 can be made variable.

FIG. 7 shows a cutoff frequency variable first-order HPF.
An example of the configuration of a (high-pass filter) 20 is shown, which includes a variable transconductance amplifier 17 and capacitors 18 and 19. Filter cutoff frequency f of this circuit
c is the conductance Gm of the variable transconductance amplifier 17 and the capacitance value C of the capacitors 18 and 19,

[0056]

[Equation 3]

It can be expressed as By the filter control signal 5, the conductance Gm of the variable transconductance amplifier 17
The cutoff frequency of the cutoff frequency variable HPF (high-pass filter) 20 can be made variable by controlling the.

FIG. 8 shows a circuit configuration of a VGA (variable gain amplifier), and this circuit has bipolar transistors 21 and 22, a current source 23, and resistors 24 and 25. The gain G of this circuit is obtained by using the current value I0 of the current source 23 and the resistance values RL of the resistors 24 and 25,

[0059]

[Equation 4]

It can be expressed as Here, re is the electron charge q, the Boltzmann constant k, and the temperature T, and

[0061]

[Equation 5]

It can be expressed as By controlling the current I0 of the current source 23, the gain G of the VGA (variable gain amplifier) can be controlled.

FIG. 9 shows a circuit configuration of the variable transconductance amplifier. This circuit is constructed by including bipolar transistors 26 to 31, current sources 32 to 34, and a resistor 35. The transconductance Gm of this circuit is
Current value I1 of current sources 32 and 33, current value I of current source 34
2, using the resistance value Re of the resistor 35,

[0064]

[Equation 6]

The current I of the current source 34 can be expressed as
2 or by controlling the current I1 of the current sources 32 and 33, the conductance Gm of the variable transconductance amplifier can be controlled.

FIG. 10 shows the cutoff frequency variable 1 of FIG.
In the next LPF (low pass filter) 15, the mutual conductance Gm1 of the variable mutual conductance amplifier 11 is
Is controlled by the gain control signal 6.

The filter gain A of this circuit is the transconductance Gm of the variable transconductance amplifier 11.
1. Using the mutual conductance Gm2 of the variable transconductance amplifier 12,

[0068]

[Equation 7]

It can be expressed as The filter cutoff frequency of this circuit is

[0070]

[Equation 8]

It can be expressed as By controlling the conductance Gm1 of the variable transconductance amplifier 11 with the gain control signal 6, it is possible to make the gain A of the cutoff frequency variable filter 15 variable without affecting the cutoff frequency of the filter. In this system, since the filter itself can have a variable gain amplifier function, it is not necessary to provide a VGA (variable gain amplifier) independently, and the circuit scale can be reduced.

FIG. 11 shows a high-order filter system constructed by connecting the filter system of FIG. 1 in multiple stages.
In this high-order filter system, since the filter gain is kept constant in each stage, it is not necessary to provide an amplifier in the next stage of the filter, and the output noise can be reduced.

Another embodiment of the present invention will be described below with reference to the drawings.

Before explaining other embodiments,
A conventional active filter will be briefly described with reference to FIG. Conventional active filters are described, for example, in the SSI32F8010 data sheet from Silicon Systems, Inc. FIG. 23 is a block diagram of a conventional active filter, which includes a microcomputer 100, a register 200, a DAC 400, and an active filter 500.

For example, the microcomputer 1 sets a digital value in the register 2 according to the transfer speed for writing data to the magnetic disk device.

The DAC 4 outputs the f0 control signal 12 according to the value set in the register 2. In addition, DAC
4 outputs the Q control signal 13 according to the value set in the register 2. The cut-off frequency of the active filter 5 is controlled by the f0 control signal 12, and the Q value of the active filter 5 is controlled by the Q control signal 13.

Now, FIG. 14 shows the configuration of another embodiment according to the present invention.

The circuit shown in FIG. 14 corresponds to the microcomputer 10
0, register 200, synthesizer 300, DAC 40
0, the active filter 500, and the Q control signal automatic generation circuit 600 are provided on the same LSI chip.
In addition, the Q control signal automatic generation circuit 6 includes a synthesizer 70.
0, DAC 900, low-pass filter 800, active filter 1000, and amplitude detection circuit 1100.

The microcomputer 100 is means for setting a digital value in the register 200 according to the transfer speed of data sent from the magnetic disk device, for example. The microcomputer 1 is realized by, for example, a configuration including at least one of a CPU, a ROM, and a RAM. Register 2
Are realized by various CMOSs, for example.

The digital value set in the register 200 may be processed by the microcomputer 100 so that it is determined in a predetermined relationship corresponding to the data transfer rate, for example. Here, the predetermined relationship is, for example,
A proportional relationship or the like is preferable.

The DAC 400 is means for generating the f0 control signal 1200 according to the set value of the register 2, and f0
0 control signal 1200 causes active filter 50
A cutoff frequency of 0, 1000 is controlled.

The active filters 500, 100
0 may be configured to have the variable transconductance amplifier and the capacitive element as described above. In addition, DAC4
00 is realized by, for example, a digital / analog converter configured by various CMOSs and the like.

The synthesizer 300 is a write (or read) clock generating means, and the cutoff frequency of the active filter and the output clock frequency of the synthesizer have a proportional relationship. The synthesizer 300 is realized by electronic devices such as various CMOSs, for example.

The synthesizer 300 is configured to output an oscillation frequency clock according to the set value of the register 200. For example, it is conceivable that a signal having an oscillation frequency proportional to the set value of the register 2 is output, and this is because a logic circuit including electronic devices such as various CMOSs is used in a synthesizer. It is realized by providing 300.

The synthesizer 700 provided in the Q control signal automatic generation circuit 6 divides the output clock of the synthesizer 300 and outputs a clock signal having the same frequency f0 as the cutoff frequency of the active filter 1000.

The low-pass filter 800 makes the cutoff frequency variable according to the oscillation frequency of the synthesizer 300, cuts the harmonic components of the output signal of the synthesizer 700, and outputs a sine wave. The low-pass filter 800 is realized by, for example, a programmable filter whose cutoff frequency can be arbitrarily set. Specifically, in this embodiment, the DAC 900 digital-analog converts the digital value set by the register 200 to generate a signal for setting the cutoff frequency.

The active filter 1000 receives the sine wave which is the output signal from the low pass filter 800 as an input signal.

The amplitude of the input signal of the active filter 1000 is Vin, the amplitude of the output signal of the active filter 1000 is Vout, the set Q value of the active filter 1000 is Q1, and the actual Q value of the active filter 1000 is Q2.

The Q value is a parameter representing the characteristics of the filter, and the phase difference of 90% in the filter phase characteristics.
Indicates the slope of the ° point. If the Q value varies depending on the frequency, the delay time of the filter (ideally, the delay time is ideally constant regardless of the frequency) varies depending on the frequency, and the output waveform is distorted.

Therefore, in the filter system,
Therefore, it is necessary to control the Q value to be constant at a predetermined value. In general, the Q value is obtained by measuring the “gain” of the filter at the cutoff frequency, and the Q value that can be taken is set in advance in the specifications for each system.

The amplitude detection circuit 11 receives the input signal and the output signal of the active filter 1000 as input, and calculates the difference between the amplitude Vin of the input signal of the active filter 1000 and the amplitude bout of the output signal of the active filter 10 by b. , Q control signal 1300 is output,
For example, it can be realized by a configuration having electronic devices such as various CMOSs. The values of a and b are

[0092]

[Equation 9]

It is set in advance so that When the control amount of the Q control signal 1300 is q (q is finally controlled to be “0”),

[0094]

[Equation 10]

It can be expressed as By the way, if the transfer function of the active filter 1000 is A (s), A (s) is

[0096]

[Equation 11]

It can be expressed as

The same frequency f as the cutoff frequency of the active filter 1000 is input to the input of the active filter 1000.
Since a signal having 0 is input, the control amount q of the Q control signal 1300 is "Vout = Q2 ×" at the cutoff frequency according to the definition of the Q value described above and Q2 from the Q value obtained by the experiment.
In consideration of becoming "Vin",

[0099]

[Equation 12]

It can be expressed as By controlling the Q value of the active filter 1000 by the Q control signal 1300, that is, by setting the control amount q to “0”, the Q value of the active filter 1000 is controlled to be Q1.
It is determined by the accuracy of the ratio of a and b regardless of variations in element characteristics and variations in cutoff frequency.

Since the active filter 1000 is formed on the same chip as the active filter 500, the variations in electrical characteristics are almost the same, and by controlling the Q value of the active filter 500 by the Q control signal 1300, The Q value is stably controlled regardless of variations in element characteristics and variations in cutoff frequency.

FIG. 15 shows an embodiment of a filter system in which the Q control signal automatic generation circuit 600 in the filter control block diagram shown in FIG. 14 is replaced with an f0, Q control signal automatic generation circuit 1400. .

F0, Q control signal automatic generation circuit 1400
The Q control signal automatic generation circuit 600 is additionally provided with a phase detection circuit 1500, a reference Q control signal generation circuit 1600, and a switch 1700. Each associated circuit is realized by an electronic device such as a CMOS.

The phase detection circuit 1500 provided in the f0, Q control signal automatic generation circuit 1400 uses the input signal and the output signal of the active filter 1000 as input signals, and outputs the integrated value of the product of the two input signals. . Let φ be the phase difference between the input signal and output signal of the active filter,
The input signal of the active filter is sin (t) and the output signal is As
If in (t + φ) and the output of the phase detection circuit 1500 are Ψ,
Ψ is

[0105]

[Equation 13]

It is expressed as follows. Here, A is a constant and n is an integer. Solving equation 13,

[0107]

[Equation 14]

It becomes:

By using the output Ψ of the phase detection circuit 1500 as the f0 control signal and controlling the cutoff frequency of the active filter 1000 with the f0 control signal 1200, Ψ is controlled so that it becomes 0 (the output from the active filter 1000). Is input to the phase difference detection circuit 1500, and the f0 control signal output from the phase difference detection circuit 1500 is input to the active filter 1000). As a result, the active filter 1000
The phase difference φ between the input signal and the output signal of is 90 °.

That is, for an input signal of frequency f0,
Since the output signal of the active filter 1000 is deviated by 90 °, the cutoff frequency of the active filter 500 is controlled to be the same f0 as the input signal frequency.

By controlling the cutoff frequency of the active filter 1000 with the f0 control signal 1200, the cutoff frequency of the active filter 1000 is determined by the accuracy of the input signal frequency, regardless of variations in element characteristics.
By controlling the cutoff frequency of the active filter 500 with the f0 control signal 1200, the active filter 50
The cutoff frequency of 0 is stably controlled regardless of variations in element characteristics.

For a predetermined period until the f0 control signal 1200 stabilizes (in order to find two stable points of f0 and Q value, one stable point is found, and then the other stable point is found), and Q control is performed. As for the signal 1300, the reference Q control signal 1600 is selected by the switch 1700 so that the reference Q signal having a constant value is output.

After the f0 control signal 1200 stabilizes, the switch 1700 selects the output of the amplitude detection circuit 1100 and outputs the output of the amplitude detection circuit 1100 to the Q control signal 1300.
As a result, the Q values of the active filter 1000 and the active filter 500 are controlled. FIG. 3 is a block diagram of an embodiment in which the active filter shown in FIG. 1 is applied to an active filter configured by cascade connection in multiple stages.

Instead of the active filter 500 shown in FIG. 1, active filters 1800 to 1900, first-order active filter 2000, amplifiers 2100 to 25
00 is attached. Active filter 18
00 to 1900 are configured to include, for example, a transconductance amplifier and a capacitive element. Also, the amplifier 2100
˜2500 are means for giving a predetermined control amount to the active filter connected to the amplifier by utilizing its frequency characteristic.

The cutoff frequencies of the active filters 1800 to 2000 are the amplifiers 2300, 2400, and 25, respectively.
Controlled by the f0 control signal 1200 via 00. The Q values of the active filters 1800 and 1900 are
Q control signal 1300 via amplifier 2100, 2200
Controlled by. That is, the f0 control signal 120
0, Q control signal 1300, amplifier 2100-2500
To the active filters 1800 to 2000 and control the cutoff frequencies and Q values of the active filters 1800 to 2000, thereby controlling the cutoff frequencies and Q values of the multistage active filters having different cutoff frequencies and Q values. can do.

FIG. 17 is a block diagram showing an embodiment in which the active filter shown in FIG. 15 is applied to an active filter constituted by cascade connection in multiple stages.

Active filters 1800 to 1900,
The cutoff frequency of the first-order active filter 2000 is the f0 control signal 1200 via the amplifiers 2300 to 2500.
Controlled by. Active filters 1800-190
0 is configured to include, for example, a transconductance amplifier and a capacitive element. Also in the present embodiment, the amplifiers 2100 to 2500 are means for giving a predetermined control amount to the active filter connected to the amplifier by utilizing the frequency characteristic thereof.

The Q values of the active filters 1800 and 1900 are controlled by the Q control signal 1300 via the amplifiers 2100 and 2200.

That is, the f0 control signal 1200 and the Q control signal 1300 are passed through the amplifiers 2100 to 2500 and the cutoff frequencies of the active filters 1800 to 2000, Q.
By controlling the value, it is possible to control the cutoff frequency and the Q value in the active filter having a multistage structure having different cutoff frequencies and Q values.

FIG. 18 shows the amplitude detection circuit 1 shown in FIG.
The structural example of 100 is shown.

The circuit shown in FIG. 18 is a differential amplifier 260.
0, peak hold circuits 2700, 2800, amplifier 2
It is configured to have 900, 3000. Each component is
It is configured to have electronic devices such as transistors, CMOSs, operational amplifiers, and resistors.

The peak hold circuit 2700 is means for outputting the signal obtained by multiplying the input signal of the active filter 1000 (see FIG. 1) by the amplifier 2900.

Similarly, the peak hold circuit 2800 is
The output signal of the active filter 1000 is supplied to the amplifier 30.
It is a means for outputting a signal multiplied by b with 00.

The differential amplifier 2600 outputs the difference between the amplitudes of the output signals of the peak hold circuits 2700 and 2800. At this time, change the Q value of the active filter 1000 to Q.
When it is set to 1, it is set as in the above-described Expression 9.

FIG. 19 shows the phase detection circuit 1 shown in FIG.
The structural example of 500 is shown.

The phase detection circuit 1500 has a loop filter 3100 and a multiplier 3200. The multiplier 3200 outputs a product signal of the input signal and the output signal of the active filter 1000. Loop filter 310
0 is a means for integrating the output of the multiplier 3200,
Output the integrated value.

FIG. 20 shows the active filter 5 of FIG.
A configuration example of 00 and 1000 is shown.

The active filter shown in FIG. 20 is a so-called second-order low-pass filter, and has transconductance amplifiers 3300, 3400, 3500, 3600, and capacitors 3700, 3800, 3900, 4000.

Mutual Conductance Amplifiers 3300 and 34
The transconductances of 00, 3500 and 3600 are gm1, gm2, gm3, gm4 and capacitance 3 respectively.
Let C be the capacitance value of 700, 3800, 3900, and 4000.

The cutoff frequency f0 of the active filter is
Using the calculation of the ratio of input / output voltage, that is, the transfer function (in this calculation, if a simple formula is made assuming the current flowing in the capacitor, the calculation will be easier),

[0131]

[Equation 15]

It is expressed as follows. The Q value of the active filter is

[0133]

[Equation 16]

It is expressed as follows.

Therefore, gm is set by the f0 control signal 1200.
By controlling 2 and gm4, the cutoff frequency f0 of the active filter can be controlled. In addition, by controlling gm3 with the Q control signal 1300, the Q value of the active filter can be controlled and does not affect the cutoff frequency of the active filter.

FIG. 21 shows a configuration example of the transconductance amplifiers 3300, 3400, 3500, 3600 shown in FIG. FIG. 21 shows npn transistors 4100 and 42.
00, 4300, 4400, 4500, 4600, resistor 4700, current sources 4800, 4900, 5000, 51
00 and 5200.

The resistance value of the resistor 4700 is R, and the current source 480 is
0, 4900 current value is i1, current source 5000, 510
The current value of 0 is i2 and the current value of the current source 5200 is “2 × i”.
2 ". At this time, the mutual conductance gm of the mutual conductance amplifier is

[0138]

[Equation 17]

It is expressed as follows. Therefore, the current source 5
The mutual conductance gm can be controlled by controlling the current values of 000, 5100, and 5200.

FIG. 22 shows a system configuration diagram when the present invention is applied to a magnetic disk device. The system shown in FIG. 22 is a disk disk 530 for recording data.
0, R / W amplifier 5400 that amplifies read and write signals, signal processing block 550 that performs signal processing
0, HDC (hard disk controller) 5600 for controlling data, I / F (interface) 5700 for exchanging data, HDC 56
00, CPU 5800 for controlling I / F 5700, V
CM (Voice Coil Motor) 5900, VCM5900
A VCM control circuit 6000 for controlling the above and a host 6400 for processing data are configured. Further, the signal processing block 5500 includes an AGC (automatic gain control) amplifier 61 that makes the amplitude of a given signal constant, an active filter 500 that is a control target of the present invention, a data separator 6200 that generates a clock synchronized with data, It is configured to have an ENDEC (encoder, decoder) 6300 that performs encoding and decoding of recording codes.

The signal obtained by reading the data stored in 5300 is input to 500 with a constant amplitude by 6100. The frequency of the signal input to 500 increases toward the outside of 5300. Therefore, in order to realize the optimum frequency characteristic, the cutoff frequency and Q value of the active filter 500 must be set to predetermined values according to the input signal. At this time, as described above, the fluctuation of the output level and Q value from 500 is eliminated, and stable data reading (of course, writing is also possible) can be performed.

FIG. 24 is a circuit diagram of the circuit shown in FIG.
The internal configuration of the Q control signal automatic generation circuit 6 is changed.

FIG. 24 shows the synthesizer 7 of FIG.
00 is replaced with a frequency divider 6800, and a new DAC6
500, ADC (Analog / Digital Converter) 660
0 and a RAM 6700 are attached.

The synthesizer 300 is oscillated at an integer multiple of the cutoff frequency of the active filter 1000, and the frequency divider 6800 divides the output signal of the synthesizer 300 to generate a signal having the same frequency as the cutoff frequency of the active filter 1000. It is configured to output.

The ADC 6600 has an amplitude detection circuit 1100.
Is used as an input signal and the output value of the amplitude detection circuit 1100 is digitized and stored in the RAM 6700.

The DAC 6500 converts the value stored in the RAM 6700 into an analog value and outputs the Q control signal 13
00 is output.

As described above, with the circuit configuration as shown in FIG. 24, even if the frequency of the output signal of the synthesizer 300 is not an integral multiple of the cutoff frequency of the active filter 1000, the output of the synthesizer 300 is temporarily output. The signal frequency can be varied to generate the Q control signal 1300.

[0148]

According to the present invention, the filter system has a structure in which a VGA (variable gain amplifier) is attached to a cutoff frequency variable filter, and the gain of the VGA (variable gain amplifier) is changed according to the cutoff frequency. By doing so, it is possible to correct the gain variation due to the change of the cutoff frequency of the filter by the VGA (variable gain amplifier) and make the gain of the filter system constant.

Since the gain is stable even when the filter cutoff frequency is changed, the variable range of the filter cutoff frequency can be widened.

Further, the circuit structure is simplified and the low voltage system can be supported.

Furthermore, due to variations in element characteristics,
It is possible to eliminate the fluctuation of the Q value and suppress the fluctuation of the Q value due to the change of the cutoff frequency of the active filter.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a filter system according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a filter system according to an embodiment of the present invention.

FIG. 3 is a configuration diagram of a filter system according to an embodiment of the present invention.

FIG. 4 is a configuration diagram of a filter system according to an embodiment of the present invention.

FIG. 5 is a configuration diagram of a filter system according to an embodiment of the present invention.

FIG. 6 is a circuit configuration diagram of a cutoff frequency variable first-order LPF.

FIG. 7 is a circuit configuration diagram of a cutoff frequency variable first-order HPF.

FIG. 8 is a circuit configuration diagram of a VGA (variable gain amplifier).

FIG. 9 is a circuit configuration diagram of a variable transconductance amplifier.

FIG. 10 is a circuit configuration diagram of a gain / cutoff frequency variable first-order LPF.

FIG. 11 is a configuration diagram of a high-order filter system according to an embodiment of the present invention.

FIG. 12 is a system configuration diagram in which the present invention is applied to a magnetic disk.

FIG. 13 is a configuration diagram of a conventional filter system.

FIG. 14 is a configuration diagram of an embodiment of the present invention.

FIG. 15 is a configuration diagram of an embodiment of the present invention.

FIG. 16 is a configuration diagram of an embodiment of the present invention.

FIG. 17 is a configuration diagram of an embodiment of the present invention.

FIG. 18 is a configuration diagram of an amplitude detection circuit.

FIG. 19 is a configuration diagram of a phase detection circuit.

FIG. 20 is a configuration diagram of an active filter.

FIG. 21 is a configuration diagram of a transconductance amplifier.

FIG. 22 is a configuration diagram of a system according to the present invention.

FIG. 23 is a configuration diagram of a conventional active filter.

FIG. 24 is a configuration diagram of an embodiment of the present invention.

[Explanation of symbols]

1 ... Cutoff frequency variable filter, 2 ... VGA (variable gain amplifier), 3 ... Register, 4 ... D / A converter, 5 ... Filter control signal, 6 ... Gain control signal, 7 ...
VGA (variable gain amplifier) control circuit, 8 ... equalizer, 9 ... HPF (high-pass filter), 10 ... VGA
(Variable gain amplifier), 11, 12 ... Variable transconductance amplifier, 13, 14 ... Capacitance, 15 ... LPF (low-pass filter), 17 ... Variable transconductance amplifier, 18, 19 ... Capacitance, 20 ... HPF, 21, 22 ... Bipolar transistor, 23 ... Current source, 24, 25 ... Resistor, 26-31 ... Bipolar transistor, 32-34
… Current source, 35… Resistor, 36… Disc disk, 37… R
/ W (Read / Write) amplifier, 38 ... Signal processing block, 39 ... HDC (hard disk controller), 40 ... I / F (interface), 41 ... CP
U, 42 ... VCM (voice coil motor), 43 ... VC
M control circuit, 44 ... Host, 45 ... AGC (automatic gain control) amplifier, 46 ... AGC control circuit, 47 ... Equalizer, 48 ... LPF, 49 ... HPF,
50 ... Data separator, 51 ... ENDEC (encoder, decoder), 52 ... Gain fixed amplifier, 53 ... Cutoff frequency variable filter, 54 ... VGA (variable gain amplifier), 55 ... Register, 56 ... D / A converter,
100 ... Microcomputer 200 ... Register, 300 ... Synthesizer, 400 ... DAC, 500 ... Active filter,
600 ... Q control signal automatic generation circuit, 700 ... Synthesizer, 800 ... Low-pass filter, 900 ... DAC, 10
00 ... active filter, 1100 ... amplitude detection circuit,
1200 ... f0 control signal, 1300 ... Q control signal, 14
00 ... f0, Q control signal automatic generation circuit, 1500 ... Phase detection circuit, 1600 ... Reference Q control signal, 1700 ... Switch

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Kenichi Hase Inventor Kenichi Hase, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa, Ltd. Hitachi, Ltd. Microelectronics Equipment Development Laboratory (72) Inventor Ken Urakami Water, Kodaira, Tokyo Honcho 5-chome 20-1 Incorporated company Hitachi Ltd. semiconductor design development center (72) Inventor Koichi Awano 292 Yoshida-cho, Totsuka-ku, Yokohama-shi Kanagawa Ltd. Hitachi Ltd. Microelectronics Equipment Development Laboratory

Claims (14)

[Claims] 1. A programmable filter capable of arbitrarily setting a filter cutoff frequency, a means for generating a gain control signal corresponding to the filter cutoff frequency, and a VGA (a gain which can be arbitrarily set by the gain control signal). A variable gain amplifier), wherein the gain of the VGA is controlled by the gain control signal to make the gain of the filter system constant. 2. A filter system according to claim 1, wherein a VGA is provided by a filter cutoff frequency control signal.
A filter system characterized by controlling the gain of a (variable gain amplifier). 3. A filter system according to claim 1, further comprising means for automatically generating a gain control signal, the gain of the filter system being kept constant.
A filter system having A (variable gain amplifier) and means for generating a gain control signal. 4. A filter system with a built-in equalizer, wherein the filter system according to claim 3 is provided with an equalizer, wherein the gain of the filter system with a built-in equalizer is constant. 5. A one-chip LSI including the filter system according to claim 3 or 4 and integrated on one chip. 6. A magnetic disk drive using the filter system according to claim 3 or 4. 7. An oscillating means for generating a signal having a specific frequency according to a given signal, an active filter for arbitrarily setting a filter cutoff frequency and a filter Q value (Quality Factor), and the oscillating means. Q control signal automatic generation means for generating a Q control signal for controlling the Q value of the active filter in accordance with the frequency of the output signal of the active filter. A filter system, wherein the Q value is controlled to be a target value given in advance. 8. An oscillating means for generating a signal having a specific frequency in accordance with a given signal, an active filter for arbitrarily setting a filter cutoff frequency and a filter Q value (Quality Factor), and the oscillating means. Q / f0 control signal automatic generation means for generating a Q control signal for controlling the Q value of the active filter and an f0 control signal for controlling the cutoff frequency of the active filter according to the frequency of the output signal of A filter system, wherein the Q value and the cutoff frequency of the active filter are controlled so as to reach a target value given in advance, according to the frequency of the signal output from the oscillating means. 9. The apparatus according to claim 7, further comprising an amplifying means, wherein the Q control signal output from the Q control signal automatic generating means is input to the active filter via the amplifying means. Filter system. 10. The Q control signal and the f0 control signal output from the Q.f0 control signal automatic generation means are further input to the active filter through the amplification means according to claim 8. A filter system characterized by: 11. A semiconductor circuit in which the filter system according to claim 7 or 8 is integrated and formed on the same chip. 12. A magnetic disk device comprising the filter system according to claim 7 or 8 therein, and filtering a data read signal from a magnetic head. 13. An oscillating means for generating a signal of a specific frequency according to a given signal, and a first active filter capable of arbitrarily setting a filter cutoff frequency and a filter Q value (Quality Factor). Q control signal automatic generation means for generating a Q control signal for controlling the Q value of the active filter according to the frequency of the output signal of the oscillating means, wherein the Q control signal automatic generation means is a filter cutoff frequency. And a second active filter capable of arbitrarily setting the filter Q value, and an amplitude detecting means, which is a sine wave signal generated from the signal output from the oscillating means. The input signal Vin having the same frequency as the cut-off frequency of the first active filter and input to the second active filter, and the second activator. The output signal Vout of the filter as an input signal, a multiple of Vin (a is a real number) signal, and, Vout
B times (b is a real number) difference signal (a × Vin−
b * Vout) is generated and Q is determined from Q1 which is a target value of a Q value given in advance and Vin and Vout.
If the value is Q2, then the controlled variable q = (Q1-Q2) × b × Vin (where Q1
= A / b), a loop for feeding back the differential signal, which is the output signal of the amplitude detecting means, to the Q value setting terminal of the second active filter is set so that q = 0. A filter system, wherein a value is set to a target value Q1 given in advance. 14. The method according to claim 13, further comprising phase detection means, wherein the phase detection means uses Vin and Vout as input signals, and an integrated value of a product of Vin and Vout is Ψ, and Ψ = 0. So that the output signal of the phase detecting means is fed back to the cutoff frequency setting terminal of the second active filter, and the cutoff frequency of the first active filter is set to a predetermined target value. A filter system characterized by the above.