JP2012129643A - Clock frequency control circuit and clock frequency control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To implement a PLL circuit for generating a signal with a slight frequency change while relatively reducing a signal frequency division rate and suppressing an increase in phase noise.SOLUTION: A clock frequency control circuit includes: a voltage-controlled oscillator having an output frequency varying with voltage input from a correlation circuit for controlling the output frequency by controlling a predetermined voltage; a first frequency division circuit for dividing the output of the voltage-controlled oscillator; a second frequency division circuit for dividing an externally input reference frequency; a phase comparator for outputting a pulse depending on the phases of the outputs of the first frequency division circuit and second frequency division circuit; and a low pass filter for extracting low frequency components from the output of the phase comparator for input to the voltage-controlled oscillator.

Description

  The present invention relates to a clock frequency control circuit and a clock frequency control method, and more particularly, to a clock frequency control circuit and a clock frequency control method for adjusting a reference frequency slightly shifted in a PLL (Phase Locked Loop) circuit.

  As shown in FIG. 17, the conventional PLL circuit includes an M frequency divider 1, a phase comparison circuit 2, a low-pass filter 3, a voltage controlled oscillator 4, and a programmable counter 5.

In the phase comparison circuit 2 of the PLL circuit shown in the figure, the signal of the reference frequency fR divided by M and the output frequency f0 of the voltage controlled oscillator 4 divided by N are phase-compared and smoothed by the low-pass filter 3 After that, it returns to the voltage controlled oscillator 4. The relationship between the reference frequency fR when the PLL is in phase synchronization and the output frequency f0 of the PLL is
f ₀ = N / M · f _R (1)
(For example, refer to Patent Document 1). In the prior art, if it is attempted to generate a frequency shifted by 1 Hz when fR = 10 GHz (10 to the 10th power Hz), for example, N = 10 to the 10th power and M = 10 to the 10th power + 1. In addition, a frequency dividing circuit having a large frequency dividing ratio is required. Furthermore, since the comparison frequency is low, there is a problem that phase noise increases and phase stability decreases (for example, see Non-Patent Document 1). The prior art document shows a configuration in which the comparison frequency is multiplied and phase comparison is performed at a high frequency. However, it is necessary to divide the output of the voltage controlled oscillator once and then multiply it, and to increase the reference frequency. There was a problem that the circuit scale and power consumption increased.

Japanese Patent Laid-Open No. 4-196620 (FIG. 3)

T. Ohira et al: "Dual-Chip GaAs Monolithic Integration Ku-Band Phase-Locked -Loop Microwave Synthesizer," IEEE Trans, Microwave Theory & Tech., Vol. 39, no. 9, pp.1204-1209, Sept, 1990. (Fig. 12 and its explanation).

  As described above, in order to finely control the frequency in the PLL circuit, it is necessary to make the frequency division ratio fine, and there is a problem that the circuit scale and power consumption increase. Furthermore, there is a problem that the phase noise increases as the frequency for dividing and phase comparison is lowered.

  The present invention has been made in view of the above points, and a clock frequency capable of generating a signal with a slight frequency change while suppressing the increase in phase noise with a relatively small signal division ratio. It is an object to provide a control circuit and a clock frequency control method.

In order to solve the above problems, the present invention is a frequency control circuit that adjusts a reference frequency by slightly shifting,
A voltage-controlled oscillator whose output frequency changes according to the input voltage;
A first frequency divider that divides the output of the voltage controlled oscillator;
A second frequency divider that divides the reference frequency input from the outside;
A phase comparator that outputs a pulse corresponding to the phase of the output of the first frequency divider circuit and the second frequency divider circuit;
A low-pass filter that extracts a low-frequency component from the output of the phase comparator and inputs it to the voltage control generator;
Correlation means for controlling an output frequency by adding or subtracting a predetermined voltage to a signal input to the voltage controlled oscillator.

  As described above, according to the present invention, a small frequency change can be generated with a small frequency division ratio, so that the circuit scale and power consumption can be reduced. Further, since the frequency division ratio can be made relatively small, an increase in phase noise can be suppressed to some extent.

It is a block diagram of the frequency control PLL circuit in the 1st Embodiment of this invention. FIG. 6 is a diagram (No. 1) for explaining the operation of the correlation circuit in the first embodiment of the invention; It is FIG. (1) for demonstrating the control voltage to the voltage controlled oscillator in the 1st Embodiment of this invention. FIG. 6 is a diagram (No. 2) for explaining the operation of the correlation circuit in the first embodiment of the present invention; FIG. 6 is a diagram (No. 2) for explaining the control voltage to the voltage controlled oscillator according to the first embodiment of the invention. It is FIG. (1) for demonstrating the example of the frequency control in the 1st Embodiment of this invention. It is FIG. (2) for demonstrating the example of the frequency control in the 1st Embodiment of this invention. It is FIG. (3) for demonstrating the example of the frequency control in the 1st Embodiment of this invention. It is FIG. (4) for demonstrating the example of the frequency control in the 1st Embodiment of this invention. It is FIG. (1) for demonstrating operation | movement of the correlation circuit in the 2nd Embodiment of this invention. It is FIG. (2) for demonstrating operation | movement of the correlation circuit in the 2nd Embodiment of this invention. It is a figure which shows control of the change of the frequency in the 3rd Embodiment of this invention. It is a block diagram of the frequency control PLL circuit in the 4th Embodiment of this invention. It is a block diagram of the low-pass filter in the 5th Embodiment of this invention. It is a calculation result of the frequency characteristic of the low-pass filter in the 5th Embodiment of this invention. It is a time characteristic of a frequency change at the time of combining control of the time constant of the low-pass filter in a 5th embodiment with the present invention. It is a block diagram of a conventional PLL circuit.

  Embodiments of the present invention will be described below with reference to the drawings.

[First embodiment]
FIG. 1 shows a configuration of a frequency control PLL circuit according to the first embodiment of the present invention.

  As shown in the figure, the frequency control PLL circuit in this embodiment includes a programmable counter (M frequency divider) 10, a phase comparison circuit 20, a low-pass filter 30, a voltage control oscillator 40, a correlation circuit 50, a programmable circuit (N Frequency divider) 60.

  As shown in the figure, the reference frequency fR signal is branched, one being sent to the programmable counter (M frequency divider) 10 and the other being sent to the correlation circuit 50. The output of the M frequency divider 10 is input to the phase comparator 20. On the other hand, after the output of the voltage controlled oscillator 40 is branched and input to a programmable counter (N divider) 60, the correlation circuit 50 performs correlation processing between the reference frequency signal and the N divider output signal, Input to the phase comparator 20. In the phase comparator 20, the phase comparison is performed between the output of the M frequency divider 10 and the output of the correlation circuit 50, and the output signal is smoothed by the low-pass filter 30 and then input to the voltage controlled oscillator 40. .

  In this circuit, the frequency shift amount with respect to the reference frequency fR is determined by the values of M and N and the operation of the output of the correlation circuit 50.

  The operation of the correlation circuit 50 has two operation modes depending on whether the control voltage for the voltage controlled oscillator is raised or lowered. The determination of which mode to operate depends on the input voltage characteristics of the output frequency of the voltage-controlled oscillator 40. Here, the description will be made assuming that the output frequency increases as the input voltage increases. The operation of the correlation circuit when the control voltage is increased (output frequency is increased) will be described with reference to FIG. A discrete pulse signal is generated based on the reference frequency signal input to the correlation circuit 50. The discrete pulse signal is a pulse in which “1” of one pulse is left every N clocks and other “1” portions are made “0”. The interval at which “1” is left depends on the frequency amount to be shifted, but details will be described later. A correlation signal is generated between the generated discrete pulse signal and the output of the programmable counter (N frequency divider) 60 which is the other input signal. Specifically, the correlation here is a logical sum (OR) of the "0" code portion of the output of the programmable counter (N frequency divider) 60 and the discrete pulse signal. As a result of the correlation processing, a voltage corresponding to “1” of the discrete pulse signal is added to the output signal of the programmable counter (N frequency divider) 60.

  Next, the process until the output of the correlation circuit 50 is fed back to the voltage controlled oscillator 40 will be described with reference to FIG. The signal after the correlation processing is input to the phase comparator 20 (for example, an EX-OR circuit). Since pulses are added in the correlation circuit 50, an output signal corresponding to the added pulse is also output from the phase comparator 20. The voltage increases. The output of the phase comparator 20 is suppressed to a DC component by suppressing the high frequency component by the low-pass filter 30 in the next stage, but the DC component (corresponding to Δv in FIG. 3) for the added pulse remains as it is. The voltage applied to the voltage controlled oscillator 40 increases, thus increasing the output frequency.

  Next, the operation of the correlation circuit when lowering the control voltage (lowering the output frequency) will be described with reference to FIG. In the operation mode in which the control voltage is lowered, discrete pulses in which “1” and “0” are inverted as compared with the case where the control voltage is raised are generated. Further, the correlation processing in this mode generates a negative logical sum (NOR) of the “1” sign portion of the output of the programmable counter (N frequency divider) 60 and the discrete pulse signal. As a result of the correlation processing, a voltage corresponding to “0” of the discrete pulse signal is subtracted from the output signal of the programmable counter (N frequency divider) 60.

  Next, the process until the output of the correlation circuit 50 is fed back to the voltage controlled oscillator 40 will be described with reference to FIG. The signal after the correlation processing is input to the phase comparator (for example, EX-OR circuit) 20, but since the pulse is subtracted in the correlation circuit 50, the output of the phase comparator 20 is also an output signal corresponding to the subtracted pulse. The voltage decreases. The output of the phase comparator 20 is suppressed by a low-pass filter of the next stage and 30 high frequency components are suppressed and smoothed to a direct current component. However, since the direct current component for the subtracted pulse is reduced, The output frequency is lowered.

  A numerical example of frequency control will be described with reference to FIG. FIG. 6 shows an example of increasing the frequency. Reference frequency fR is 9.95328 GHz, frequency division ratio N = M = 16, pulse voltage “0” level is 0 (V), “1” level is 3.3 (V), conversion gain of voltage controlled oscillator kv = 5000 rad / s / V. As for the discrete pulse, a 1-bit “1” pulse is generated every 16 clocks. Since the time width per clock of the reference frequency is about 0.1 ns, the time width of 1/16 divided clock is 0.1 × 16 = 1.6 ns, and the pulse width of “1” bit of discrete pulse is 0.1 / 2 = 0.05 ns It becomes. The DC component of 3.3V × 0.05ns / 1.6ns = 0.103V increases due to the addition of discrete pulses. If the increase is estimated to increase the frequency, ΔV × kv × 2π = 0.103 × 5000 × 2π = about 3200 Hz can be increased.

  An example of reducing the frequency will be described with reference to FIG. Compared with the example of FIG. 6, the DC component of the output of the correlation circuit 50 decreases by 0.103 V, so that the output frequency of the voltage controlled oscillator can be reduced by Δv × kv × 2π = 0.103 × 5000 × 2π = about 3200 Hz. .

  Further, when creating a correlation pulse, only the DC voltage component corresponding to the frequency to be increased (or decreased) needs to be reflected in the correlation signal. Therefore, when the frequency is increased as shown in FIGS. It is sufficient that at least a part of “0” of the N-divided clock signal and at least a part of “1” of the reference frequency signal are correlated (OR). The correlation (NOR) of at least a part of “1” and at least a part of “0” of the reference frequency signal may be taken.

  In order to change the frequency by 1 Hz, Δv = 1 Hz / 5000 / 2π = 0.000032 (V), and the division ratio N is 3.3 × 0.05 / 0.1 / 0.000032 = 51563, which is obtained by dividing 9.95328 GHz by 51563, A discrete pulse can be generated by making a 1-bit "1" pulse (pulse width 0.05 ns) every 51563 clocks (frequency division ratio M is 51563). Compared with having to divide by 10 to produce a frequency change of 1 Hz in the conventional configuration, the number of divisions can be greatly reduced, so that the circuit scale can be reduced and phase noise can be reduced. The increase of can also be suppressed relatively.

[Second Embodiment]
The configuration of the PLL circuit in this embodiment is the same as that in FIG.

With reference to FIGS. 10 and 11, a second embodiment according to the present invention will be described. In this example, the circuit block configuration is the same as that of the first embodiment, but the signal processing in the correlation circuit is different. Specifically, in the first embodiment, one pulse is left every N clocks when creating a discrete pulse, but in this embodiment, one pulse is left every N × L bits. That is different. As a result, in the first embodiment, the correlation processing is performed for each bit of the N-divided clock, but the correlation processing is performed for every L divided clocks. Since the number of pulses to be added or subtracted is every L, the amount of change in the smoothed DC voltage component is also 1 / L, so that a finer frequency change is possible with respect to the division ratio N. . Considering changing the 1 Hz frequency with the same parameters as in the first embodiment, for example, if N = 64 and L = 38, the pulse width of 1/64 clock is 3.2 ns, and the pulse width of the reference clock is 0.05 ns. Because
3.3V × 0.05ns / 3.2ns / 38 = 0.00135V
The voltage changes.

Therefore,
0.00135 × 5000 / 2π = 1.07Hz
Thus, a frequency change of 1 Hz can be realized with a frequency division ratio of about 64.

[Third Embodiment]
The configuration of the PLL circuit in this embodiment is the same as that in FIG.

  A third embodiment according to the present invention will be described with reference to FIG. In the second embodiment, one pulse is left for every N × L bits, but the correlation circuit 50 in the present embodiment changes the frequency by changing the number of pulses left at a constant interval with time. Control change. When the voltage corresponding to the amount of frequency shift corresponds to the increase or decrease resulting from correlation processing of P discrete pulses per N × K bits, N × K bits are not correlated with P discrete pulses from the beginning. Increase the number of pieces per little. For example, by increasing one by one, such as one, two,... P, the frequency is slowly adjusted toward the final target frequency shift amount compared to the case of performing P correlation processing from the beginning. Can be changed.

[Fourth embodiment]
FIG. 13 shows a configuration of a frequency control PLL circuit according to the fourth embodiment of the present invention. In the figure, the same components as those in FIG.

  The PLL circuit shown in the figure is different in circuit configuration from the first to third embodiments. Specifically, the correlation circuit 50 is arranged at the subsequent stage of the phase comparison circuit 20, performs correlation processing between the output of the phase comparison circuit 20 and the discrete pulse of the reference clock, and increases or decreases the DC component of the output of the phase comparison circuit 20 This causes a frequency shift. The operation principle can be explained by replacing “N frequency divider circuit output” with “phase comparison circuit output” in the first to third embodiments.

[Fifth embodiment]
A fifth embodiment will be described with reference to FIGS. In the present embodiment, in addition to the frequency shift adjustment by the correlation processing of the first to fourth embodiments, the time change of the frequency is controlled by changing the time constant of the low-pass filter 30. FIG. 14 shows a lag reed filter generally used as the low-pass filter 30. In the lag lead filter, the cutoff frequency fc is
fc = 1 / (2πC (R1 + R2))
Given in. Therefore, in the lag lead filter, the time constant of the low-pass filter 30 can be changed by changing the value of the capacitance C. The value of C can be changed by the voltage by using, for example, a varactor diode. FIG. 15 shows the calculation result of the frequency characteristics of the low-pass filter 30 when the resistance R1 = 1.5 kΩ and R2 = 260Ω and the value of the capacitance C is changed. Since fc changes depending on the capacitance value, the time constant of the PLL changes, and the temporal change in frequency can be controlled. From FIG. 15, it can be seen that as the C value is increased, fc becomes smaller and therefore the frequency change becomes slow, and when the C value is reduced, fc becomes larger and the frequency change becomes abrupt. As shown in FIG. 16, the temporal characteristic of the frequency change can be freely adjusted by combining the control of the time constant of the low-pass filter.

  The present invention is not limited to the above-described embodiment, and various modifications and applications can be made within the scope of the claims.

1 M frequency divider 2 phase comparison circuit 3 low-pass filter 4 voltage controlled oscillator 5 programmable counter (N)
10 Programmable counter (M frequency divider)
20 Phase comparison circuit 30 Low pass filter 40 Voltage controlled oscillator 50 Correlation circuit 60 Programmable counter (N frequency divider)

Claims (6)

A frequency control circuit that adjusts the reference frequency by slightly shifting,
A voltage-controlled oscillator whose output frequency changes according to the input voltage;
A first frequency divider that divides the output of the voltage controlled oscillator;
A second frequency divider that divides the reference frequency input from the outside;
A phase comparator that outputs a pulse corresponding to the phase of the output of the first frequency divider circuit and the second frequency divider circuit;
A low-pass filter that extracts a low-frequency component from the output of the phase comparator and inputs it to the voltage control generator;
A frequency control circuit for controlling an output frequency by adding or subtracting a predetermined voltage to a signal input to the voltage controlled oscillator. 2. The frequency control circuit according to claim 1, further comprising first correlation means for adjusting a voltage of an output signal of the phase comparator. 2. The frequency control circuit according to claim 1, further comprising second correlation means for adjusting the voltage of the output signal of the second frequency dividing circuit. 4. The frequency control circuit according to claim 1, further comprising a third correlator for controlling a time change of the output signal by changing a period for adjusting the output signal. 5. 4. The frequency control circuit according to claim 1, further comprising: a fourth correlation unit that controls a time change of the output frequency by changing a time constant of the low-pass filter. A frequency control method for adjusting the reference frequency by slightly shifting,
Compare the phase of the discrete pulse signal with the pulse width of the reference frequency changed at a constant period and the reference frequency,
A frequency control method characterized in that an output frequency is controlled by adding or subtracting a voltage by a voltage corresponding to a changed pulse width to a discrete pulse signal changed at a certain period.

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