JP2015103895A - Spread spectrum clock generation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To match an SS modulation cycle with an integral multiple of a cycle of a predetermined synchronizing signal without resetting a spread spectrum clock generation circuit, and to maintain continuity of the SS modulation cycle.SOLUTION: A phase controller 5 determines a phase φ of a rising edge of a phase shift clock signal pi_out selected by a phase selection circuit 6 so that a cycle of the phase shift clock signal pi_out becomes a length that is changed from a cycle of an output clock signal vco_ck just by a determined first phase shift amount pll_frac and generates a second phase shift amount pi_ssd that is periodically changed within a predetermined range. Further, a cycle error correction circuit 5c that the phase controller 5 includes generates a third phase shift amount cor_d and when performing spread spectrum modulation on the output clock signal vco_ck, a phase shift amount Δph of the output clock signal vco_ck is determined by the first phase shift amount pll_frac, the second phase shift amount pi_ssd and the third phase shift amount cor_d.

Description

  The present invention relates to a spread spectrum clock generation (SSCG) circuit.

  In the technical field of the clock generation circuit, in order to prevent the generation of EMI (radiated electromagnetic noise) having a peak at a specific frequency, the frequency of the clock signal is slightly modulated (spread spectrum) to be peaked at a specific frequency. There is known a “Spread Spectrum Clock Generator (SSCG) circuit” that reduces the peak value by dispersing EMI energy. As an SSCG circuit, for example, a system using a PLL (Phase Locked Loop) circuit disclosed in Patent Document 1 is known.

  FIG. 17 is a block diagram showing a configuration of a conventional spread spectrum clock generation (SSCG) circuit 90B. The SSCG circuit 90B of FIG. 17 is configured as a fractional PLL circuit. A reference clock signal ref_ck generated by a reference clock generator (not shown) is frequency-divided by the input frequency divider 11, and the frequency-divided input clock signal comp_ck is input to the phase frequency comparator 21. The phase frequency comparator 21 detects a phase difference between the input clock signal comp_ck and a feedback signal fb_ck described later, and outputs the phase difference to the charge pump 22. The charge pump 22 outputs the charge pump voltage increased or decreased according to the phase difference to the loop filter 23, and the loop filter 23 outputs the control voltage corresponding to the charge pump voltage to the voltage controlled oscillator (VCO) 24. The voltage controlled oscillator 24 includes a V / I converter 24a that converts a control voltage into a control current, and a current DA converter (IDAC) that generates a control current that is subjected to spread spectrum (SS) modulation under the control of the spread spectrum controller 25. 24b and a current controlled oscillator (CCO) 24c that generates and outputs an output clock signal vco_ck having a frequency and a phase corresponding to the SS-modulated control current. The output clock signal vco_ck is further divided by the output frequency divider 12 in order to use the output clock signal vco_ck, for example, in an image processing apparatus connected to the subsequent stage of the SSCG circuit 90B. Hereinafter, the signal divided by the output frequency divider 12 is referred to as a pixel clock signal pix_ck. The output clock signal vco_ck is divided by the frequency divider 26 and input to the phase frequency comparator 21 as the feedback signal fb_ck. The frequency division ratio of the frequency divider 26 is periodically switched between predetermined integers N and N + 1 according to the count value of the accumulator 27 that counts the input clock signal comp_ck. The fractional PLL circuit performs negative feedback control so that the frequency and phase of the feedback signal fb_ck coincide with the frequency and phase of the input clock signal comp_ck. Furthermore, by switching the frequency dividing ratio of the frequency divider 26, a frequency dividing ratio expressed on the average by a decimal number between N and N + 1 is realized.

  FIG. 16 is a diagram for explaining spread spectrum (SS) modulation by the current DA converter 24b of FIG. By performing SS modulation, the frequency of the output clock signal vco_ck periodically changes with a modulation period ssint over a frequency between the maximum frequency fmax and the minimum frequency fmin, centering on a predetermined center frequency fc. In the spread spectrum controller 25, a modulation degree ss_amp indicating the maximum change rate of the frequency of the output clock signal vco_ck is set. The modulation degree ss_amp takes an integer value of 0 to 31, and the maximum change rate of the frequency of the output clock signal vco_ck is represented by ss_amp / 1024 (%). For example, when ss_amp = 31, the frequency of the output clock signal vco_ck increases by about 3.1% with respect to the center frequency fc at the maximum frequency fmax, and decreases by about 3.1% with respect to the center frequency fc at the minimum frequency fmin. To do. The spread spectrum controller 25 generates SS modulation waveform data ddsd_org for changing the control current in the current DA converter 24b so as to change the frequency of the output clock signal vco_ck within the range of the maximum change rate. The SS modulation waveform data ddsd_org takes an integer value of 0 to 255, for example, the maximum value 255 corresponds to the maximum frequency fmax, the minimum value 0 corresponds to the minimum frequency fmin, and 128 is the center frequency fc (that is, the frequency change). None).

Hereinafter, a calculation example of the SS modulation waveform data ddsd_org shown in FIG. 16 when the frequency of the output clock signal vco_ck changes in a triangular waveform will be described. In order to calculate the SS modulation waveform data ddsd_org, for example, a count value count (n) that increments for each clock of the pixel clock signal pix_ck is used. The step size Δcount of the count value count (n), the initial value count (0) of the count value, and the count value count (n) are represented by (Equation 1) to (Equation 3), respectively.
Δcount = 2 × 255 / ssint (Equation 1)
count (0) = 0 (Equation 2)
count (n) = count (n−1) + Δcount, 1 ≦ n ≦ ssint−1 (Equation 3)

The count value count (n) is incremented by the step size Δcount over the modulation period ssint. In accordance with the count value count (n), the SS modulation waveform data ddsd_org is calculated from (Equation 4) to (Equation 6).
If 0 ≦ int (count (n)) <128:
ddsd_org = 128 + int (count (n)) (Expression 4)
If 128 ≦ int (count (n)) <383:
ddsd_org
= 255- {int (count (n))-127}
= 382-int (count (n)) (Equation 5)
If 383 ≦ int (count (n)) <510:
ddsd_org
= 128 + {int (count (n))-(2 × 255-0)}
= Int (count (n))-382 (Equation 6)

  Here, int (count (n)) represents the integer part of the count value count (n).

  The current DA converter 24b changes the control current for the current-controlled oscillator 24c based on the SS modulation waveform data ddsd_org, and thereby the output clock signal vco_ck is within the range of the maximum change rate represented by the modulation degree ss_amp. Change the frequency.

  In order to improve the accuracy of the amplitude of SS modulation, the current DA converter 24b uses a part of the control current of the current control oscillator 24c as a reference current, and uses the amplitude of the SS modulation waveform as the average frequency (of the output clock signal vco_ck). That is, tracking may be performed at the center frequency fc).

  However, according to such a conventional SSCG circuit 90B, when the spread spectrum modulation (SS modulation) cycle is desired to be an integral multiple of the cycle of a predetermined synchronization signal, the SSCG circuit 90B is reset for each predetermined synchronization signal. I had to hang it. Therefore, since the phase of the input clock signal comp_ck obtained by dividing the reference clock signal ref_ck and the phase of the SS-modulated output clock signal vco_ck are generated at the time of resetting, the continuity of the SS modulation waveform is impaired, There is a problem that the jitter of the output clock signal vco_ck generated based on the SS modulation waveform generated in this way cannot be sufficiently reduced.

  The present invention has been made in view of the above circumstances, and without changing the SSCG circuit, the spread spectrum period (SS modulation period) is adjusted to an integral multiple of the period of a predetermined synchronization signal, and the SS An object of the present invention is to obtain an SS modulation signal having an output clock signal vco_ck in phase with the input clock signal comp_ck by maintaining the continuity of the modulation period, thereby reliably reducing the jitter of the output clock signal vco_ck. .

  The spread spectrum clock generation circuit according to the present invention detects a phase difference between a reference input clock signal and a feedback signal, and outputs a control voltage corresponding to the phase difference, and a phase comparison means corresponding to the control voltage. Select one of voltage-controlled oscillation means for generating and outputting an output clock signal having a frequency, and a phase obtained by equally dividing one cycle of the clock of the output clock signal into a predetermined number, and a rising edge at the selected phase A phase selection means for generating a phase-shifted clock signal and sending the phase-shifted clock signal as the feedback signal to the phase comparison means; and a period of the phase-shifted clock signal is predetermined from a period of the output clock signal The phase of the rising edge of the phase-shifted clock signal selected by the phase selection means so that the length is changed by the first phase-shift amount. And a phase control means for controlling the phase selection means to select and determine the determined phase, wherein the phase control means is a second phase shift amount that periodically changes within a predetermined range. And determining the phase of the rising edge of the phase-shifted clock signal selected by the phase selecting means by adding the second phase shift amount to the first phase shift amount, and In the spread spectrum clock generation circuit for performing spread spectrum modulation on the output clock signal with the second phase shift amount that changes to the above, the phase control means further comprises: calculating the target value from the target value and the actual measurement value of the spread spectrum modulation period. Periodic error correction means for detecting a phase difference from the actual measurement value and generating a third phase shift amount for correcting the phase difference is provided. When adjusting, and determining the amount of phase shift when the spread spectrum modulation of said output clock signal and the third amount of phase shift may be reflected by.

  According to the spread spectrum clock generation circuit (SSCG circuit) configured as described above, the phase comparison means detects the phase difference between the reference input clock signal and the feedback signal, and outputs a control voltage corresponding to the phase difference. Then, the voltage controlled oscillation means generates and outputs an output clock signal having a frequency corresponding to the control voltage, and the phase selecting means equally divides one cycle of the clock of the output clock signal into a predetermined number of phases. Is selected, and a phase-shifted clock signal having a rising edge in the selected phase is generated and sent as a feedback signal to the phase comparison means. The phase control means outputs the period of the phase-shifted clock signal as an output clock. The rising edge of the phase-shifted clock signal selected by the phase selection means is set so that the length is changed by a predetermined first phase shift amount from the signal period. Determining the phase and controlling the phase selection means to select the determined phase, wherein the phase control means generates a second phase shift amount that periodically changes within a predetermined range; By adding the phase shift amount to the first phase shift amount, the phase of the rising edge of the phase shift clock signal selected by the phase selection means is determined, and the output clock signal is spread spectrum modulated by the second phase shift amount. In this case, the cycle error correction unit included in the phase control unit further detects the phase difference between the input clock signal that is the target value of the spread spectrum modulation cycle (SS modulation cycle) and the SS modulation clock that is the actual measurement value. Since the third phase shift amount for correcting the phase difference is generated and the third phase shift amount is reflected when the output clock signal is spread spectrum modulated, the SSCG circuit is not reset. An SS modulation signal having an output clock signal whose phase matches that of the reference clock signal is obtained by adjusting the S modulation period to an integral multiple of the period of the predetermined synchronization signal and maintaining the continuity of the SS modulation period. As a result, the jitter of the output clock signal can be reliably reduced.

  According to the spread spectrum clock generation circuit of the present invention, the SS modulation period is adjusted to an integral multiple of the period of the predetermined synchronization signal without resetting the SSCG circuit, and the continuity of the SS modulation period is maintained. Thus, it is possible to obtain an SS modulated signal having an output clock signal in phase with the reference clock signal, thereby reliably reducing jitter of the output clock signal.

1 is a block diagram showing a configuration of a spread spectrum clock generation circuit according to an embodiment of the present invention. FIG. 2 is a diagram for describing a phase of an output clock signal vco_ck selected by a phase selection circuit shown in FIG. 1. FIG. 2 is a diagram for describing a phase of an output clock signal vco_ck selected by a phase selection circuit shown in FIG. 1. 2 is a timing chart showing an example of phase shift performed when the frequency division ratio is 1 and the phase shift amount Δph is positive in the phase selection circuit shown in FIG. 1. 5 is a graph for explaining phases selected by a phase selection circuit when performing the phase shift shown in FIG. 4. 2 is a timing chart illustrating an example of phase shift performed when the frequency division ratio is 1 and the phase shift amount Δph is negative in the phase selection circuit illustrated in FIG. 1. It is a graph explaining the phase selected by a phase selection circuit when performing the phase shift shown in FIG. 2 is a timing chart showing an example of phase shift performed when the frequency division ratio is other than 1 and the phase shift amount Δph is positive in the phase selection circuit shown in FIG. 1. It is a graph explaining the phase selected by a phase selection circuit when performing the phase shift shown in FIG. 2 is a timing chart illustrating an example of phase shift performed when the frequency division ratio is other than 1 and the phase shift amount Δph is negative in the phase selection circuit illustrated in FIG. 1. It is a graph explaining the phase selected by a phase selection circuit when performing the phase shift shown in FIG. It is a figure for demonstrating the spread spectrum modulation performed with the phase selection circuit shown in FIG. It is a graph explaining the relationship between a synchronizing signal and SS modulation | alteration waveform. It is a block diagram explaining the structure of the loop filter in a phase controller. It is a graph explaining the SS modulation profile reflecting the correction value. It is a figure which shows the mode of the frequency modulation explaining the spread spectrum modulation performed with the spread spectrum clock generation circuit of FIG. 1 or FIG. It is a block diagram which shows the structure of the conventional spread spectrum clock generation circuit.

  Embodiments of a spread spectrum clock generation circuit according to the present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of a spread spectrum clock generation circuit 90A (SSCG circuit) according to the first embodiment of the present invention. The SSCG circuit 90A shown in FIG. 1 is configured as a fractional PLL circuit. A reference clock signal ref_ck generated by a reference clock generator (not shown) is frequency-divided by the input frequency divider 11, and the frequency-divided input clock signal comp_ck is input to the phase frequency comparator 1. The phase frequency comparator 1 detects a phase difference between the input clock signal comp_ck and a feedback signal fb_ck described later, and outputs it to the charge pump 2. The charge pump 2 outputs the charge pump voltage increased or decreased according to the phase difference to the loop filter 3, and the loop filter 3 outputs the control voltage corresponding to the charge pump voltage to the voltage controlled oscillator (VCO) 4. The voltage controlled oscillator 4 generates and outputs an output clock signal vco_ck having a frequency and phase corresponding to the control voltage. The output divider 12 divides the output clock signal vco_ck for use in other circuits and outputs it as a pixel clock signal pix_ck.

  The feedback circuit from the voltage controlled oscillator 4 to the phase frequency comparator 1 is provided with a phase selection circuit 6 that operates under the control of the phase controller 5 and a frequency divider 7 having a fixed integer frequency division ratio. . The phase selection circuit 6 generates and outputs a phase-shifted clock signal pi_out having a period changed from the period of the output clock signal vco_ck by changing the phase of the rising edge of the output clock signal vco_ck. Specifically, the phase selection circuit 6 selects one of the phases obtained by equally dividing one cycle of the clock of the output clock signal vco_ck into a predetermined number, and selects the phase-shifted clock signal pi_out having a rising edge in the selected phase. Generate and output. The phase controller 5 sets the period of the phase shift clock signal pi_out to a length that is changed from the period of the output clock signal vco_ck by a predetermined phase shift amount Δph (an integer multiple of the equally divided phase). Therefore, the phase of the phase shift clock signal pi_out selected by the phase selection circuit 6 is determined to control the phase selection circuit 6. The frequency divider 7 divides the phase-shifted clock signal pi_out and inputs it to the phase frequency comparator 1 as a feedback signal fb_ck.

  Specifically, the phase controller 5 includes a Δ value addition calculation unit 5a, a triangular wave generation unit 5b, a periodic error correction circuit 5c, a phase shift amount addition unit 5g, a phase selection signal generation unit 5h, and a frequency divider 5i. Has been. Their operation will be described later.

  The fractional PLL circuit included in the SSCG circuit 90A of the present embodiment performs negative feedback control so that the frequency and phase of the feedback signal fb_ck coincide with the frequency and phase of the input clock signal comp_ck. Further, the fractional PLL circuit of the present embodiment generates a phase shift clock signal pi_out having a period changed from the period of the output clock signal vco_ck by the phase selection circuit 6. For this reason, it is possible not only to change the frequency dividing ratio of the frequency divider 7 but to realize a rational frequency dividing ratio. When the phase shift amount Δph is positive, the frequency of the feedback signal fb_ck is higher than the frequency of the input clock signal comp_ck. When the phase shift amount Δph is negative, the frequency of the feedback signal fb_ck is higher than the frequency of the input clock signal comp_ck. Also lower. Furthermore, the SSCG circuit 90A of the present embodiment can SS modulate the frequency of the output clock signal vco_ck by changing the period of the phase-shifted clock signal pi_out by the phase selection circuit 6.

  The phase selection circuit 6 can further divide the output clock signal vco_ck when generating the phase shift clock signal pi_out having a period changed from the period of the output clock signal vco_ck. In the present embodiment, the set value of the division ratio of the phase selection circuit 6 is represented by div_puck = 0, 1, 2,..., And when div_puck = n, it is assumed that the division ratio is n + 1. When the output divider 12 has a division ratio of 2 or more, the phase selection circuit 6 further divides the output clock signal vco_ck in consideration of this division ratio. In the present embodiment, the set value of the frequency division ratio of the output frequency divider 12 is expressed by div_pll = 0, 1, 2,..., And when div_pll = n, the frequency division ratio is assumed to be n + 1. In the present embodiment, the set value of the frequency division ratio of the frequency divider 7 is represented by div_fb = 0, 1, 2,..., And when div_fb = n, the frequency division ratio is n + 1. Therefore, the division ratio of the feedback signal fb_ck to the output clock signal vco_ck is obtained by multiplying the division ratio of the phase selection circuit 6, the division ratio of the output divider 12, and the division ratio of the divider 7. become.

  The output divider 12 divides the output clock signal vco_ck having a frequency of, for example, 60 to 120 MHz into a pixel clock signal pix_ck having a frequency of 5 to 40 MHz.

  2 and 3 are diagrams for explaining the phase of the output clock signal vco_ck selected by the phase selection circuit 6. In the present embodiment, it is assumed that the phase selection circuit 6 selects one of the phases (shown as 0 to 511 in FIGS. 2 and 3) obtained by equally dividing one cycle of the clock of the output clock signal vco_ck into 512 pieces. The phase selection circuit 6 functions as a phase interpolator that inserts a rising edge into an arbitrary phase.

  First, the operation of the SSCG circuit 90A as a fractional PLL circuit will be described in detail with reference to FIGS. For simplification of explanation, it is assumed that the division ratios of the phase selection circuit 6, the output divider 12, and the divider 7 are all 1, that is, div_puck = 0, div_fb = 0, div_pll = 0. .

  FIG. 4 is an example of the phase shift performed by the phase selection circuit 6 of FIG. 1, and is a timing chart showing the phase shift when the phase shift amount Δph is positive. The horizontal axis of FIG. 4 sets the phase φ obtained by equally dividing one cycle of the clock of the output clock signal vco_ck to 512 as a minimum unit (hereinafter, the phase φ is expressed in the same unit throughout FIGS. 5 to 11). ). In the case of FIG. 4, the cycle of the phase shift clock signal pi_out increases by the phase shift amount Δph from the cycle of the output clock signal vco_ck (ie, becomes 512 + Δph). Therefore, the rising edge of each clock of the phase-shifted clock signal pi_out is delayed by an amount of phase shift Δph from the rising edge of each clock corresponding to the output clock signal vco_ck each time the clock advances.

  Now, it is assumed that the rising edges of the first clock vco_ck (0) of the output clock signal vco_ck and the first clock pi_out (0) of the phase shift clock signal pi_out coincide. At this time, the rising edge of the second clock pi_out (1) of the phase shift clock signal pi_out is delayed by the phase shift amount Δph from the rising edge of the second clock vco_ck (1) of the output clock signal vco_ck. The rising edge of the third clock pi_out (2) of the phase shift clock signal pi_out is delayed by twice the phase shift amount Δph from the rising edge of the third clock vco_ck (2) of the output clock signal vco_ck. Similarly, the rising edge of the nth clock pi_out (n−1) of the phase shift clock signal pi_out is n−1 of the phase shift amount Δph from the rising edge of the nth clock vco_ck (n−1) of the output clock signal vco_ck. Delay by a factor of two.

  FIG. 5 is a graph for explaining the phase φ selected by the phase selection circuit 6 when the phase shift of FIG. 4 is performed. The phase selection circuit 6 selects any one of the phases 0 to 511 obtained by equally dividing one cycle of the clock of the output clock signal vco_ck into 512 as the current phase φ. As shown in FIG. 5, every time the clock of the output clock signal vco_ck advances, the phase selection circuit 6 selects the phase incremented by the phase shift amount Δph as a new phase φ. When the phase φ is incremented by the phase shift amount Δph, there are cases where the phase of φ after the increment is less than one cycle of the output clock signal vco_ck and when it is longer than one cycle. When the phase φ after the increment is less than one cycle of the output clock signal vco_ck, the rising edge of the next clock of the phase shift clock signal pi_out corresponds to the corresponding phase φ within the cycle of the next clock of the output clock signal vco_ck. It is in. For example, this is the case when the phase φ after the increment is 511 or less. On the other hand, when the phase φ after the increment exceeds one cycle of the output clock signal vco_ck, the rising edge of the next clock of the phase shift clock signal pi_out is the phase φ after the increment in the clock cycle two clocks after the output clock signal vco_ck. The phase φ is obtained by subtracting 512 from the phase φ. For example, the case where the phase φ after the increment is 512 or more corresponds to this case. In the latter case, for example, as illustrated in FIG. 4, the rising edge of the fifth clock pi_out (4) of the phase shift clock signal pi_out is not the fifth clock vco_ck (4) of the output clock signal vco_ck but the sixth clock vco_ck ( It is within the period of 5). Accordingly, the phase φ is delayed from the rising edge of the sixth clock vco_ck (5) of the output clock signal vco_ck by a remainder of mod (4 × Δph, 512), that is, 4 × Δph divided by 512. In FIG. 5, the delay of the phase φ is indicated by a white arrow. That is, instead of selecting the phase φ indicated by the circles (p1, p2, p3) of the clocks vco_ck (4), vco_ck (8), vco_ck (12) of the output clock signal vco_ck, the next clock circle (P1 , P2, P3) is selected.

  As described above with reference to FIGS. 4 and 5, by selecting the phase φ, the period of each clock pi_out (0),..., Pi_out (n) of the phase-shifted clock signal pi_out is set to the clock of the output clock signal vco_ck. The length is increased from the cycle by the phase shift amount Δph. That is, in the present embodiment, the period of the phase-shifted clock signal pi_out is 512 + Δph.

  In FIG. 6, the frequency division ratios of the phase selection circuit 6, the output frequency divider 12, and the frequency divider 7 are all 1, that is, div_puck = 0, div_fb = 0, and div_pll = 0. This is an example of the phase shift performed by the phase selection circuit 6. That is, it is a timing chart showing the state of phase shift when the phase shift amount Δph is negative. In the case of FIG. 6, the cycle of the phase shift clock signal pi_out is shortened by the phase shift amount | Δph | from the cycle of the output clock signal vco_ck (that is, 512− | Δph |). Accordingly, the rising edge of each clock of the phase-shifted clock signal pi_out precedes the rising edge of each corresponding clock of the output clock signal vco_ck by incrementing the phase shift amount | Δph | every time the clock advances.

  Now, it is assumed that the rising edges of the first clock vco_ck (0) of the output clock signal vco_ck and the first clock pi_out (0) of the phase shift clock signal pi_out coincide. At this time, the rising edge of the second clock pi_out (1) of the phase shift clock signal pi_out precedes the rising edge of the second clock vco_ck (1) of the output clock signal vco_ck by the phase shift amount | Δph |. The rising edge of the third clock pi_out (2) of the phase shift clock signal pi_out precedes the rising edge of the third clock vco_ck (2) of the output clock signal vco_ck by twice the phase shift amount | Δph |. Similarly, the rising edge of the nth clock pi_out (n−1) of the phase shift clock signal pi_out is n of the phase shift amount | Δph | from the rising edge of the nth clock vco_ck (n−1) of the output clock signal vco_ck. -1 times ahead.

  FIG. 7 is a graph for explaining the phase φ selected by the phase selection circuit 6 when the phase shift of FIG. 6 is performed. As shown in FIG. 7, each time the clock of the output clock signal vco_ck advances, the phase selection circuit 6 selects the phase φ preceded by the phase shift amount | Δph | as a new phase φ. If the phase preceded by the phase shift amount | Δph | does not become negative even if the phase φ is preceded by the phase shift amount | Δph |, the rising edge of the clock next to the phase shift clock signal pi_out is the period of the clock next to the output clock signal vco_ck. Of the corresponding phase φ. On the other hand, when the preceding phase φ becomes negative when the phase shift amount | Δph | is advanced by one, the phase φ of the rising edge of the next clock of the phase shift clock signal pi_out is the next clock of the output clock signal vco_ck. It will not be a rising edge. That is, in this case, the phase is obtained by adding 512 to the preceding and succeeding phases within the current clock cycle. In the latter case, for example, as illustrated in FIG. 6, the rising edge of the fifth clock pi_out (4) of the phase shift clock signal pi_out is not within the period of the fourth clock vco_ck (3) of the output clock signal vco_ck. It is within the period of the clock vco_ck (2). That is, the leading edge of the fourth clock vco_ck (3) of the output clock signal vco_ck is preceded by mod (4 × | Δph |, 512) corresponding to the remainder when 4 × | Δph | is divided by 512. In FIG. 7, the preceding phase φ is indicated by a white arrow. That is, instead of selecting the phase φ indicated by the circles (q1 to q7) of the clocks vco_ck (1), vco_ck (3),... Of the output clock signal vco_ck, the circles (Q1 to Q7) of the previous clock are selected. The phase φ corresponding to is selected.

  As described above with reference to FIGS. 6 and 7, by selecting the phase φ, the cycle of each clock pi_out (0),..., Pi_out (n) of the phase-shifted clock signal pi_out is the same as that of the output clock signal vco_ck. The length is obtained by subtracting the phase shift amount | Δph | from the period. That is, in the present embodiment, the period of the phase-shifted clock signal pi_out is 512- | Δph |.

  As described with reference to FIGS. 4 to 7, the phase controller 5 determines the phase φ of the rising edge of the phase-shifted clock signal pi_out, and controls the operation of the phase selection circuit 6 according to the determined phase φ.

When the frequency of the phase-shifted clock signal pi_out is fpi_out and the frequency of the output clock signal vco_ck is fvco_ck, (Equation 7) holds.
fpi_out = fvco_ck × 512 / (512 + Δph) (Expression 7)

At this time, as described above, the fractional PLL circuit of the present embodiment performs negative feedback control so that the frequency and phase of the feedback signal fb_ck coincide with the frequency and phase of the input clock signal comp_ck. Therefore, when the frequency of the input clock signal comp_ck is fcomp_ck and the frequency of the feedback signal fb_ck is ffb_ck, (Equation 8) to (Equation 10) are established between the frequencies of the respective signals.
ffb_ck = fpi_out = fcomp_ck (Equation 8)
fcomp_ck = fvco_ck × 512 / (512 + Δph) (Equation 9)
fvco_ck = fcomp_ck × (1 + Δph / 512) (Equation 10)

  According to the SSCG circuit 90A including the fractional PLL circuit of the present embodiment, a very small multiplication factor (for example, a multiplication factor of 1% or less) can be realized by improving the resolution of the phase selection circuit 6. For example, in this embodiment, the minimum multiplication rate is 1 / 512≈0.002 = 0.2%.

  Next, referring to FIG. 8 to FIG. 11, when each division ratio of the phase selection circuit 6, the output divider 12, and the divider 7 is considered, that is, any of div_puck, div_fb, div_pll The operation of the SSCG circuit 90A when the number is 1 or more will be described. 8 to 11 show a case where the division ratio setting value div_puck = 2 of the phase selection circuit 6, that is, the division ratio of the phase selection circuit 6 is 3. FIG.

  FIG. 8 is an example of a phase shift by the phase selection circuit 6 of the SSCG circuit 90A in this setting state, and is a timing chart showing the state of the phase shift when the phase shift amount Δph is positive. The three clocks of the output clock signal vco_ck corresponding to the frequency division ratio 3 of the phase selection circuit 6 are collectively referred to as the frequency division clock signal div_ck of the phase selection circuit 6. For example, the tenth to twelfth clocks vco_ck (9), vco_ck (10), and vco_ck (11) of the output clock signal vco_ck become the fourth clock div_ck (3) of the divided clock signal. In each of the clocks of the divided clock signal div_ck, the three clocks of the output clock signal vco_ck are referred to as first to third sub clocks vco_ck (0) ′, vco_ck (1) ′, and vco_ck (2) ′. In the case of FIG. 8, the period of the phase shift clock signal pi_out increases by a phase shift amount Δph from the period of three clocks of the output clock signal vco_ck (that is, the period of the divided clock signal div_ck) (ie, 512 × 3 + Δph). ). Accordingly, the rising edge of each clock of the phase-shifted clock signal pi_out is delayed by an increment of the phase shift amount Δph from the rising edge after 3 clocks of the output clock signal vco_ck each time the clock advances.

  Now, it is assumed that the rising edges of the first clock vco_ck (0) of the output clock signal vco_ck and the first clock pi_out (0) of the phase shift clock signal pi_out coincide. The rising edge of the second clock pi_out (1) of the phase shift clock signal pi_out is delayed by the phase shift amount Δph from the rising edge of the fourth clock vco_ck (3) of the output clock signal vco_ck. The rising edge of the third clock pi_out (2) of the phase shift clock signal pi_out is delayed from the rising edge of the seventh clock vco_ck (6) of the output clock signal vco_ck by twice the phase shift amount Δph. Similarly, the rising edge of the nth clock pi_out (n−1) of the phase shift clock signal pi_out is shifted in phase amount Δph from the rising edge of the (3n−2) clock vco_ck (3n−3) of the output clock signal vco_ck. Is delayed by n-1 times.

  FIG. 9 is a graph for explaining the phase φ selected by the phase selection circuit 6 when the phase shift of FIG. 8 is performed. The phase selection circuit 6 selects any one of the phases 0 to 1535 obtained by equally dividing the period of the divided clock signal div_ck into 1536 as the current phase φ. However, the phase selection circuit 6 substantially selects any one of the phases 0 to 511 obtained by equally dividing one cycle of the clock of the output clock signal vco_ck into 512, as in FIGS. As shown in FIG. 9, the phase selection circuit 6 selects a phase that is incremented by the phase shift amount Δph as a new phase φ every time the clock of the divided clock signal div_ck advances. Note that when the phase φ is incremented by the phase shift amount Δph, there are cases where the phase after the increment is less than one cycle of the divided clock signal div_ck and when it is one cycle or more. When the incremented phase φ is less than one cycle of the divided clock signal div_ck, the rising edge of the next clock of the phase-shifted clock signal pi_out corresponds to the next clock cycle of the divided clock signal div_ck. It is in phase φ. For example, the case where the phase φ after the increment is 1535 or less corresponds to this case. On the other hand, when the phase φ after the increment exceeds one cycle of the divided clock signal div_ck, the rising edge of the next clock of the phase-shifted clock signal pi_out is the increment within the cycle two clocks after the divided clock signal div_ck. It is in the phase φ obtained by subtracting 1536 from the later phase φ. For example, the case where the phase φ after the increment is 1535 or more corresponds to this case. In the latter case, for example, as shown in FIG. 8, the rising edge of the eighth clock pi_out (7) of the phase-shifted clock signal pi_out is within the period of the seventh clock div_ck (6) of the divided clock signal. Therefore, the rising edge of the eighth clock pi_out (7) is mod (5 × Δph, 1536), that is, 5 × Δph divided by 1536 from the head of the seventh clock div_ck (6) of the divided clock signal. Delay by the remainder of. In FIG. 9, this delay is indicated by a white arrow. That is, instead of selecting the phase φ indicated by the circles (r1, r2) of the clocks div_ck (5), div_ck (11) of the divided clock signal, it corresponds to the circles (R1, R2) of the next clock. The phase φ to be selected is selected.

  As described with reference to FIGS. 8 and 9, by selecting the phase φ, the period of each clock pi_out (0),..., Pi_out (n) of the phase-shifted clock signal pi_out is equal to three clocks of the output clock signal vco_ck. The length is increased from the cycle by the phase shift amount Δph. That is, in the case of the present embodiment, the period of the phase shift clock signal pi_out is 512 × 3 + Δph.

  FIG. 10 is a timing chart showing the phase shift when the division ratio setting value of the phase selection circuit 6 is div_puck = 2, that is, the division ratio of the phase selection circuit 6 is 3, as before. . In particular, FIG. 10 shows the phase shift when the phase shift amount Δph is negative. In the case of FIG. 10, the period of the phase shift clock signal pi_out is shortened by the phase shift amount Δph from the period of three clocks of the output clock signal vco_ck (that is, the period of the divided clock signal div_ck) (that is, 512 × 3- | Δph |). Accordingly, the rising edge of each clock of the phase-shifted clock signal pi_out precedes the rising edge after three clocks of the output clock signal vco_ck by incrementing the phase shift amount | Δph | every time the clock advances.

  Now, it is assumed that the rising edges of the first clock vco_ck (0) of the output clock signal vco_ck and the first clock pi_out (0) of the phase shift clock signal pi_out coincide. The rising edge of the second clock pi_out (1) of the phase shift clock signal pi_out precedes the rising edge of the fourth clock vco_ck (3) of the output clock signal vco_ck by the phase shift amount | Δph |. The rising edge of the third clock pi_out (2) of the phase shift clock signal pi_out precedes the rising edge of the seventh clock vco_ck (6) of the output clock signal vco_ck by twice the phase shift amount | Δph |. Similarly, the rising edge of the nth clock pi_out (n−1) of the phase shift clock signal pi_out is shifted from the rising edge of the (3n−2) th clock vco_ck (3n−3) of the output clock signal vco_ck | It precedes by n−1 times Δph |.

  FIG. 11 is a graph for explaining the phase φ selected by the phase selection circuit 6 when the phase shift of FIG. 10 is performed. As shown in FIG. 11, every time the clock of the divided clock signal div_ck advances, the phase selection circuit 6 selects the phase φ preceded by the phase shift amount | Δph | as a new phase φ. Note that if the preceding phase does not become negative even if the phase φ is preceded by the phase shift amount | Δph |, the rising edge of the next clock of the phase-shifted clock signal pi_out is the next clock of the divided clock signal div_ck. It is in the corresponding phase φ within the period. On the other hand, when the preceding phase φ becomes negative when preceding by the phase shift amount | Δph |, the phase φ of the rising edge of the next clock of the phase shift clock signal pi_out is the current of the divided clock signal div_ck. This is a phase obtained by adding 1536 to the preceding and succeeding phases in the cycle. In the latter case, for example, as shown in FIG. 10, the rising edge of the sixth clock pi_out (5) of the phase-shifted clock signal pi_out is within the period of the fourth clock div_ck (3) of the divided clock signal. Therefore, mod (5 × | Δph |, 1536), that is, 5 × | Δph | divided by 1536 precedes from the rising edge of the fifth clock div_ck (4) of the divided clock signal. In FIG. 11, the preceding phase φ is indicated by a white arrow. That is, instead of selecting the phase φ indicated by the circles (s1 to s5) of the clocks div_ck (1), div_ck (4),... Of the divided clock signal, the previous clock circles (S1 to S5). The phase φ corresponding to is selected.

  As described with reference to FIGS. 10 and 11, by selecting the phase φ, the period of each clock pi_out (0),..., Pi_out (n) of the phase-shifted clock signal pi_out is equal to three clocks of the output clock signal vco_ck. The length is obtained by subtracting the phase shift amount | Δph | from the period. That is, in the present embodiment, the period of the phase-shifted clock signal pi_out is 512 × 3- | Δph |.

  As described with reference to FIGS. 8 to 11, the phase controller 5 determines the phase φ of the rising edge of the phase-shifted clock signal pi_out, and controls the operation of the phase selection circuit 6 according to the determined phase φ.

In the case of FIGS. 8 to 11 (that is, when any of div_puck, div_fb, div_pll is 1 or more), (Equation 7) is transformed from (Equation 11) to (Equation 13).
fpi_out = fvco_ck × 512 / {512 × (div_pll + 1) × (div_puck + 1) + Δph} (Expression 11)
fcomp_ck
= Ffb_ck
= Fpi_out / ([div_fb] +1)
= Fvco_ck × 512 / [{512 × (div_pll + 1) × (div_puck + 1) + Δph} × ([div_fb] +1)] (Equation 12)
fvco_ck
= Fcomp_ck × (div_fb + 1) × {512 × (div_pll + 1) × (div_puck + 1) + Δph} / 512
= Fcomp_ck × (div_fb + 1) × {(div_pll + 1) × (div_puck + 1) + Δph / 512}
= Fcomp_ck × {(div_fb + 1) × (div_pll + 1) × (div_puck + 1) + (div_fb + 1) × Δph / 512} (Equation 13)

According to the SSCG circuit 90A including the fractional PLL circuit of the present embodiment, a smaller multiplication factor can be realized by the phase selection circuit 6 performing frequency division. For example, in the models of (Equation 11) to (Equation 13), the minimum multiplication rate (%) is expressed by (Equation 14).
([Div_fb] +1) × Δph / 512
≈ 0.002 × ([div_fb] +1)
= 0.2 × ([div_fb] +1)% (Equation 14)

The minimum unit of the change rate of the frequency fvco_ck of the output clock signal vco_ck is expressed by (Expression 15).
Δfvco_ck / fvco_ck
= {(Div_pll + 1) × (div_puck + 1) + Δph / 512}
/ {(Div_pll + 1) × (div_puck + 1) +0/512}
= 1 + Δph / {512 × (div_pll + 1) × (div_puck + 1)}
≈ 1 + 0.002 / {(div_pll + 1) × (div_puck + 1)} (Expression 15)

  Thus, according to the SSCG circuit 90A including the fractional PLL circuit of the present embodiment, the frequency dividing ratio of the frequency divider 7 is a fixed value during operation, and the frequencies of the phase shift clock signal pi_out and the feedback signal fb_ck are also constant. It is. Therefore, the phase mismatch in the phase frequency comparator 1 that occurs when the frequency division ratio of the frequency divider is changed as in the prior art can be eliminated. Then, due to this phase mismatch, it is possible to prevent spurious generation, which is an unnecessary signal component mixed in the output clock signal vco_ck, and to reduce jitter that is a phase fluctuation of the output clock signal vco_ck. Further, according to the SSCG circuit 90A including the fractional PLL circuit of the present embodiment, the frequency division ratio of the frequency divider 7 can be reduced by improving the resolution of the phase selection circuit 6. As a result, it is possible to increase the loop band of the fractional PLL circuit and reduce jitter, which is a phase fluctuation of the output clock signal vco_ck.

  As described above, according to the present embodiment, it is possible to provide the SSCG circuit 90A including a novel fractional PLL circuit that does not use the principle of operation to change the frequency division ratio of the frequency divider. Further, the phase selection circuit 6 performs frequency division, so that the resolution of the fractional PLL circuit can be improved.

  Next, SS modulation by the phase selection circuit 6 will be described with reference to FIGS. FIG. 12 is a diagram for explaining spread spectrum modulation by the phase selection circuit 6 of FIG. FIG. 13 is an enlarged view showing a change in the phase shift amount Δph of FIG.

  As described with reference to FIGS. 4 to 11, the SSCG circuit 90 </ b> A including the fractional PLL circuit according to the present embodiment corresponds to the period of the phase shift clock signal pi_out from the period of the output clock signal vco_ck to the phase shift amount Δph. Change by the amount you want. At this time, the output clock signal vco_ck is further changed by changing the phase shift amount pll_frac (hereinafter referred to as the first phase shift amount pll_frac) which is the center of the phase shift amount Δph by the second phase shift amount pi_ssd. SS modulation is performed. The frequency f of the output clock signal vco_ck depends on the setting values div_puck, div_fb, div_pll, the modulation degree ss_amp, and the modulation period ssint of the respective division ratios of the phase selection circuit 6, the output divider 12, and the divider 7. In the same manner as in FIG.

Here, a specific SS modulation method will be described. Now, let the minimum time unit for changing the phase shift amount Δph for performing SS modulation be SS modulation clocks puck (0), puck (1),..., Puck (n). The SS modulation clock puck (n) is obtained by dividing the clock of the output clock signal vco_ck based on the frequency division ratio set by the output frequency divider 12 and the frequency division ratio set by the phase selection circuit 6. is there. Therefore, the frequency fpuck of the SS modulation clock puck (n) is expressed by (Equation 16) and (Equation 17).
fpuck = fpix_ck / (div_puck + 1) (Equation 16)
fpix_ck = fvco_ck / (div_pll + 1) (Equation 17)

  Specifically, this processing is executed in the frequency divider 5i inside the phase controller 5 shown in FIG.

  As shown in FIG. 12, the phase shift amount Δph is changed stepwise with a step size Δθ for each time interval (hereinafter referred to as a step time interval step_p) including a predetermined number of SS modulation clocks puck (n). Approximately, the phase shift amount Δph is changed in a triangular wave shape. The number of SS modulation clocks puck (n) in the step time interval step_p varies depending on the setting.

Next, the maximum value pi_ssd_max and the minimum value pi_ssd_min of the second phase shift amount pi_ssd are calculated from (Equation 18) to (Equation 20).
pi_ssd_max = int ([ss_amp] / 1024 / Δf_step) (Expression 18)
pi_ssd_min = −int ([ss_amp] / 1024 / Δf_step) (Expression 19)
Δf_step
= Δfvco_ck / fvco_ck-1
= 1/512 / {(div_pll + 1) × (div_puck + 1)} (Equation 20)

  The definition of the modulation degree ss_amp is as described in the background art section.

Next, in order to calculate the second phase shift amount pi_ssd, a count value count (n) that is incremented every modulation clock puck (n) is introduced. The count value count (n) and its step size Δcount are represented by decimal numbers including, for example, a 9-bit integer part and a 16-bit decimal part. The step size Δcount of the count value, the initial value count (0) of the count value, and the count value count (n) are expressed by (Equation 21) to (Equation 23).
Δcount = 2 × (pi_ssd_max−pi_ssd_min) / ssint (Expression 21)
count (0) = 0 (Equation 22)
count (n) = count (n−1) + Δcount, 1 ≦ n ≦ ssint−1 (Equation 23)

The count value count (n) is incremented by the step size Δcount over the modulation period ssint. In accordance with the count value count (n), the second phase shift amount pi_ssd is calculated from (Equation 24) to (Equation 26).
If 0 ≦ int (count (n)) <pi_ssd_max + 1:
pi_ssd = int (count (n)) (Equation 24)
When pi_ssd_max + 1 ≦ int (count (n)) <pi_ssd_max + 1 + (pi_ssd_max−pi_ssd_min):
pi_ssd = pi_ssd_max− {int (count (n)) − pi_ssd_max} (Equation 25)
When pi_ssd_max + 1 + (pi_ssd_max−pi_ssd_min) ≦ int (count (n)) <2 × (pi_ssd_max−pi_ssd_min):
pi_ssd = pi_ssd_min + {int (count (n)) − (2 × pi_ssd_max−pi_ssd_min)} (Equation 26)

  Specifically, this calculation is performed in the Δ value addition calculation unit 5a and the triangular wave generation unit 5b inside the phase controller 5 shown in FIG.

By adding the second phase shift amount pi_ssd calculated as described above to the first phase shift amount pll_frac, the phase shift amount Δph of the phase selection circuit 6 is obtained as shown in FIG. That is, the phase shift amount Δph when performing SS modulation is expressed by (Equation 27).
Δph = pll_frac + pi_ssd (Equation 27)

  According to the spread spectrum clock generation circuit 90A (SSCG circuit) of the present embodiment, the frequency of the output clock signal vco_ck can be changed as shown in FIG. 16 by changing the phase shift amount Δph in this way. When the phase shift amount Δph increases, the frequency fvco_ck of the output clock signal vco_ck also increases. When the phase shift amount Δph decreases, the frequency fvco_ck of the output clock signal vco_ck also decreases.

  FIG. 13 is a diagram for explaining the relationship between the synchronization signal (lsync) and the SS modulation waveform. It is assumed that lsync is a synchronization signal (for example, a line synchronization signal at the time of image writing / reading processing), and its cycle is 512 cycles generated by the input clock signal comp_ck (FIG. 1) that is not SS-modulated. Further, it is assumed that the SS modulation clock puck (n) is a clock obtained by SS-modulating the input clock signal comp_ck with the divided clock (FIG. 17) of the output clock signal vco_ck. At this time, the SS modulation cycle is puck and is 512 cycles, and the puck average frequency at the time of SS modulation is equal to the input clock signal comp_ck.

  In order for the cycle of the synchronization signal lsync and the SS modulation cycle to be an integer multiple of 1: 1, the phases of the input clock signal comp_ck and the SS modulation clock puck (n) should be the same for each cycle of the synchronization signal lsync. . That is, every 512 cycles of the input clock signal comp_ck, the phases of the input clock signal comp_ck and the SS modulation clock puck (n) should match.

  However, actually, as shown in FIG. 13, there is a difference between the clock phase of the input clock signal comp_ck for each period of the synchronization signal lsync and the clock phase of the SS modulation clock puck (n). Therefore, the synchronization signal lsync and the SS modulation waveform gradually shift with time. Note that this phase shift occurs due to various factors such as a response delay of the SSCG circuit 90A.

  For this reason, in this embodiment, the period error correction circuit 5c provided in the phase controller 5 shown in FIG. 1 is used to correct the period of the synchronization signal lsync and the period error of the SS modulation waveform.

  In the period error correction circuit 5c, the phase comparison unit 5d performs phase comparison between the input clock signal comp_ck and the SS modulation clock puck (n) for each period of the SS modulation waveform. Then, a phase shift amount cor_d (third phase shift amount) that is a correction value corresponding to the SS modulation profile (pi_ssd) is generated from the phase difference value sub_cnt via the loop filter 5e (LPF).

  For example, when the SS modulation cycle is 512puck, the phase comparison unit 5d measures the phase difference of each clock after 512 clocks with the input clock signal comp_ck and the SS modulation clock puck (n), and outputs the difference value sub_cnt. . The clock to be measured is preferably the fastest output clock signal vco_ck. (Puck is div_puck + 1 divided clock of output clock signal vco_ck)

  For example, if the difference value sub_cnt when the phase comparison is performed with the output clock signal vco_ck is one clock, it indicates that the SS modulation period is larger by one clock of the output clock signal vco_ck. When the minimum unit of the phase φ that can be selected in the phase selection circuit 6 of FIG. 1 is 1/512 phase as shown in FIG. 2, in order to correct this difference, the phase shift amount Δph within the next 1SS modulation period May be added in total 512.

  Note that if the difference value sub_cnt is immediately reflected in the next SS modulation period, the change becomes too large, and therefore a loop filter 5e is inserted after the phase comparison unit 5d. For example, as shown in FIG. 14, the loop filter 5e is configured by a PI (proportional integration) type low-pass filter.

  Specifically, the loop filter 5e includes two adders 5p and 5t, a delay element 5q, and two multipliers 5r and 5s.

  The adders 5p and 5t output the sum of the two input signals. Delay element 5q delays the signal by one sampling period. The multipliers 5r and 5s output the input signals by multiplying the coefficients Ki and Kp by Ki and Kp, respectively.

  The loop filter 5e outputs a filter output lpf_out in which the high-frequency component determined by the constant of each element described above is cut with respect to the input difference value sub_cnt. The frequency band of the loop filter 5e can be changed by changing the coefficients Ki and Kp in FIG.

  The correction value control unit 5f outputs an optimum phase shift amount cor_d (hereinafter referred to as a third phase shift amount cor_d) according to the value of the filter output lpf_out. For example, when lpf_out = 1/32, it indicates that the SS modulation period is larger by 1/32 clock in vco_ck. To correct this, the phase shift amount Δph may be added for a total of 512/32 = 16 cycles within the next 1SS modulation period. FIG. 15 shows an example of the SS modulation profile when 16 cycles are added.

In addition to the addition of the second phase shift amount pi_ssd and the first phase shift amount pll_frac described above, the third phase shift amount cor_d that is a correction value calculated by the periodic error correction circuit 5c of FIG. 1 is added. As shown in FIG. 15, the phase shift amount Δph of the phase selection circuit 6 is obtained. That is, the phase shift amount Δph when performing SS modulation is expressed by the following equation.
Δph = pll_frac + pi_ssd + cor_d (Equation 28)

  More specifically, this calculation is performed in the phase shift amount adding unit 5g configured by an adder inside the phase controller 5 shown in FIG. Then, in the phase selection signal generation unit 5h, an SS modulation profile reflecting the calculated phase shift amount Δph is generated.

  According to the spread spectrum clock generation circuit of this embodiment, the frequency of the output clock signal vco_ck can be changed as shown in FIG. 16 by changing the phase shift amount Δph in this way. That is, when the phase shift amount Δph increases, the frequency fvco_ck of the output clock signal vco_ck increases, and when the phase shift amount Δph decreases, the frequency fvco_ck of the output clock signal vco_ck decreases.

  Note that the response characteristic of the loop of the fractional PLL circuit needs to be sufficiently high with respect to the SS modulation frequency. When the frequency of the output clock signal vco_ck is on the order of 100 MHz, for example, about 10 to 50 kHz can be used as the SS modulation frequency.

  As described above, according to the spread spectrum clock generation circuit 90A (SSCG circuit) according to the first embodiment, the phase comparison unit 5d (phase comparison unit) determines the phase difference between the input clock signal comp_ck and the feedback signal fb_ck. The value sub_cnt (phase difference) is detected. Then, a control voltage corresponding to the difference value sub_cnt is output, and the voltage controlled oscillator 4 (voltage controlled oscillating means) generates and outputs an output clock signal vco_ck having a frequency corresponding to the control voltage. Further, the phase selection circuit 6 (phase selection means) selects any one of the phases φ obtained by equally dividing one cycle of the clock of the output clock signal vco_ck into a predetermined number, and sets the rising edge to the selected phase φ. The phase-shifted clock signal pi_out is generated. Then, the generated phase shift clock signal pi_out is sent to the phase comparison unit 5d as a feedback signal fb_ck. The phase controller 5 (phase control means) sets the period of the phase shift clock signal pi_out to a length that is changed from the period of the output clock signal vco_ck by a first phase shift amount pll_frac. Therefore, the phase φ of the rising edge of the phase shift clock signal pi_out selected by the phase selection circuit 6 is determined. Further, the phase selection circuit 6 is controlled so as to select the determined phase φ, and the phase controller 5 further reduces the first phase shift amount pll_frac to a predetermined range by the second phase shift amount pi_ssd. Change periodically. SS modulation of the output clock signal vco_ck is performed by the first phase shift amount pll_frac and the second phase shift amount pi_ssd generated in this way. Further, the cycle error correction circuit 5c (cycle error correction means), for each cycle of the SS modulation waveform ddsd_org, receives the input clock signal comp_ck that is the target value of the SS modulation cycle and the SS modulation clock puck that is the actual value of the SS modulation cycle. The phase difference of (n) is calculated. Then, a third phase shift amount cor_d that corrects the difference value sub_cnt that is the calculated phase difference is generated. The generated third phase shift amount cor_d is reflected together with the first phase shift amount pll_frac and the second phase shift amount pi_ssd when the output clock signal vco_ck is subjected to spread spectrum modulation. Therefore, the spread spectrum modulation period (SS modulation period) can be adjusted to an integral multiple of the period of the predetermined synchronization signal without resetting the SSCG circuit 90A. In addition, by maintaining the continuity of the SS modulation cycle, it is possible to obtain the SS modulation signal ddsd_org having the output clock signal vco_ck whose phase matches the input clock signal comp_ck (reference clock signal). Therefore, the jitter of the output clock signal vco_ck can be reliably reduced.

  Furthermore, according to the spread spectrum clock generation circuit 90A according to the first embodiment of the present invention, the period error correction circuit 5c (period error correction means) determines the phase difference between the target value of the SS modulation period and the actual value of the SS modulation period. Is calculated. That is, the phase difference between the input clock signal comp_ck, which is the target value of the SS modulation period, and the SS modulation clock puck (n), which is the actual value of the SS modulation period, is calculated. Then, based on the minimum unit of the phase φ that can be selected by the phase selection circuit 6 (phase selection means), a third phase shift amount cor_d for correcting the difference value sub_cnt that is the calculated phase difference is generated. Therefore, by reducing the set value of the phase φ that can be selected by the phase selection circuit 6, it is possible to improve the accuracy of correcting the cyclic error.

  Further, according to the spread spectrum clock generation circuit 90A according to the first embodiment of the present invention, the phase controller 5 (phase control means) includes the first phase shift amount pll_frac, the second phase shift amount pi_ssd, and the third And the phase shift amount cor_d. Then, based on the added result, a phase shift amount Δph when the output clock signal vco_ck is spread spectrum modulated is calculated. Therefore, the phase shift amount Δph can be calculated by a simple calculation.

  As mentioned above, although the Example of this invention was described in detail using drawing, since this Example is only an illustration of this invention, this invention is limited only to the structure of this Example. is not. That is, it is a matter of course that the present invention includes any design change within a range not departing from the gist of the present invention.

DESCRIPTION OF SYMBOLS 1 Phase frequency comparator 2 Charge pump 3 Loop filter 4 Voltage controlled oscillator (voltage controlled oscillation means)
5 Phase controller (phase control means)
5a Δ value addition operation unit 5b Triangular wave generation unit 5c Periodic error correction circuit (periodic error correction means)
5d Phase comparison unit (phase comparison means)
5e Loop filter 5f Correction value control unit 5g Phase shift amount addition unit 5h Phase selection signal generation unit 5i Frequency divider 6 Phase selection circuit (phase selection means)
7 Divider 11 Input Divider 12 Output Divider 90A Spread Spectrum Clock Generation Circuit (SSCG Circuit)

JP 2004-328280 A

Claims (3)

A phase comparison unit that detects a phase difference between a reference input clock signal and a feedback signal, outputs a control voltage corresponding to the phase difference, and generates and outputs an output clock signal having a frequency corresponding to the control voltage. Selecting one of a voltage-controlled oscillating means and a phase obtained by equally dividing one cycle of the clock of the output clock signal into a predetermined number, and generating a phase-shifted clock signal having a rising edge in the selected phase, Phase selection means for sending the phase-shifted clock signal as the feedback signal to the phase comparison means, and a length obtained by changing the period of the phase-shifted clock signal by a predetermined first phase shift amount from the period of the output clock signal As described above, the phase of the rising edge of the phase-shifted clock signal selected by the phase selection unit is determined, and the determined phase is selected. Phase control means for controlling phase selection means, wherein the phase control means generates a second phase shift amount that periodically changes within a predetermined range, and the second phase shift amount is converted into the first phase shift amount. The phase of the rising edge of the phase shift clock signal selected by the phase selection means is determined by adding to the phase shift amount of 1, and the output clock signal is determined by the second phase shift amount that periodically changes. In a spread spectrum clock generation circuit that performs spread spectrum modulation on
The phase control means further detects a phase difference between the target value and the actual measurement value from the target value and the actual measurement value of the spread spectrum modulation period, and corrects the phase difference. A phase error correction means for generating the output clock signal, and when the clock signal is spread spectrum modulated, the third phase shift amount is also reflected to determine the phase shift amount when the output clock signal is spread spectrum modulated A spread spectrum clock generation circuit characterized by:   The period error correction unit is configured to select the third phase shift based on a phase difference between the target value of the spread spectrum modulation period and the actually measured value and a minimum unit of phase that can be selected by the phase selection unit. The spread spectrum clock generation circuit according to claim 1, wherein the spread spectrum clock generation circuit generates a quantity.   The phase control unit adds the first phase shift amount, the second phase shift amount, and the third phase shift amount to perform spread spectrum modulation on the output clock signal. 3. The spread spectrum clock generation circuit according to claim 1, wherein a phase shift amount is calculated.