JP2008090774A - Spread spectrum clock generator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To exchange signals between a device operated by a spread spectrum clock and a device operated by a non-spread spectrum clock synchronously. <P>SOLUTION: The generator comprises a frequency phase comparator 104 for detecting a phase difference between reference clock RCLK and output clock CLKO; a charge pump 103 for generating a charge/discharge signal according to the phase difference; a loop filter 104 for generating a difference signal according to the charge/discharge signal; a spread spectrum modulator 106 for modulating the difference signal to generate a spread spectrum modulation signal; and a clock generator 107 for generating an output clock according to composite signal of the output of the loop filter and the spread spectrum modulation signal. The spread spectrum modulator 106 generates a spread spectrum modulation signal that reverses the sign of the difference between the period of the output clock and the period of the reference clock and successively changes the absolute value of the difference. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a spread spectrum clock generator that generates a clock signal whose period varies by a small amount in order to reduce electromagnetic radiation (EMI).

  In recent years, processing capacity has been improved in electronic devices by increasing the speed of the clock signal of the control device. Along with this, EMI (Electro-Magnetic Interference) due to harmonics of the clock signal also tends to deteriorate.

  On the other hand, regulations regarding EMI noise have become stricter, such as laws or voluntary regulations being established in each country. Representative regulations include VCCI (Japan Voluntary Regulation), FCC (US), CISPR (Europe), and the like.

  As the operating frequency is increased, the signal wavelength is shortened, and the length of the connection circuit or the wiring inside the substrate is approximately the same as the wavelength of the high-frequency signal. As a result, connection portions such as wirings easily function as antennas, and electromagnetic radiation to the surroundings increases rapidly.

  In order to solve such problems, in electronic equipment where electromagnetic radiation is a problem, measures such as reducing the electromagnetic radiation by improving the circuit arrangement and reducing electromagnetic radiation to the surroundings by improving the circuit arrangement, etc. Has been done. Measures are also being taken by using ferrite cores and multilayering of substrates.

  However, such measures have been problematic in that the cost is increased and the physical size of the apparatus is increased.

  In order to solve such a problem, a method using a spread spectrum clock generator (SSCG) using spread spectrum has been proposed (see Patent Document 1). Spread spectrum refers to frequency spreading by minutely changing the operation clock cycle of a semiconductor device. Thereby, electromagnetic wave radiation can be reduced.

  Conventionally, a triangular waveform shown in FIG. 6 has been frequently used as a spectrum modulation signal. FIG. 7 shows a spread spectrum profile when the spectrum modulation signal 409 of FIG. 6 is used. When the spectrum modulation signal 409 has a triangular waveform, a feature is that peaks are formed at both ends of the spectrum.

Therefore, a waveform as shown in FIG. 8 has been proposed as a spectrum modulation signal (see Patent Document 2). Accordingly, the peak shown in FIG. 7 is lowered, and there is an effect that electromagnetic wave radiation is reduced.
JP-A-9-98152 JP-A-7-235862

  However, there is a problem that signals cannot be exchanged while being handled synchronously on the data bus between a device operating with an SSCG clock and a device operating with a non-SSCG clock. .

  FIG. 9 shows a block diagram of a general control circuit using the SSCG clock. The CPU incorporates a clock buffer, handles voltage oscillation from the oscillation element (X'tal) as a clock, and operates with RCLK as a reference clock. Also, RCLK is supplied to the SSCG, and this SSCG outputs a spread spectrum clock CLKO.

  The operation of an application specific integrated circuit (ASIC) is controlled with reference to spread spectrum CLKO. On the other hand, the CPU side needs to operate with a reference clock that is not spread spectrum because accurate time measurement is required. For example, it is for accurately performing time by a clock function or a timer interrupt (not shown). For this reason, the CPU side operates with a reference clock (RCLK) that is not spread spectrum, and the ASIC side operates with a spread spectrum clock.

  In such a configuration, the BUS handshake between the CPU and the ASIC is handled asynchronously. Therefore, it is necessary to provide a buffer (BUFFER) for temporarily storing data in the ASIC. However, since the buffer configuration is provided in the ASIC, there are problems such as a complicated structure and a decrease in the BUS cycle.

  Next, FIG. 10 is a timing chart showing the relationship between the reference clock RCLK and the spread spectrum CLKO.

  This shows a case where the spectrum modulation signal has a triangular waveform and cycle-to-cycle jitter (jitter between adjacent cycles) is tg. As can be seen from the figure, while the output amplitude of the spectrum modulation signal is increasing, the cycle of the output clock CLKO is increased by tg every cycle with respect to the cycle of the reference clock RCLK.

  When the spectrum modulation signal is on the plus side, the cycle of the output clock CLKO is larger than the cycle of the reference clock RCLK, but when it is on the minus side, the cycle of the output clock CLKO is smaller than the cycle of the reference clock RCLK. Usually, the increase / decrease of the cycle of the output clock CLKO is often performed with a certain cycle. (Here, the positive and negative origins are not necessarily defined as 0, and may be increased or decreased based on an arbitrary offset value.) For example, modulation is performed at a period of about 30 KHz with respect to 66.7 MHz CLKO. There is an SSCG device that performs the above (spreading period 30 KHz, spreading frequency width about 1%).

  Next, the phase difference between the reference clock RCLK and the spread spectrum CLKO will be described.

  When attention is paid to the nth clock in the timing chart of FIG. 10, the phase difference between the reference clock RCLK and the spread spectrum CLKO is Σntg. That is, the phase difference between the reference clock and the spread spectrum CLKO becomes a large value because it is the sum of the cycle-to-cycle jitter tg up to the n-th clock, which can be one period or more of the reference clock. Therefore, the phase between CLKO and RCLK is not guaranteed, and the BUS exchange shown in FIG. 9 is handled asynchronously.

  As a result, a buffer is required on the ASIC side, which causes problems such as a complicated structure and a decrease in the BUS cycle.

  The present invention has been made in such a background, and the purpose of the present invention is to provide a method for synchronizing signals between a device operating with a spread spectrum clock and a device operating with a non-spread spectrum clock. An object of the present invention is to provide a spread spectrum clock generator capable of exchanging data.

  A spread spectrum clock generator according to the present invention is a spread spectrum clock generator for generating a spread spectrum output clock based on a reference clock, a frequency phase comparator for detecting a phase difference between the reference clock and the output clock, A charge pump for generating a charge / discharge signal according to the phase difference detected by the frequency phase comparator; a loop filter for generating a difference signal according to the charge / discharge signal; and a spread spectrum modulation signal by modulating the difference signal And a clock generator that generates an output clock according to a combined signal of the output of the loop filter and the spread spectrum modulation signal, the spread spectrum modulator having a period of the output clock And the sign of the difference between the reference clock cycle and the difference And generating a spread spectrum modulated signal the absolute value is sequentially changed.

  Since the spread spectrum modulation signal generated by the spread spectrum modulator is a signal that inverts the sign of the difference between the cycle of the output clock and the cycle of the reference clock and sequentially changes the absolute value of the difference, the cycle of the output clock is The absolute value of the period changes while alternately increasing and decreasing alternately, instead of continuously increasing or decreasing continuously. Therefore, the accumulation of the change in period is reduced.

  The spread spectrum modulation signal is, for example, a signal whose amplitude sign is inverted every one or several clocks of the reference clock and whose absolute value of the amplitude changes periodically.

  A 1 / X divider for dividing the reference clock by X and a 1 / Y divider for dividing the output clock by Y; It may be configured to detect the phase difference of the output of the peripheral. As a result, an output clock that fluctuates in a predetermined cycle is obtained with a period Y / X times as long as the period of the reference clock CLK.

  According to another aspect, the spread spectrum clock generator according to the present invention is a clock generator that generates a clock CLKO having a frequency (Y / X) times from a reference clock by using PLL (Phase Locked Loop) control. And a PLL including a voltage controlled oscillator, wherein the sign of the amplitude is inverted every one or several clocks of the reference clock with respect to the input signal of the voltage controlled oscillator in the previous stage of the voltage controlled oscillator and the absolute amplitude A signal whose value changes periodically is added.

  According to the spread spectrum clock generator of the present invention, as a spread spectrum modulation signal, by using a signal that inverts the sign of the difference between the period of the output clock and the period of the reference clock and sequentially changes the absolute value of the difference. The phase difference between the reference clock and the spread clock can be easily suppressed to 1 clock or less. As a result, it is possible to exchange signals between a device that operates with a spread spectrum clock and a device that operates with a non-spread spectrum clock while maintaining the synchronization.

  Hereinafter, preferred embodiments of the present invention will be described in detail.

  FIG. 1 is a basic configuration diagram of the SSCG circuit of the present embodiment.

  This circuit uses a PLL (Phase Locked Loop) control to generate a clock CLKO having a frequency (Y / X) times that of the reference clock RCLK. For this purpose, a 1 / X frequency divider 101 that divides the reference clock RCLK by a factor of X, a frequency phase comparison that receives the output of the 1 / X frequency divider 101 and the output of a 1 / Y frequency divider 108 described later. , A charge pump 103 that receives the output of the frequency phase comparator 102, a loop filter 104 that receives the output of the charge pump 103, and a voltage adding circuit that adds the output of the loop filter 104 to the output of a symmetric modulator 106 described later. 105, a symmetric modulator 106 that generates a predetermined modulation signal, a voltage controlled oscillator (clock generator) VCO 107 that receives the output of the voltage adding circuit 105 and outputs an output clock CLKO, and outputs the voltage controlled oscillator VCO 107 for Y minutes 1 / Y frequency divider 108 that divides the frequency into one.

  The frequency phase comparator 102 detects the phase difference between the output of the 1 / X frequency divider 101 and the output of the 1 / Y frequency divider 108 and outputs a signal for controlling the charge pump 103 according to the phase difference. .

  The charge pump 103 outputs a signal for charging and discharging the loop filter 104 according to the phase difference, and a voltage difference 110 corresponding to the phase difference is generated at one end of the loop filter 104.

  In the case of simple PLL control, that is, when spectrum spread is not performed, this voltage difference 110 is applied to the VCO 107, and a clock with a certain period is generated accordingly.

  On the other hand, in the SSCG circuit, the symmetric modulator 106 outputs a spectrum modulation signal 109 that fluctuates in a predetermined cycle with a small amplitude, and the voltage addition circuit 105 adds the spectrum modulation signal 109 to the difference voltage 110 and applies it to the VCO 107. . As a result, the cycle of the generated clock CLKO fluctuates in a predetermined cycle, centering on a cycle Y / X times the cycle of the reference clock CLK.

  The fluctuation rate of the period and the fluctuation cycle are determined by the spectrum modulation signal generated by the modulator. Further, since the response time of the PLL circuit is set sufficiently longer than the period of the spectrum modulation signal, the fluctuation value of the spectrum modulation signal 109 is not phase locked by the PLL circuit.

  In particular, in this embodiment, the symmetric modulator 106 outputs a spectrum symmetric modulation signal 109 whose sign is inverted every clock with positive and negative symmetric amplitudes and whose amplitude absolute value changes periodically, and voltage addition is performed. The circuit 105 adds the spectrum modulation signal 109 to the differential voltage 110 and applies it to the VCO 107. As a result, the period of the generated clock CLKO is spread alternately in positive and negative directions every clock, with the period Y / X times the period of the reference clock RCLK being the center.

  2A and 2B show profiles of the spectrum symmetric modulation signal 109 output from the spectrum symmetric modulator 106. FIG. FIG. 2A shows a spectrum symmetrical modulation signal 109 when the waveform corresponding to FIG. 6 is alternately modulated in the + direction or the − direction every clock. Similarly, FIG. 2B shows a spectrum symmetrical modulation signal 109 when the waveform corresponding to FIG. 7 is alternately modulated in the + direction or the − direction every clock. The spectrum symmetric modulation signal 109 may be a digital counter generating circuit or an analog circuit. The spectrum symmetric modulation signal 109 is added by the adder 105, and the voltage controlled oscillator VCO 107 outputs a spread spectrum clock CLKO whose period alternately changes in the period extending direction and the period reducing direction for each clock. Furthermore, when using a spread spectrum clock modulation signal that alternately modulates positive or negative at every clock, the phase difference of the output clock from the reference clock can be expressed in ntg, so that the phase difference can be set easily. Is possible.

  FIG. 3 is a timing chart showing the relationship between the reference clock RCLK and the output clock CLKO input to the circuit of FIG.

In FIG. 3, tg is cycle-to-cycle jitter (cycle-to-cycle jitter) representing the period difference between the current clock and the next clock. The output clock CLKO is a clock obtained by spectrum spreading in which the cycle extension direction and the cycle reduction direction change every clock. In the following, the phase difference of the corresponding cycle for each cycle of the reference clock RCLK will be considered.
(1) Cycle No. 0 is a phase difference of 0 with respect to RCLK of CLKO.
(2) No. At 1, the cycle jitter (+ tg) is added and the phase difference with respect to RCLK is “0”.
(3) No. In 2, the cycle jitter (-tg) is added and the phase difference with respect to RCLK is "tg".
(4) No. 3, the cycle jitter (+2 tg) is added and the phase difference with respect to RCLK is “0”.
(5) No. 4, the cycle jitter (-2tg) is added and the phase difference with respect to RCLK is "2tg".
(6) No. 5, the cycle jitter (+3 tg) is added and the phase difference with respect to RCLK is “0”.
(7) No. At 6, cycle jitter (−3 tg) is added and the phase difference with respect to RCLK is “3 tg”.
(8) No. A cycle jitter (-ntg) is added at 2n, and the phase difference with respect to RCLK is ntg.

  As the phase difference with respect to the reference clock, “0” and “ntg” (n is a natural number with an upper limit) appear alternately. If the condition (ntg <reference clock period) is satisfied, the phase difference between the reference clock RCLK and the output clock CLKO (ie, the spread spectrum clock) is 1 clock or less, and the phases of CLKO and RCLK are the same. Guaranteed. As a result, in the case of the block configuration shown in FIG. 9, the BUS handshake between the CPU and the ASIC can be handled synchronously by setting ntg <1 clock. In the case of the conventional spread spectrum clock generator, the phase difference from the reference clock is Σntg, whereas when the cycle change direction is changed every clock, it is ntg. It is possible to reduce it to a very low level.

For example, if we focus on the 50th clock with tg = 100 psec at a clock with a cycle of 20 nsec
While Σntg = 127.5 nsec,
ntg = 5nsec
It becomes. This means that the accumulation of jitter is greatly reduced by the present invention.

  In addition, since the BUS handshake between the CPU and the ASIC can be handled synchronously in the block configuration shown in FIG. 9, it is not necessary to provide a buffer. Along with this, there is no decrease in the BUS cycle due to the buffer.

  In actual timing design, it is necessary to consider the CPU data setup time and hold time in addition to the condition of ntg <1 clock. Hereinafter, conditions for actually performing timing design between the CPU and the ASIC will be described with reference to FIGS. 4 and 5. FIG.

FIG. 4 is a timing chart during CPU write. It is assumed that the CPU operates with RCLK that is not spread spectrum, and the ASIC operates with CLKO that is spread spectrum. Therefore, the write strobe point for writing data from the CPU to the ASIC is governed by the operation clock on the ASIC side and becomes the rising edge 41 of CLKO. Also, considering the known setup time (setup) and hold time (hold) for the ASIC to receive data,
hold <t / 2-ntg + twr + twdf (i)
setup <(t + ntg) / 2− (twdr−ntg / 2) (ii)
It is necessary to satisfy. Here, the meaning of each variable is as follows.
hold: Data hold time required by an external device operating in CLKO (here, ASIC) setup: Data setup time required by an external device operating in CLKO (here, ASIC) trdr: CPU data from the fall of RCLK Twrf: the time from the falling edge of RCLK to the falling edge of the CPU write signal WR twrf: the data retention time of the CPU from the rising edge of the write signal WR

FIG. 5 is a timing chart at the time of CPU reading. As in the case of FIG. 4, it is assumed that the CPU operates with RCLK that is not spread spectrum, and the ASIC operates with CLKO that is spread spectrum. Therefore, the read strobe point for fetching data from the ASIC to the CPU is controlled by the operation clock on the CPU side and becomes the point 51. Also, considering the known setup time (setup) and hold time (hold) for the CPU to receive data,
hold <trr + trdf ... (iii)
setup <t-trdr-ntg / 2 (iv)
It is necessary to satisfy. Here, the meaning of each variable is as follows.
hold: Data hold time required by the CPU setup: Data setup time required by the CPU trdr: Time from the falling edge of CLKO until the data is output by the external device (here, ASIC) operating at CLKO trr: RCLK Time trdr from the fall of the read signal RD to the rise of the CPU read signal RD: the data retention time of the CPU from the rise of the read signal RD

  Thus, it is necessary to design a circuit in consideration of the setup time and hold time of each device.

  The preferred embodiments of the present invention have been described above, but various modifications and changes other than those mentioned above can be made. For example, the spread spectrum modulation signal is a signal whose sign is alternately inverted every clock of the reference clock, but may be a signal whose sign is alternately inverted every several clocks of the reference clock.

1 is a basic configuration diagram of an SSCG circuit according to an embodiment of the present invention. It is a figure which shows two examples (a) and (b) of the profile of the spectrum symmetrical modulation signal output from the spectrum symmetrical modulator shown in FIG. FIG. 2 is a timing diagram showing a relationship between a reference clock RCLK and an output clock CLKO input to the circuit of FIG. 1. It is a timing chart at the time of CPU write in an embodiment of the invention. 6 is a timing chart at the time of CPU reading in the embodiment of the present invention. It is a figure which shows the triangular waveform which is the conventional spectrum modulation signal. It is a figure which shows the profile of a spread spectrum when the spectrum modulation signal of FIG. 6 is used. It is a figure which shows the other conventional spectrum modulation signal. It is a block diagram of a general control circuit using an SSCG clock. FIG. 6 is a timing diagram showing a relationship between a basic quasi-clock RCLK and a spread spectrum CLKO.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 ... 1 / X frequency divider 102 ... Frequency phase comparator 103 ... Charge pump 104 ... Loop filter 105 ... Voltage addition circuit 106 ... Symmetric modulator 107 ... Voltage controlled oscillator (VCO)
108 ... 1 / Y frequency divider 109 ... spectrum modulation signal 110 ... voltage difference

Claims (5)

A spread spectrum clock generator for generating a spread spectrum output clock based on a reference clock,
A frequency phase comparator that detects the phase difference between the reference clock and the output clock;
A charge pump for generating a charge / discharge signal according to the phase difference detected by the frequency phase comparator;
A loop filter that generates a difference signal according to the charge / discharge signal;
A spread spectrum modulator that modulates the difference signal to generate a spread spectrum modulated signal;
A clock generator that generates an output clock according to a combined signal of the output of the loop filter and the spread spectrum modulation signal;
The spread spectrum modulator generates a spread spectrum modulation signal that inverts the sign of a difference between an output clock period and a reference clock period and sequentially changes an absolute value of the difference. apparatus.   2. The spread spectrum clock generator according to claim 1, wherein the spread spectrum modulation signal is a signal whose amplitude sign is inverted every one or several clocks of the reference clock and whose absolute value of the amplitude changes periodically.   A 1 / X divider for dividing the reference clock by X and a 1 / Y divider for dividing the output clock by Y; 2. The spread spectrum clock generator according to claim 1, wherein the phase difference of the output of the peripheral is detected.   2. The spread spectrum clock generator according to claim 1, wherein the phase difference detected by the frequency phase comparator is equal to or less than one period of the reference clock. A clock generator that generates a clock CLKO having a frequency of (Y / X) times from a reference clock by using PLL control,
A PLL including a voltage controlled oscillator, wherein the sign of the amplitude is inverted every one or several clocks of the reference clock and the absolute value of the amplitude is a period with respect to the input signal of the voltage controlled oscillator in the previous stage of the voltage controlled oscillator Spread-spectrum clock generator characterized by adding a signal that changes periodically.

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