KR101465881B1 - Digital phase locked loop apparatus - Google Patents

Abstract

The present invention discloses a digital phase locked loop device. According to the present invention, a digital controlled oscillator for outputting a signal having a frequency and a phase corresponding to a control code; A frequency divider dividing a signal output from the digitally controlled oscillator and outputting a feedback clock having a predetermined magnification of a reference clock; A sampler for sampling the reference clock with the feedback clock and outputting a digital code; And a digital filter for comparing a digital code previously output by the sampler with a digital code output at present and outputting a control code for adjusting a phase of a signal output from the digital controlled oscillator .

Description

[0001] Digital phase locked loop apparatus [0002]

The present invention relates to a digital phase locked loop apparatus, and more particularly, to a digital phase locked loop apparatus capable of fixing a phase without a time-to-digital converter.

A phase locked loop is a block that produces a clock on the system, and the performance of the system is determined by the performance of the phase locked loop.

The most commonly used phase-locked loop is analog-based.

The phase locked loop, which is generally used in analog, consists of a phase detector that compares the reference clock with the generated clock, a charge pump (CP) that converts the voltage generated by the phase detector into a current, a lowpass filter A low pass filter (LPF), a voltage controlled oscillator (VCO) for generating a clock, and a frequency divider for dividing the generated clock

In this analog phase locked loop, the phase detector detects the phase difference between the clock generated by the VCO and the reference clock received from the outside, and outputs a pulse width equal to the difference of the phases generated at present.

The CP supplies the LPF with the current as much as the pulse width output from the phase detector, repeats this process and adjusts the phase difference.

Since this phase-locked loop has a second-order low-pass filter characteristic, it must stabilize the loop through a cap (capacitor) and an LPF made of resistors.

At this time, since the size of the cap used for the LPF is large, the area is disadvantageous. To solve this problem, a digital phase locked loop has been developed. This digital phase locked loop digitally implements the function of each block implemented in the analog method.

The phase detector is replaced by a time-to-digital converter (TDC), the CP and LPF are replaced by digital filters, and the VCO is replaced by a digitally controlled oscillator (DCO) Respectively.

However, although the disadvantage of the area can be solved through the digital phase locked loop, a quantization error occurs in the TDC, and the performance of the entire PLL is deteriorated.

In order to solve this problem, a digital phase locked loop using a Bang-bang phase detector (BBPD), which can only obtain information on whether the phase difference is fast or slow, has been proposed. In the BBPD, only information that the phase is fast or slow is known. Therefore, even if the phase of the clock generated by the DCO is the same as the phase of the reference clock, information that is fast or slow is always generated. State, the jitter of the output clock is increased.

Also, since BBPD is ideal in situations where there is no quantization error, a method has been devised to prevent jitter of the output clock from increasing through digital processing in the digital filter.

However, since information obtained from the phase detector is limited to information that the phase of the generated clock is faster or slower than the reference clock, the operation in the digital filter becomes complicated, which causes a disadvantage of increasing the size of the filter. In addition, since it is necessary to perform calculation using only limited information, there is a limit to reducing the jitter of the clock.

In order to solve the above problems, the present invention proposes a digital phase locked loop capable of eliminating a quantization error due to the limitation of TDC resolution and solving the jitter increase problem.

According to a preferred embodiment of the present invention, there is provided a digital phase locked loop apparatus comprising: a digitally controlled oscillator for outputting a signal having a frequency and a phase corresponding to a control code; A frequency divider dividing a signal output from the digitally controlled oscillator and outputting a feedback clock having a predetermined magnification of a reference clock; A sampler for sampling the reference clock with the feedback clock and outputting a digital code; And a digital filter for comparing a digital code previously output by the sampler with a digital code output at present and outputting a control code for adjusting a phase of a signal output from the digital controlled oscillator .

The feedback clock may have k times frequency of the reference clock, where k is 2 or more.

The feedback clock may have a frequency four times that of the reference clock.

Wherein the digital filter comprises: a storage unit for storing a digital code previously output by the sampler; A comparison unit comparing the previously output digital code with the currently output digital code and outputting a control signal; And a counter unit for changing a control code input to the digital controlled oscillator according to a control signal outputted by the comparing unit.

The control signal may include a control code change signal which is an enable signal for changing the control code and an up-down signal for increasing or decreasing the control code.

The comparing unit may compare the previously output digital code with the currently output digital code to determine whether the phase of the signal output from the digital controlled oscillator is fast or slow.

And a frequency detector for detecting a frequency by receiving a signal output from the frequency divider and outputting a control signal for fixing a frequency of a signal output from the digital controlled oscillator to the digital filter.

After the frequency of the signal output from the digitally controlled oscillator is fixed by the frequency detector, the frequency divider may output a feedback clock having a predetermined magnification of the reference clock to the sampler.

According to another aspect of the present invention, there is provided a digital phase locked loop apparatus comprising: a digitally controlled oscillator outputting a signal having a frequency and a phase corresponding to a control code; A frequency divider for dividing the signal output from the digitally controlled oscillator at a preset magnification and outputting a frequency division signal; A frequency detector for detecting a frequency of the frequency division signal and outputting a control signal for fixing a frequency of a signal output from the digital controlled oscillator; A digital filter for outputting a control code having a most significant bit of the control code adjusted by the control signal to the digital controlled oscillator; And a sampler for sampling a reference clock with a frequency dividing signal input from the frequency divider and outputting a digital code when the frequency of the signal output from the digital controlled oscillator is fixed by the frequency detector, There is provided a digital phase locked loop device for comparing a digital code previously output by a sampler with a currently output digital code and outputting a control code for adjusting a phase of a signal output from the digital controlled oscillator.

According to the present invention, the TDC is not used because the phase of the output signal is adjusted by using the sampled result and the tendency of the phase difference change after storing the phase detection result with the divided clock as the reference clock. It is possible to eliminate the quantization error as well as to fix the phase faster than using the BBPD and to reduce the complexity of the filter.

1 is a block diagram illustrating a structure of a digital phase locked loop according to a preferred embodiment of the present invention.
Figure 2 is a timing diagram for sampling a reference clock in accordance with the present invention as a feedback clock;
3 is a block diagram of a digital filter according to a preferred embodiment of the present invention;
4 is a diagram showing a trend of a digital code outputted by a sampler according to the present invention and an output signal of the comparator according to the trend.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the invention is not intended to be limited to the particular embodiments, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for like elements in describing each drawing.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In order to facilitate a thorough understanding of the present invention, the same reference numerals are used for the same means regardless of the number of the drawings.

The present invention discloses a digital phase locked loop based on a method of detecting a phase difference, storing a detection result, and comparing the detected result with a previous detection result. The phase locked loop according to the present invention is implemented in a digital manner and is insensitive to semiconductor processes, operating voltages, and operating temperatures, and has the advantage of reducing the complexity of the digital filter while eliminating quantization errors occurring in conventional methods.

1 is a block diagram showing a structure of a digital phase locked loop according to a preferred embodiment of the present invention.

A digital controlled oscillator (DCO) 100, a divider 102, a frequency detector 104, a digital filter 106 and a sampler 108, as shown in FIG. . ≪ / RTI >

The digital controlled oscillator 100 outputs a signal having a predetermined frequency and phase (hereinafter, referred to as 'DCO signal') according to the operation of the phase locked loop.

The DCO signal of the digitally controlled oscillator 100 is applied to the frequency divider 102 and the frequency divider 102 divides the DCO signal by a predetermined factor (e.g., k times, where k is two or more) do.

According to the present invention, the signal output in the frequency divider 102 is applied to the frequency detector 104 for frequency locking.

The frequency detector 104 according to the present invention outputs a control signal for controlling the most significant bit (MSB) allocated for frequency fixing among the control codes input to the digital controlled oscillator 100 by the digital filter 106. [

For this purpose, the frequency detector 104 receives a reference clock and a signal divided into a frequency divider 102. The frequency detector 104 detects a rising edge of a frequency division signal included in one cycle of the reference clock, ) And the number of the down edges to adjust the most significant bit.

For example, if the target frequency of the frequency dividing signal is four times the reference clock, if the number of upward edges and down edges included in one cycle of the reference clock is 8, And outputs a control signal for fixing the most significant bit input to the digitally controlled oscillator 100.

On the other hand, when the number of the upward edges and the down edges included in one period of the reference clock is less than 8, the frequency detector 104 adjusts the most significant bit to adjust the frequency of the DCO signal of the digital controlled oscillator 100 And when it exceeds 8, the most significant bit is adjusted to decrease the frequency of the DCO signal of the digitally controlled oscillator 100. [

The adjustment of the most significant bit according to the present invention can be performed by a conventional binary search technique or a sequential search technique, which is well known to those skilled in the art, and thus a detailed description thereof will be omitted.

When the DCO signal is fixed to a desired frequency through the above process, the phase fixing process is performed through the sampler 108. [

Hereinafter, for convenience of explanation, it will be explained that the frequency of the DCO signal is fixed to four times the reference clock, but it should be understood by those skilled in the art that the present invention is not limited thereto.

A frequency division signal having a frequency four times the reference clock frequency is defined as a feedback clock and a feedback clock is applied to the sampler 108. [

The sampler 108 according to the present invention applies a digital code obtained by sampling the reference clock to the feedback clock to the digital filter 106 and the digital filter 106 is controlled using the digital code input at the sampler 108 Code to generate a control code, through which the digitally controlled oscillator 100 outputs a phase-adjusted DCO signal.

For example, when the control code is composed of 10 bits, 5 bits corresponding to the most significant bit are used for frequency fixing as described above, and the remaining 5 least significant bits can be used for phase locking.

2, the sampler 108 according to the present invention samples a reference clock using a feedback clock, and outputs an 8-bit digital code when the feedback clock is four times the reference clock, as described above.

The sampler 108 outputs a digital code corresponding to a locked state using a sampling clock Sam_clk having the same frequency as the reference clock and having a period of a quarter of the feedback clock.

The digital filter 106 changes the control code output to the digitally controlled oscillator 100 using the digital code output from the sampler 108. [ In more detail, the digital filter 106 changes the binary code or the like using the digital code output from the sampler 108 and changes the least significant bit of the control code to output it.

3 is a block diagram of a digital filter according to a preferred embodiment of the present invention.

As shown in FIG. 3, the digital filter according to the present invention may include a storage unit 300, a comparison unit 302, and a counter unit 304.

The storage unit 300 stores the (n-1) -th digital code rsam (n-1) previously output from the sampler 108, And outputs the digital code rsam (n) to the comparison unit 302. [

The comparing unit 302 compares rsam (n-1) and rsam (n) to compare whether the current DCO signal is earlier or slower than the previous DCO signal. That is, the comparator 302 determines the tendency of the phase difference change of the DCO signal using the digital code.

4 is a diagram showing a trend of rsam (n) and an output signal of the comparator according to the trend.

In Fig. 4, rsam (n-1) is denoted by rsam1 and rsam (n) is denoted by rsam.

Referring to FIG. 4, the comparison unit 302 determines that the phase of the currently output DCO signal is faster than the previous one, when rsam (n) is 00011110 and rsam (n-1) is 00111100.

If it is determined that the phase of the DCO signal is fast, the comparator 302 outputs a control signal to the counter 304 to control the phase of the DCO signal slowly.

The control signal output from the comparison unit 302 may include a control code change signal (Con-adder) and an up-down signal (UDT). Here, the control code change signal may be defined as an enable signal for changing the control code, and the up-down signal may be defined as a value for the counter unit 304 to increase or decrease the control code.

As described above, when the phase of the DCO signal is fast, the control code change signal has a value of 1, and the up-down signal can also have a value of 1.

For example, when a binary search or a sequential search is performed, the up-down signal 1 may be a value such that a control code having a larger value than the previous control code is output.

However, this is only an example, and the change of the up-down signal and the control code may be variously changed.

Meanwhile, the comparator 302 determines that the phase of the currently output DCO signal is slower than before when rsam (n) is 00011110 and rsam (n-1) is 00001111.

If it is determined that the phase of the DCO signal is slow, the comparator 302 outputs a control signal to the counter 304 to control the phase of the DCO signal quickly.

Here, when the phase of the DCO signal is slow, the control code change signal has a value of 1, and the up-down signal can be output as 0 (or -1).

Finally, if the previously stored digital code matches the current digital code, the comparator 302 determines that the phase is fixed and outputs a control signal for phase locking.

When the phase is fixed, the comparator 302 can output the control code change signal as zero.

That is, when the control code change signal is outputted as 0, the counter unit 304 fixes the previously output control code and outputs it to the digital controlled oscillator 100.

According to the present invention, since the frequency is fixed, the phase is fixed by determining whether the phase is fast or slow through the sampler 108, so that the time-to-digital converter is not used, and further, the quantization by the time- No error will occur.

It will be apparent to those skilled in the relevant art that various modifications, additions and substitutions are possible, without departing from the spirit and scope of the invention as defined by the appended claims. The appended claims are to be considered as falling within the scope of the following claims.

Claims (10)

A digital phase locked loop device,
A digital controlled oscillator for outputting a signal having a frequency and a phase corresponding to the control code;
A frequency divider dividing a signal output from the digitally controlled oscillator and outputting a feedback clock having a predetermined magnification of a reference clock;
A sampler for sampling the reference clock with the feedback clock and outputting a digital code; And
And a digital filter for comparing a digital code previously output by the sampler with a digital code output at present and outputting a control code for adjusting a phase of a signal output from the digital controlled oscillator. The method according to claim 1,
Wherein the feedback clock has a k-th frequency of the reference clock and k is at least two. 3. The method of claim 2,
Wherein the feedback clock has a quadruple frequency of the reference clock. The method according to claim 1,
The digital filter includes:
A storage unit for storing the digital code previously output by the sampler;
A comparison unit comparing the previously output digital code with the currently output digital code and outputting a control signal; And
And a counter section for changing a control code inputted to the digital controlled oscillator according to a control signal outputted by the comparing section. 5. The method of claim 4,
Wherein the control signal comprises a control code change signal which is an enable signal for changing the control code and an up-down signal for increasing or decreasing the control code. 5. The method of claim 4,
Wherein the comparison unit compares the previously output digital code with the currently output digital code to determine whether the phase of the signal output from the digital controlled oscillator is fast or slow. The method according to claim 1,
And a frequency detector for receiving a signal output from the frequency divider to detect a frequency and outputting a control signal for fixing a frequency of a signal output from the digital controlled oscillator to the digital filter. 8. The method of claim 7,
Wherein the frequency divider outputs a feedback clock having a predetermined magnification of the reference clock to the sampler after the frequency of the signal output from the digitally controlled oscillator is fixed by the frequency detector. A digital phase locked loop device,
A digital controlled oscillator for outputting a signal having a frequency and a phase corresponding to the control code;
A frequency divider for dividing the signal output from the digitally controlled oscillator at a preset magnification and outputting a frequency division signal;
A frequency detector for detecting a frequency of the frequency division signal and outputting a control signal for fixing a frequency of a signal output from the digital controlled oscillator;
A digital filter for outputting a control code having a most significant bit of the control code adjusted by the control signal to the digital controlled oscillator; And
And a sampler for sampling a reference clock with a frequency dividing signal input from the frequency divider and outputting a digital code when the frequency of the signal output from the digitally controlled oscillator is fixed by the frequency detector,
Wherein the digital filter compares a digital code previously output by the sampler with a digital code currently output and outputs a control code for adjusting a phase of a signal output from the digital controlled oscillator. 10. The method of claim 9,
Wherein the frequency dividing signal input to the sampler is a feedback clock having a frequency of a predetermined magnification of the reference clock and the sampler samples the reference clock with the feedback clock to output the digital code.

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