CN115333532A

CN115333532A - Full digital phase-locked loop and correction method thereof

Info

Publication number: CN115333532A
Application number: CN202110514804.3A
Authority: CN
Inventors: 杨育哲; 陈家源
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2021-05-10
Filing date: 2021-05-10
Publication date: 2022-11-11

Abstract

The invention provides an all-digital phase-locked loop and a calibration method thereof, wherein the all-digital phase-locked loop comprises a digital control oscillator, a phase detector and a calibration circuit coupled between the digital control oscillator and the phase detector. The digital controlled oscillator generates a clock signal according to a frequency control signal, and the phase detector generates a phase difference value according to a reference signal and the clock signal. In particular, after the adpll is locked for a period of time, the frequency control signal can be fixed to a locking value obtained when the adpll is locked, and the correction circuit can adjust the current of at least one current source in the dco according to the phase difference value.

Description

Full digital phase-locked loop and correction method thereof

Technical Field

The present invention relates to an all-digital phase-locked loop, and more particularly, to an all-digital phase-locked loop and a calibration method thereof.

Background

In the adpll, a digitally controlled oscillator is required, and the digitally controlled oscillator significantly affects the performance of the adpll, and especially the phase noise of the digitally controlled oscillator itself is often the most important performance index for the designer. In order to optimize the overall performance of the adpll, a novel adpll and related calibration method are needed to optimize the circuit architecture for the phase noise of the dco.

Disclosure of Invention

An objective of the present invention is to provide an all-digital phase-locked loop (ADPLL) and a calibration method thereof, so as to optimize a circuit architecture for phase noise of a Digitally Controlled Oscillator (DCO) under the condition of no side effect or less side effect, thereby improving the overall performance of the ADPLL.

At least one embodiment of the present invention provides an all-digital phase-locked loop, wherein the all-digital phase-locked loop may include a numerically controlled oscillator, a phase detector, and a calibration circuit coupled between the numerically controlled oscillator and the phase detector. The digital controlled oscillator is used for generating a clock signal according to a frequency control signal, and the phase detector is used for generating a phase difference value according to a reference signal and the clock signal. In particular, after the adpll is locked for a period of time, the frequency control signal is fixed to a locked value obtained when the adpll is locked, and the correction circuit adjusts the current of at least one current source in the dco according to the phase difference value.

At least one embodiment of the present invention provides a calibration method for an all-digital phase-locked loop, wherein the calibration method comprises: locking for a period of time by using the all-digital phase-locked loop so as to make a frequency control signal of a digital control oscillator of the all-digital phase-locked loop converge to a locking value; fixing the frequency control signal to the locking value to enable the digital control oscillator to generate a clock signal according to the locking value; generating a phase difference value by using a phase detector of the all-digital phase-locked loop according to a reference signal and the clock signal; and adjusting the current of at least one current source in the numerically controlled oscillator according to the phase difference value by using a correction circuit of the all-digital phase-locked loop.

Embodiments of the present invention provide an all-digital phase-locked loop that can utilize a correction circuit therein to calculate a numerically controlled oscillator, thereby gradually finding a bias current that minimizes phase noise. In addition, compared with the related art, the embodiment of the invention does not greatly increase the additional cost. Therefore, the invention can optimize the circuit architecture aiming at the phase noise of the digital control oscillator under the condition of no side effect or less side effect, thereby improving the overall efficiency of the all-digital phase-locked loop.

Drawings

Fig. 1 is a schematic diagram of an all-digital phase-locked loop 10 according to an embodiment of the present invention.

Fig. 2 is a schematic diagram of the adpll 10 according to an embodiment of the invention during calibration.

Fig. 3 is a diagram of a digital signal processing circuit according to an embodiment of the invention.

Fig. 4 is a flowchart illustrating a calibration method of an adpll according to an embodiment of the invention.

FIG. 5 is an example of the calibration method shown in FIG. 4 according to an embodiment of the present invention.

Detailed Description

Fig. 1 is a schematic diagram of an all-digital phase-locked loop (ADPLL) 10 for locking according to an embodiment of the invention, and fig. 2 is a schematic diagram of the ADPLL 10 for calibration according to an embodiment of the invention. As shown in fig. 1 and 2, the adpll 20 can include a Digitally Controlled Oscillator (DCO) 100, a phase detector, a filter 110 (e.g., a Low Pass Filter (LPF)), and a calibration circuit 120. For simplicity, in fig. 1 and 2, the numerically controlled oscillator 100 may be illustrated with a circular pattern depicted with a sine wave, while the filter 110 may be illustrated with a block depicted with a low-pass frequency response waveform.

As shown in FIG. 1, when the ADPLL 10 is locked, a signal for controlling the current of at least one current source, such as a bias current source, of the numerically controlled oscillator 100 may be temporarily fixed at an initial value DCOI _INITIAL So that the current of the bias current source is fixed at the initial current while the control path from the correction circuit 120 to the digitally controlled oscillator 100 is disabled. Take the time point k as an example (e.g. the kth period of the reference signal FREF)Where k is a positive integer), the numerically controlled oscillator 100 may control the frequency according to a frequency control signal (e.g., a value d [ k ]]) A clock signal CKV is generated, wherein the frequency control signal comes from the filter 110 when the adpll 10 is locked. In addition, the phase detector can generate a phase difference value according to the reference signal FREF and the clock signal CKV

And filter 110 may compare the phase difference values

Filtering is performed to generate the frequency control signal.

In this embodiment, the phase detector can calculate the frequency ratio between the frequency of the reference signal FREF and the frequency of the clock signal CKV, and compare the frequency ratio with the reference ratio FCW _ F to generate the phase difference value. For example, the phase detector may include a counter 131, a time-to-digital converter (TDC) 132, and a plurality of calculating units 133 and 134 (shown as circles with a plus sign therein for simplicity), wherein the counter 131 may calculate the integer portion of the frequency ratio

(e.g., by detecting several cycles of the clock signal CKV within one cycle of the reference signal FREF), the time-to-digital converter 132 calculates the fractional part of the frequency ratio

(e.g., according to the time difference Δ t between the rising edge of the reference signal FREF and the rising edge of the clock signal CKV _r And a time difference Δ t between a rising edge of the reference signal FREF and a falling edge of the clock signal CKV _f Known by calculation); in addition, the calculation unit 133 may scale the frequency such as

Accumulating with the period of the reference signal FREF to generate an accumulationAs a result, the

The accumulator 140 (labeled as "Σ" in the figure for simplicity) may also accumulate the reference ratio FCW _ F with the period of the reference signal FREF to generate an accumulation result

Wherein the calculation unit 134 may calculate the accumulation result

And

difference between them to produce a phase difference value

But the invention is not limited thereto.

Referring next to fig. 2, assuming that the adpll 10 reaches a steady state (e.g., the variation of the frequency control signal over time is less than a predetermined threshold) after locking for a period of time (e.g., the kth period of the reference signal FREF), the adpll can be turned off, and the frequency control signal can be fixed to a locking value such as d k obtained when the adpll 10 locks (particularly, reaches the steady state)]. Therefore, the numerically controlled oscillator will be based on this fixed lock value d k]Generates the clock signal CKV, and the calibration circuit 120 will be based on the phase difference value under this condition

The current of the bias current source in the digitally controlled oscillator 100 is adjusted. As shown in fig. 2, the control path from the calibration circuit 120 to the digitally controlled oscillator 100 is now enabled (enabled), wherein the signal used to control the current of the bias current source of the digitally controlled oscillator 100 is no longer fixed at the initial value DCOI _INITIAL But rather by the N-bit control signal DCOISW provided by the correction circuit. For example, the calibration circuit 120 can be based on the phase difference value

The control signal DCOISW is generated to adjust the current of the bias current source of the dco 100 by switching the control signal DCOISW. Since the remaining circuits (e.g., the phase detector and accumulator 140) operate in the same manner as the embodiment of fig. 1, they are not repeated herein.

In this embodiment, the calibration circuit 120 can calibrate the phase difference value

Performing a calculation to obtain an index value (e.g.

May be used to represent the ith index value obtained during the calibration process, where i is a positive integer), and the current of the bias current source of the dco 100 (e.g., the switchable current ISW) is adjusted to minimize the index value (e.g., find the value of the switchable current ISW that minimizes the index value), where the index value corresponds to the phase noise of the dco. As shown in fig. 2, the correction circuit 120 may include a Digital Signal Processing (DSP) circuit 121 and a finite state machine (finite state machine) 122, wherein the finite state machine 122 is coupled to the DSP circuit 121. Specifically, the digital signal processing circuit 121 may compare the phase difference value

The calculation is performed to obtain the index value, and then the finite state machine 122 can adjust the switchable current ISW according to the change of the index value to minimize the index value. For example, the calibration circuit 120 (e.g., the finite state machine 122 therein) may sequentially switch the value of the switchable current ISW to a plurality of candidate current values to sequentially obtain corresponding index values, and select a candidate current value corresponding to the smallest index value from the candidate current values as the final current value according to the index values. As another example of the above-mentioned,the calibration circuit 120 (e.g., the finite state machine 122 therein) gradually approaches the candidate current value corresponding to the minimum target value through a binary search for being used as the final current value. After the calibration is completed, the control path from the calibration circuit 120 to the dco 100 may be disabled again, and the signal path from the filter 110 to the dco 100 may be enabled again, so that the adpll 10 continues to lock, wherein the phase noise of the dco 100 is reduced by the current adjustment mechanism, thereby improving the overall performance of the adpll 10.

Since the adpll 10 has locked for a period of time and reached a steady state before the correction is made, the control signal is fixed at the frequency at the locked value d k]In this case, the frequency of the clock signal CKV is substantially equal to the target frequency (e.g., the frequency FCW _ F of the reference clock). In practice, the frequency of CKV varies around the target frequency (e.g., varies up and down with the target frequency as an average) because the dco 100 itself has phase noise. Similarly, the phase difference values at different time points (e.g., at k, k +1, k +2, \ 8230; and k + n periods of the reference frequency, respectively)

Where n is a positive integer) is varied in practice around the accumulated result of the reference ratio FCW _ F at these time points, respectively (e.g. respectively

Up and down the mean). To produce the index value such as

The digital signal processing circuit 121 may accumulate the absolute value of the phase difference value for a period of time to generate the index numberThe value is obtained. For example, the DSP 121 may compare the phase difference values at k, k +1, k +2, 823030A, and k + n cycles of the reference frequency, respectively

Is added up to obtain

(e.g. in the case of

). As shown in FIG. 3, the DSP 121 implementing the above calculation method may include an absolute value calculation circuit 310 (denoted as "absolute") for simplicity) for sequentially taking absolute values of the phase difference values at each time point, and an accumulator 320 coupled to the absolute value calculation circuit 310 for summing the absolute values to generate the index value such as

Fig. 4 is a flowchart illustrating a calibration method of an all-digital phase-locked loop according to an embodiment of the invention, wherein the calibration method can be applied to the all-digital phase-locked loop 10. In addition, one or more steps may be added, modified or deleted from the flowchart shown in fig. 4 as long as the overall result is not obstructed, and the steps do not necessarily have to be completely executed in the order shown in fig. 4.

In step 410, the adpll 10 can lock for a period of time such that the frequency control signal of the dco 100 of the adpll 20 converges to a locked value (e.g., d [ k ] shown in fig. 1 and 2).

In step 420, the frequency control signal may be fixed to the lock value for the dco 100 to generate a clock signal (e.g., CKV shown in fig. 2) according to the lock value.

In step 430, the phase detector (e.g., the counter 131, the time-to-digital converter 132, and the calculating

units

133 and 134 shown in fig. 1 and 2) of the adpll 10 generates a phase difference value (e.g., the FREF shown in fig. 2) according to the reference signal (e.g., the FREF shown in fig. 2) and the clock signal

)。

In step 440, the calibration circuit 120 of the adpll 10 can adjust a current (e.g., the switchable current ISW) of at least one current source in the dco according to the phase difference value.

FIG. 5 is an example of the calibration method of FIG. 4 according to one embodiment of the present invention, wherein one or more steps may be added, modified or deleted from the flowchart of FIG. 5 as long as the overall result is not hindered, and the steps do not have to be performed in the exact order shown in FIG. 5.

In step 500, the process begins.

In step 502, the all-digital phase-locked loop 10 can normally perform the locking operation of the phase-locked loop.

In step 504, the frequency control signal may be fixed to d [ k ].

In step 506, the correction circuit 120 may set the value of the switchable current ISW of the digitally controlled oscillator 100 to ISW _ init.

In step 508, the calibration circuit 120 can calculate and measure the index value

In step 510, the calibration circuit 120 (e.g., the finite state machine 122 therein) may determine whether it is the last step currently. If the determination result is "yes", the flow proceeds to step 518; if the determination result is "NO", the flow proceeds to step 512.

In step 512, correction circuit 120 (e.g., finite state machine 12 therein)2) Can judge the index value

Whether it is larger than the current minimum index value

(is marked as

For simplicity). If the determination result is "yes", the flow proceeds to step 516; if the determination result is "no", the flow proceeds to step 514.

In step 514, the correction circuit 120 (e.g., the finite state machine 122 therein) may determine the minimum index value

Is updated to

(is marked as

)。

In step 516, the correction circuit 120 (e.g., the finite state machine 122 therein) may update the control signal DCOISW to adjust the value of the switchable current ISW, and the process returns to step 508.

In step 518, the all-digital phase-locked loop 10 continues to perform the locking operation of the phase-locked loop.

In step 520, the process ends.

To summarize, embodiments of the present invention utilize an existing phase detector within the adpll to serve as a component for detecting phase noise of the digitally controlled oscillator, and utilize a calibration circuit to iteratively adjust the bias current within the digitally controlled oscillator based on the detection result to optimize the bias current based on the behavior of the phase noise. In addition, the embodiment of the invention does not greatly increase the additional cost. Therefore, the invention can optimize the circuit architecture aiming at the phase noise of the digital control oscillator under the condition of no side effect or less side effect, thereby improving the overall efficiency of the all-digital phase-locked loop.

The above description is only a preferred embodiment of the present invention, and all the equivalent changes and modifications made according to the claims of the present invention should be covered by the present invention.

[ notation ] to show

10 all-digital phase-locked loop

100 digitally controlled oscillator

110 filter

120 correction circuit

121 digital signal processing circuit

122 finite state machine

131: counter

132 time-to-digital converter

133. 134 calculating unit

140 accumulator

CKV clock signal

FREF reference signal

FCW _ F reference ratio

d [ k ] is the locking value

Accumulated result

Numerical value of phase difference

Integer part of frequency ratio

Fractional part of frequency ratio

Index value

DCOISW control signal

DCOI _INITIAL Initial value

310 absolute value calculating circuit

320 accumulator

410. 420, 430, 440 step

500. 502, 504, 506, 508, 510, 512, 514, 516, 518, 520, step

Claims

1. An all-digital phase-locked loop, comprising:

a digital control oscillator for generating a clock signal according to the frequency control signal;

a phase detector for generating a phase difference value according to a reference signal and the clock signal; and

a calibration circuit coupled between the digitally controlled oscillator and the phase detector;

wherein after the adpll is locked for a period of time, the frequency control signal is fixed to a locked value obtained when the adpll is locked, and the correction circuit adjusts a current of at least one current source in the dco according to the phase difference value.

2. The adpll of claim 1, wherein the correction circuit calculates the phase difference value to obtain an index value, and adjusts the current of the at least one current source to minimize the index value, wherein the index value corresponds to phase noise of the dco.

3. The adpll of claim 1, wherein the correction circuit comprises:

the digital signal processing circuit is used for calculating the phase difference value to obtain an index value; and

a finite state machine coupled to the digital signal processing circuit for adjusting the current of the at least one current source according to the change of the index value to minimize the index value;

wherein the index value corresponds to a phase noise of the numerically controlled oscillator.

4. The adpll of claim 3, wherein the dsp circuit accumulates absolute values of the phase difference values to generate the index value.

5. The adpll of claim 1, wherein the phase detector calculates a frequency ratio between the frequency of the reference signal and the frequency of the clock signal and compares the frequency ratio to a reference ratio to generate the phase difference value.

6. The all-digital phase-locked loop of claim 5 wherein the phase detector comprises a counter for calculating the integer portion of the frequency ratio.

7. The adpll of claim 5, wherein the phase detector comprises a time-to-digital converter for calculating the fractional portion of the frequency ratio.

8. A calibration method for an all-digital phase-locked loop includes:

locking for a period of time by using the all-digital phase-locked loop so as to make a frequency control signal of a digital control oscillator of the all-digital phase-locked loop converge to a locking value;

fixing the frequency control signal to the locking value to enable the digital control oscillator to generate a clock signal according to the locking value;

generating a phase difference value by using a phase detector of the all-digital phase-locked loop according to a reference signal and the clock signal; and

and adjusting the current of at least one current source in the digital control oscillator according to the phase difference value by utilizing a correction circuit of the all-digital phase-locked loop.

9. The calibration method of claim 8, wherein the step of utilizing the calibration circuit of the adpll to adjust the current of the at least one current source in the dco according to the phase difference value comprises:

calculating the phase difference value by using a digital signal processing circuit in the correcting circuit to obtain an index value; and

adjusting the current of the at least one current source to minimize the index value according to the change of the index value by using a finite state machine in the correction circuit;

10. The calibration method of claim 9, wherein the step of calculating the phase difference value by the digital signal processing circuit in the calibration circuit to obtain the index value comprises:

the absolute value of the phase difference value is accumulated by the digital signal processing circuit to generate the index value.