GB2420667A

GB2420667A - Frequency comparator

Info

Publication number: GB2420667A
Application number: GB0426049A
Authority: GB
Inventors: Jeff Butters
Original assignee: Snell and Wilcox Ltd
Current assignee: Snell Advanced Media Ltd
Priority date: 2004-11-26
Filing date: 2004-11-26
Publication date: 2006-05-31
Anticipated expiration: 2024-11-26
Also published as: GB2420667B; GB0426049D0

Abstract

Method and apparatus for generating an oscillating signal having a frequency which is controlled relative to a reference clock. An accumulator is maintained and proportionally adjusted in response to the reference clock and proportionally adjusted differently in response to the output oscillators. The process can be performed in the digital domain, and a non-integral multiple of the reference clock can be achieved.

Description

FREQUENCY COMPARKIJF

This invention concerns the generation of a single-frequency signal, such as a sampling clock, from a reference frequency having a known frequency relationship with respect to the signal to be generated.

It is often necessary to "lock" an oscillator at some nominal frequency to a signal at a different frequency so as to maintain a fixed ratio between the two frequencies. One example is the need to generate a sampling clock for a digital audio signal accompanying a digital television signal. If the audio and video components are to be multiplexed together for transmission it is advantageous for the audio and video sampling rates to be maintained in a fixed relationship with each other.

This problem is easy to solve where one of the frequencies is a simple integer multiple of the other. There are known methods for frequency division or multiplication which can be used in such cases; the multiple, or sub-multiple of an input frequency can be used directly, or indirectly. A well-known indirect method is to use an oscillator whose frequency is determined by a control voltage to generate the desired signal; the oscillator output is applied to a frequency multiplier or (more usually) divider and the resulting multiplied (or divided) output is compared with the reference frequency in a phase discriminator whose output is used to control the frequency of that oscillator.

Where the desired frequency ratio is not a simple integer multiple it may be possible to divide or multiply both frequencies by respective factors which give rise to two respective frequencies which can be compared and used to create a frequency-control signal for a variable frequency oscillator.

However this is unsatisfactory because two frequency multiplication (or division) processes are required.

It is an object of one aspect of the present invention to provide an improved method of oscillator control.

According to a first aspect, the invention provides a method of controlling the frequency of an oscillator relative to a reference clock frequency, wherein an accumulator is adjusted by a first value proportional to detected cycles of the reference clock frequency, and by a second value proportional to detected cycles of the oscillator frequency, and wherein the oscillator is controlled based on the value of the accumulator.

In this way, the frequency comparison process can advantageously be carried out substantially in the digital domain in a way which avoids the need S for frequency division or multiplication by impractical factors (e. g. those without binary sub-factors). Furthermore, the process can be performed using simple sequential logic controlled by a single frequency or clock, which may be one of the input or output frequencies.

A second aspect of the invention provides a method of locking the frequency of an oscillator to a given non-integral multiple of a reference frequency by incrementing an accumulator in response to at least one phase within a cycle of the said reference frequency and decrementing the accumulator in response to at least one phase within a cycle of the output from said oscillator; the ratio of: the total net increments due to a cycle of said reference frequency, to: the total net decrements due to one cycle at the output of said oscillator, being equal to said given non-integral multiple, wherein the value of the accumulator is used to control the frequency of said oscillator.

Suitably, an earlier increment or decrement is summed with a later increment or decrement and the result applied to the said accumulator.

Advantageously, the timing of the application of an increment or decrement to said accumulator is varied in dependence upon the instantaneous phase relationship between said reference frequency and the output of said oscillator.

Two examples of the invention will now be described with reference to the drawings in which: Figure 1 shows a locked oscillator system according to the invention.

Figure 2 shows how the contents of the accumulator of Figure 1 vary over time.

Figure 3 shows a locked oscillator system according to an alternative embodiment of the invention.

Figure 4 shows how the contents of the accumulator of Figure 3 vary over time.

Suppose it is necessary to generate a 48 kHz audio sampling clock from the 74.25 MHz video sampling clock of a digital, high-definition television system. A typical audio clock generator requires an input at a convenient binary multiple of 48 kHz, say 512 x 48 kHz, or 24.576 MHz. This frequency is related to the video sampling frequency by a ratio of 12375:4096.

Figure 1, shows a system for deriving this frequency from the video sampling frequency. Referring to the Figure, an input 74.25 MHz clock (1) drives a digital "latch" (2) which re-clocks (i.e. samples and holds) the binary clock signal from a voltage-controlled oscillator (3), having a nominal frequency of 24.576 MHz. The output from the latch (2) feeds a rising-edge detector (4), which outputs a binary logic signal which indicates the condition when the input to the latch (2) was HIGH at the last 74.25 MHz clock, but LOW at the preceding 74.25 MHz clock.

The output from the detector (4) controls a switch (5), with routes one of two increment values an accumulator (6). If no rising edge was detected, the accumulator (6) is incremented by 4,096 on the next 74.25 MHz clock; if a rising edge was detected the accumulator is decremented by 8,279 on the next 74.25 MHz clock.

The accumulator (6) should preferably be able to handle positive and negative count values of at least 12,375. And, it must be designed not to overflow or under-flow; i.e. an increment which would exceed the maximum positive count, or a decrement which would exceed the maximum negative count, should leave the count value substantially unchanged.

The value of the count is filtered and used in a known manner to control the frequency of the oscillator (3). A digital-to-analogue converter (7) creates an analogue voltage which represents to value in the accumulator (6) and this is low-pass filtered (8) to derive a frequency control voltage for the oscillator (3). Other methods (both analogue and digital) of filtering the stream of count values and using them to control the frequency of the oscillator (3) will be apparent to the skilled person.

The function of the accumulator (6) is to check whether, over time, there are the correct relative numbers of cycles of the two clocks, If the clock frequencies were required to be equal, this task would be easy - a cycle of one of the clocks would increment the accumulator by some value, and a cycle of the other clock would decrement it by the same value. However, this is not the case; there are more cycles of the faster clock than the slower clock in an arbitrary period.

The desired frequency ratio is 12,375:4,096. There will therefore be some time scale on which the period of a fast clock is represented by 4,096 units, and the period of a slow clock represents 12,375 units. It follows that if the frequencies are correct, the count should average to zero if it is incremented by 4,096 every fast clock cycle and decremented by 12, 375 every slow clock cycle.

In the system shown in Figure 1 the count is changed once per cycle of the faster (74.25 MHz) clock. When there has not been a rising edge of the slower clock the increment value is 4,096. However, when a rising edge of the slower clock has been detected the required increment of 4, 096 and the required decrement of 12,375 are combined in a net decrement of (12,375 - 4,096 =) 8,279.

If the frequency ratio is correct, the count will oscillate over a range of about 12,000 units as shown in Figure 2. As can be seen, there are generally two increments, followed by a decrement; this is because the desired frequency ratio is just over three times. Eventually, however the relative phasing of the two clocks reaches a point where there are three increments before the next decrement. The net effect is that the value that would be given by taking a running average (or other low-pass filter process having no response above about 150 times the frequency of the fast clock) of the count value is a constant depending on the initial conditions of the system.

If the frequency of the oscillator (3) is too high, there will be more decrements than can be cancelled by the increments, and the average count value will fall; this will result in the oscillator control signal falling, and so correcting the frequency to the intended relationship.

This method of comparison has the advantage over methods using modulatorbased phase discriminators that the error signal increases monotonically for a constant frequency error; the only limit is the size of the accumulator. The choice of accumulator maximum size will depend on the desired frequency ratio, the loop gain of the system, the type of loop filter used, and the required holding and capture ranges of the system. If a "second order loop" (in which the error signal is integrated) is used, then a smaller accumulator can be used. In general, the accumulator should be large enough not to reach its maximum or minimum limiting count in normal operation.

An alternative implementation, having a potentially faster response time, is shown in Figure 3 and will now be described. A voltage-controlled oscillator (301) is to be locked to a frequency of 4096/12,375 times the frequency of a reference digital-clock input (302). The output from the oscillator (301) clocks a latch (303) configured as a simple frequencyhalving circuit to give a binary signal (304) which changes state once per cycle of the oscillator (301). (This division stage is not always necessary, the system could be modified to use both positive and negative edges of the oscillator's output.) The frequency of the signal (304) is compared with that of the clock (302) in a digital process (305) to produce a phase error signal (306). This phase error signal can then be used to control the frequency of the oscillator (301) in known manner via a loop filter (307). The process (305) is a discrete- time digital process, controlled by the clock (302).

The signal (304) is sampled on the positive edge of the clock (302) by a latch (308), and the resulting signal is delayed (by half of one clock period) in the latch (309), which is clocked on the negative edge of the clock (302). The delayed and undelayed signals are compared in an exclusive-or gate (310) to give a signal (311) which indicates when the signal (304) has changed state.

The signal (311) therefore comprises a pulse once per cycle of the output from the oscillator (301).

The signal (304) is also sampled on the negative edge of the clock (302) by a latch (312) whose output is compared with that of the latch (309) in an exclusive-or gate (313). The result (314) of this comparison indicates the phasing of edges (transitions) of the signal (304) with respect to the clock (302). If the signal (304) changes state during the period when the clock (302) is high, the latch (312) will change state before the latch (308) and a pulse will appear at (314). Alternatively if the signal (304) changes state when the clock (302) is low, the latch (308) will change state before the latch (312) and there will be no pulse at (314). The signal (314) thus gives an indication of an "early" change of state by the signal (304).

A logic block (315) determines an increment value (316) and this increment is applied to an accumulator (317) on the positive edge of the clock (302).

- If there has been no edge of the signal (304) since the last clock (302) , the increment is set to 4,096 which is the phase value due to a cycle of the clock (302).

- If there has been an edge during the early half of the clock period (i. e. the "early" signal (314) is active) the increment is set to -8,279, which represents the net phase value due to one cycle of the clock (302) and one cycle of the oscillator (301).

(4,096 - 12,375 = -8,279) - If there has been an edge during the latter half of the clock period (i. e. there is no "early" signal (314)), the phase contribution due to the oscillator (301) is spread over two clock cycles as follows: On both the first and second clock cycles after the edge, the increment is one cycle of the clock (302) and half a cycle of the oscillator (301).

(4096 - 1/2 xl 2,375 -2091.5 which can be rounded to 2,091 on the first clock and 2,092 on the second clock.) The spreading of the phase contribution from later edges gives the system greater phase resolution and reduces the peak-to-peak variation of the count value, as shown in Figure 4. It can be seen that for part of the time (i.e. when the slow clock edges are "early") the system operates in the same way as that of Figure 1; however, when the slow clock edges fall in the later half of the fast clock cycles, the splitting of the large decrement over two (fast) clock cycles reduces the peak-to-peak variation of the accumulated count.

This does not affect the long term average count because the increment and decrement values for each complete cycle of each clock have not been changed. However, decrements due to the slow clock have effectively been delayed (or not) by half a fast clock cycle in dependence upon the timing of the slow clock edges relative to the fast clock. This allows an effective increase in the precision of the comparison.

In the two examples described so far, the digital processing has been controlled by the reference frequency; this is not essential. In some applications it may be preferable to clock the process at a convenient third frequency, which need not be related to the frequencies being compared.

Preferably this third frequency should be higher than either of the compared frequencies; the timing of the increments and decrements can then be controlled independently in response to transitions by the respective frequencies being compared.

It will be apparent that the concept of the invention can cover other embodiments not described here; for example: more than one edge of either or both clocks can be used to increment or decrement the accumulator; the increment from either clock can be spread over more than two cycles; and, the spreading can be varied more precisely with changes in the relative clock phase.

Claims

1. A method of controlling the frequency of an oscillator relative to a reference clock frequency, wherein an accumulator is adjusted by a first value proportional to detected cycles of the reference clock frequency, and by a second value proportional to detected cycles of the oscillator frequency, and wherein the oscillator is controlled based on the value of the accumulator.

2. A method according to Claim 1, wherein detection of cycles of the reference clock frequency and of the oscillator frequency is controlled by a single clock frequency.

3. A method according to Claim 1 or Claim 2, wherein the oscillator frequency is controlled to be a multiple of the reference frequency.

4. A method according to Claim 3, wherein said multiple is non-integral.

5. A method according to Claims 3 or 4, wherein the ratio of the first value to the second value is equal to said multiple.

6. A method according to any preceding claim wherein said first value is positive and said second value negative.

7. A method according to any preceding claim, wherein the accumulator value is low pass filtered.

8. A method of controlling the frequency of an oscillator to a given nonintegral multiple of a reference frequency by incrementing an accumulator in response to at least one phase within a cycle of the said reference frequency and decrementing the accumulator in response to at least one phase within a cycle of the output from said oscillator; the ratio of: the total net increments due to a cycle of said reference frequency, to: the total net decrements due to one cycle at the output of said oscillator, being equal to said given non-integral multiple, wherein the value of the accumulator is used to control the frequency of said oscillator.

9. A method according to Claim 8, in which an earlier increment or decrement is summed with a later increment or decrement and the result applied to the said accumulator.

1O.A method according to Claim 8 or Claim 9, in which the timing of the application of an increment of decrement to said accumulator is varied in dependence upon the instantaneous phase relationship between said reference frequency and the output of said oscillator.

11.Apparatus for controlling the frequency of an oscillator in response to a reference signal, comprising an accumulator; an edge detector and a processor, the processor adapted to adjust the accumulator by a first amount in response to an edge of said reference signal, and by a second amount in response to an edge of the output of said oscillator, and wherein the value of the accumulator is used to control the oscillator.

12.Apparatus according Claim 11, wherein said accumulator, said edge detector and said processor operate in the digital domain.

13. Apparatus according to Claim 11 or Claim 12, wherein said accumulator, said edge detector and said processor are all clocked at a common frequency.