CN105656480A - Low-noise video digital phase-locked loop - Google Patents
Low-noise video digital phase-locked loop Download PDFInfo
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- CN105656480A CN105656480A CN201511009480.9A CN201511009480A CN105656480A CN 105656480 A CN105656480 A CN 105656480A CN 201511009480 A CN201511009480 A CN 201511009480A CN 105656480 A CN105656480 A CN 105656480A
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- phase
- controlled oscillator
- clock
- video signal
- digital
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
- H03L7/0992—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider
Abstract
The invention relates to the field of video signal processing in the field of design of micro-electronics, and in particular relates to a digital phase-locked loop applied to video signal processing. The embodiment of the invention aims to provide a video signal clock recovery processing method and realize the purposes of inhibiting system noise and reducing phase-locked loop clock jitter. The digital phase-locked loop provided in the embodiment of the invention comprises a phase frequency detector PFD, a digital filter, a numerically controlled oscillator NCO and a feedback counter; an external Filter is unnecessary; the traditional analogue voltage-controlled oscillator VCO/current-controlled oscillator ICO is replaced in a manner of the numerically controlled oscillator NCO; a clock recovery circuit having high following performance and good performance is realized; the anti-interference capability is high; the system cost is low; and the method is realized by the following steps of: inputting synchronous signals HSYNCs of video signals in different modes, recovering a sampling clock and the synchronous signals to process by a rear-end digital analogue converter ADC, and performing video signal clock recovery processing by adopting the numerically controlled oscillator NCO.
Description
Technical field
The present invention relates to the field of video frequency signal processing in microelectronics design field, refer in particular to a kind of digital phase-locked loop being applied to video frequency signal processing.
Background technology
Phase Lock Technique is generally adopted phase-locked loop circuit (PhaseLockedLoop, PLL) realizing, it is KHz (KHz) that conventional phase locked loops realizes the line of input frequency of video signal, and the frequency band of wave filter is relatively low, the resistance capacitance value of wave filter is bigger, it is impossible to be integrated into chip internal. Chip needs external wave filter Filter, not only increases system cost, and external wave filter Filter is subject to ectocine in system, thus influential system performance. The digital phase-locked loop that the present invention adopts, it is not necessary to external wave filter Filter, system is simple, and anti-noise ability is strong. Adopting numerically-controlled oscillator NCO, chip area is little, and cost is low.
Summary of the invention
The purpose of the embodiment of the present invention is in that to propose a kind of digital phase-locked loop being applied to video frequency signal processing, it is intended to realize suppressing outside noise, reduces phase-locked loop clock shake.
Digital phase-locked loop of the present invention, including: phase frequency detector PFD, digital filter, numerically-controlled oscillator NCO and feedback counter, it is not necessary to external wave filter Filter. Substituting traditional analog vco VCO/ current control oscillator ICO by the mode of numerically-controlled oscillator NCO, it is achieved high followability, the clock recovery circuitry that performance is excellent, capacity of resisting disturbance is strong, and system cost is low.
To achieve these goals, the embodiment of the present invention proposes a kind of video signal processing method, and the method is achieved like this:
By the synchronizing signal HSYNC of the video signal of the different systems of input, again recover sampling clock and synchronizing signal by back-end digital analog converter ADC process, adopt numerically-controlled oscillator NCO to carry out video frequency signal processing;
When line of input horizontal-drive signal HSYNC clock is advanced or lag feedback clock, phase frequency detector PFD produces error signal (including extent and symbol by mistake). According to error signal, in numerically-controlled oscillator NCO, the value of accumulator is down or up, numerically-controlled oscillator NCO frequency reduces accordingly or increases, until the frequency of feedback clock and phase place are equal to frequency and the phase place of HSYNC clock, numerically-controlled oscillator NCO control bit will remain unchanged, thus low noise digital video phase lock loop locks.
The mode of error in judgement signal is to carry out counting error pulse width with high frequency clock, enumerator is destined to the accumulator of numerically-controlled oscillator NCO, so when error signal is wider, the number being sent to accumulator is relatively large, and time near phase lock loop locks, then the number being sent to accumulator is only small. If phase error is less than sampling clock cycle, then all without being detected in each cycle. Therefore, the phase error precision detected is determined by sample clock frequency, and frequency is more high, means less phase error. But high-frequency circuit then needs more hardware to realize the function identical with low-frequency channel, and high frequency power consumption is bigger.
For altofrequency phase error, increasing digital filter and process, its gain is programmable, and such error pulse width can less than the sampling clock in a cycle. At each HSYNC or feedback clock rising edge, accumulator direction determines that, will be regulated by a fixing value. The gain of wave filter is arranged in rational situation, even if phaselocked loop is in locking mode, numerically-controlled oscillator NCO still can finely tune at control point, without influence on the output frequency of numerically-controlled oscillator NCO.
The present invention has the advantage that and has the benefit effect that system is simple, and cost is low, and capacity of resisting disturbance is strong without external wave filter; Frequency drift is not had in synchronizing signal region during video frequency signal processing; Without balance between bandwidth and shake Jitter, digital phase-locked loop separate regulation; Employing digital form realizes, and chip area is little, and cost is low.
Accompanying drawing explanation
Fig. 1 is low noise digital video phase-locked loop module schematic diagram of the present invention;
Fig. 2 is traditional analog phaselocked loop illustraton of model;
Fig. 3 is low noise digital video phase-locked loop systems block diagram of the present invention;
Fig. 4 is traditional analog phase-locked loop module schematic diagram.
Detailed description of the invention
In order to make the purpose of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated. Should be appreciated that specific embodiment described herein is only in order to explain the present invention, is not intended to limit the present invention.
With reference to Fig. 1, low noise digital video phaselocked loop analogy traditional analog phaselocked loop of the present invention (with reference to Fig. 2), the transfer function of traditional analog phaselocked loop closed loop is:
Hclose=��2 n/(s2+2�Ʀ�n+��2 n)=��2 n/(s-s0)(s-s1)
The system block diagram of low noise digital video phase-locked loop pll of the present invention is with reference to Fig. 3, and the transfer function of system closed loop is as follows:
H(z)=ac��z-c/[z2+(ac-2)z+(1-c)]=N(z)/(z-z0)(z-z1)
The transfer function of low noise digital video cycle of phase-locked loop wave filter of the present invention and NCO is as follows:
Hfilter(z)=a��z-1/z-1
HNCO(z)=c��z/z-1
As k1=Gpd Gvco G1/N,k2=Gpd��Gvco��G2/ N, low noise digital video phaselocked loop closed function of the present invention is:
H(z)=N[(k1+k2)z-k1]/[z2+(k1+k2-2)z+(1-k1)]
When molecule=0, and combine mapping result above and can obtain the value of k1 and k2.
When �� and the �� n of system is known, k1 and k2 can calculate and learn.
The root that the steady-state conditions of discrete-time system is characteristic equation must in unit circle planar. One of maximally effective standard of discrete-time system stability is Jury ' s stability criterion. The method can instruct the design of digital phase-locked loop to converge to rapidly a stable system, it is not necessary to carries out substantial amounts of numerical computations. For a second-order system, according to this standard, stable essential condition and sufficient condition be: (1) 0; (-1) 0; | a0| a2��
The characteristic equation of second-order system, or the feature of transmission function:
��(z)=a2z2+a1z+a0=0
Conditions above ensures that the root of characteristic equation must in unit circle planar. Apply these conditions, it is possible to derive the steady-state conditions of digital servo-control ring structure: 0 < k1 < 2;0 < k2 < 4.
Claims (6)
1. for a digital phase-locked loop for video frequency signal processing, including phase frequency detector PFD, digital filter, numerically-controlled oscillator NCO and feedback counter.
2. digital phase-locked loop according to claim 1, it is characterised in that carry out video signal clock recovery under the premise without external wave filter Filter.
3. video signal clock restoration methods according to claim 2, it is characterised in that substitute traditional analog vco VCO/ current control oscillator ICO by the mode of numerically-controlled oscillator NCO.
4. the video signal clock restoration methods according to Claims 2 or 3, it is characterised in that by the synchronizing signal HSYNC of the video signal of the different systems of input, recovers sampling clock and synchronizing signal again by back-end digital analog converter ADC process.
5. video signal clock restoration methods according to claim 4, it is characterised in that described method includes when line of input synchronizing signal HSYNC clock is advanced or during lag feedback clock, it is achieved digital video phase lock loop locks.
6. video signal processing method according to claim 5, it is characterized in that, described method includes numerically-controlled oscillator NCO frequency and is adjusted with the phase frequency detector PFD error signal produced, when the frequency of feedback clock and phase place equal to the frequency of HSYNC clock and phase place, numerically-controlled oscillator NCO control bit remains unchanged.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201511009480.9A CN105656480A (en) | 2015-12-30 | 2015-12-30 | Low-noise video digital phase-locked loop |
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| CN201511009480.9A CN105656480A (en) | 2015-12-30 | 2015-12-30 | Low-noise video digital phase-locked loop |
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| CN105656480A true CN105656480A (en) | 2016-06-08 |
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| CN201511009480.9A Pending CN105656480A (en) | 2015-12-30 | 2015-12-30 | Low-noise video digital phase-locked loop |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112911188A (en) * | 2018-07-25 | 2021-06-04 | 杭州海康威视数字技术股份有限公司 | Video signal system identification method and device, electronic equipment and readable storage medium |
| US11930158B2 (en) | 2018-07-25 | 2024-03-12 | Hangzhou Hikvision Digital Technology Co., Ltd. | Video signal identification method and apparatus, electronic device and readable storage medium |
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| CN101520672A (en) * | 2009-03-20 | 2009-09-02 | 东南大学 | All-digital spread-spectrum clock generator for use in SATA |
| CN101582691A (en) * | 2008-05-16 | 2009-11-18 | 上海全盛微电子有限公司 | De-twitter circuit based on fully digital phase-locked loop |
| CN102916693A (en) * | 2012-11-02 | 2013-02-06 | 长沙景嘉微电子股份有限公司 | All-digital phase-locked ring applicable to video signal processing |
| CN103269220A (en) * | 2013-05-30 | 2013-08-28 | 上海坤锐电子科技有限公司 | Clock recovery circuit through NFC active load modulation based on digital phase-locked loop |
| CN104333377A (en) * | 2013-07-08 | 2015-02-04 | 美国亚德诺半导体公司 | Digital phase detector |
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2015
- 2015-12-30 CN CN201511009480.9A patent/CN105656480A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1409490A (en) * | 2001-09-30 | 2003-04-09 | 深圳市中兴通讯股份有限公司上海第二研究所 | Shake-removing circuit based on digital lock phase loop |
| CN101582691A (en) * | 2008-05-16 | 2009-11-18 | 上海全盛微电子有限公司 | De-twitter circuit based on fully digital phase-locked loop |
| CN101520672A (en) * | 2009-03-20 | 2009-09-02 | 东南大学 | All-digital spread-spectrum clock generator for use in SATA |
| CN102916693A (en) * | 2012-11-02 | 2013-02-06 | 长沙景嘉微电子股份有限公司 | All-digital phase-locked ring applicable to video signal processing |
| CN103269220A (en) * | 2013-05-30 | 2013-08-28 | 上海坤锐电子科技有限公司 | Clock recovery circuit through NFC active load modulation based on digital phase-locked loop |
| CN104333377A (en) * | 2013-07-08 | 2015-02-04 | 美国亚德诺半导体公司 | Digital phase detector |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112911188A (en) * | 2018-07-25 | 2021-06-04 | 杭州海康威视数字技术股份有限公司 | Video signal system identification method and device, electronic equipment and readable storage medium |
| US11930158B2 (en) | 2018-07-25 | 2024-03-12 | Hangzhou Hikvision Digital Technology Co., Ltd. | Video signal identification method and apparatus, electronic device and readable storage medium |
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Application publication date: 20160608 |