CN112911188A - Video signal system identification method and device, electronic equipment and readable storage medium - Google Patents
Video signal system identification method and device, electronic equipment and readable storage medium Download PDFInfo
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Abstract
The application provides a video signal system identification method, a device, an electronic device and a readable storage medium, wherein the method comprises the following steps: reading a standard value of the received video signal; when the standard value is shared by target video signals of multiple standards, registers are configured according to the standards of the target video signals respectively, and whether the received video signals are locked or not is detected; when the register is configured according to a first target system and the received video signal is detected to be locked, determining the system of the received video signal as the first target system. The method can improve the accuracy of video signal system identification.
Description
Technical Field
The present disclosure relates to video monitoring technologies, and in particular, to a method and an apparatus for identifying a video signal format, an electronic device, and a readable storage medium.
Background
The traditional Video monitoring industry mainly comprises products such as Video acquisition equipment (such as an analog camera) and Video storage equipment (such as a Digital Video Recorder (DVR)), and external scenes are acquired by the Video acquisition equipment and then transmitted to the Video storage equipment for storage, Video analysis and other processing.
The video signal transmission between the video acquisition device and the video storage device comprises two technologies of modulation output and modulation input. Since there are various types of video acquisition devices and different formats of corresponding video signals, in order to ensure compatible access of video signals, a video storage device needs to be able to accurately identify the format of a received video signal.
Disclosure of Invention
In view of the above, the present application provides a method and an apparatus for identifying a video signal format, an electronic device and a readable storage medium.
Specifically, the method is realized through the following technical scheme:
according to a first aspect of an embodiment of the present application, there is provided a method for identifying a video signal format, including:
reading the standard value of the received video signal by reading the standard value of the register;
when the standard value is shared by target video signals of multiple standards, a register is configured according to at least one standard in the standards of each target video signal until the received video signal is locked;
when the register is configured according to a first target system and the received video signal is locked, determining the system of the received video signal as the first target system; wherein the first target format is a format of a first target video signal among the plurality of target video signals.
According to a second aspect of the embodiments of the present application, there is provided a video signal format identifying apparatus, including:
the reading unit is used for reading the standard value of the received video signal by reading the standard value of the register;
the configuration unit is used for configuring a register according to at least one system in the system of each target video signal until the received video signal is locked when the system value is shared by the target video signals of multiple systems;
the determining unit is used for determining the format of the received video signal as the first target format when the configuration unit configures the register according to the first target format and the received video signal is locked; wherein the first target format is a format of a first target video signal among the plurality of target video signals.
According to a third aspect of the embodiments of the present application, there is provided a video processing apparatus, where the video processing apparatus includes an AD chip, and the AD chip is configured to implement the above-mentioned video signal format identification method.
According to a fourth aspect of the embodiments of the present application, there is provided an electronic device, including a processor, a communication interface, a memory, and a communication bus, where the processor, the communication interface, and the memory complete communication with each other through the communication bus;
a memory for storing a computer program;
and the processor is used for realizing the video signal system identification method when executing the program stored in the memory.
According to a fifth aspect of embodiments of the present application, there is provided a computer-readable storage medium having stored therein a computer program, which when executed by a processor, implements the above-described video signal format identification method.
According to the video signal system identification method, the system value of a received video signal is read by reading the system value of a register, and when the system value is shared by target video signals of multiple systems, the register is configured according to at least one system in the systems of the target video signals until the received video signals are locked; when the register is configured according to the first target system and the received video signal is locked, the system of the received video signal is determined to be the first target system, and the accuracy of video signal system identification is improved.
Drawings
Fig. 1 is a flowchart illustrating a method for identifying a format of a video signal according to an exemplary embodiment of the present application;
FIG. 2 is a schematic diagram of a one frame 4M12.5 video signal and a two frame 720P25 video signal shown in an exemplary embodiment of the present application;
fig. 3 is a flowchart illustrating a video signal format identification method according to another exemplary embodiment of the present application;
FIG. 4 is a diagram illustrating an example embodiment of the present application for identifying a format of a received video signal using priority polling;
fig. 5 is a schematic structural diagram of a video signal format recognition apparatus according to an exemplary embodiment of the present application;
fig. 6 is a schematic structural diagram of a video signal format recognition apparatus according to still another exemplary embodiment of the present application;
fig. 7 is a schematic diagram of a hardware structure of an electronic device according to an exemplary embodiment of the present application.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
In order to make the technical solutions provided in the embodiments of the present application better understood and make the above objects, features and advantages of the embodiments of the present application more comprehensible, the technical solutions in the embodiments of the present application are described in further detail below with reference to the accompanying drawings.
Referring to fig. 1, a flowchart of a video signal recognition method according to an embodiment of the present disclosure is shown, where the video signal recognition method can be applied to an AD chip in a video processing device having an AD (Analog-to-Digital) chip, such as an AD chip of a DVR (hereinafter, the video processing device is referred to as a DVR for example), and as shown in fig. 1, the method can include the following steps:
it should be noted that, in the embodiments of the present application, unless otherwise specified, all of the mentioned video signals are analog video signals, and the description thereof will not be repeated in the embodiments of the present application.
And S100, reading the standard value of the received video signal.
In the embodiment of the present application, when receiving a video signal, an AD chip configures a value of system information (referred to as a system value herein for short) of a register according to the system information in the video signal.
For example, the AD chip can record system information of a received video signal in bits 0 to 2 of a 0x3 register.
The format of the video signal may include, but is not limited to: NTSC (National Television Standards Committee), PAL (Phase alternation Line), 720P25/30, 720P50/60, 1080P25/30, 1080P HALF25/30, 3M18, 4M12.5/15, 4M25/30, 4M HALF25/30, 5M12, 5M20, 5M HALF 20, 8M12.5/15, 8M HALF 12.5/15, etc.; the video signals of all systems have corresponding system values.
Correspondingly, when the format of the video signal needs to be identified, the AD chip can determine the format value of the received video signal by reading the format value of the register.
For example, the AD chip can read the values of bits 0 to bit2 of the 0x3 register.
Step S110, when the standard value is shared by target video signals of multiple standards, registers are configured according to the standards of the target video signals respectively, and whether the received video signals are locked or not is detected.
In the embodiment of the present application, it is considered that in an actual application scenario, there may exist a situation that format values of video signals of multiple formats are the same, that is, video signals of multiple formats share the same format value, and therefore, the format of the video signal may not be accurately identified only according to the format value.
For example, assuming that the format value is 0x6, the format of the video signal may be NTSC or PAL; assuming that the format value is 0x7, the format of the video signal may be 3M18, 5M12, or 5M 20.
Correspondingly, when the AD chip reads the standard value of the register, the AD chip can judge whether the standard value is shared by the target video signals of multiple standards, and when the standard value is determined to be shared by the target video signals of multiple standards, the standard of the received video signals is further identified according to other strategies.
In this embodiment of the application, when the AD chip determines that the read format value is shared by video signals of multiple formats (referred to as target video signals herein), the AD chip may configure registers according to formats of the target video signals, and detect whether the received video signals are locked.
For example, the AD chip may select the format of each target video signal in a polling manner, configure a register according to the format of the selected target video signal, and detect whether the received video signal is locked.
For specific implementation of the AD chip configuring the register according to the selected format, reference may be made to related descriptions in the related art, and details of the embodiment of the present application are not described herein.
For example, assuming that the format values read by the AD chip are shared by target video signals of formats 1 to 3 (assuming that the target video signals are 1 to 3 respectively), the AD chip may select format 1 first, configure a register according to format 1, and detect whether the received video signal is locked, in the order from the front to the back of formats 1 to 3; if the video signal is not locked, selecting the system 2, configuring a register according to the system 2, and detecting whether the received video signal is locked; and if the video signal is not locked, selecting the system 3, configuring a register according to the system 3, and detecting whether the received video signal is locked.
Step S120, when the register is configured according to the first target system and the received video signal is detected to be locked, determining that the system of the received video signal is the first target system.
In the embodiment of the present application, the first target format does not refer to a fixed format, but may refer to a format of any one of the target video signals (referred to as a first target video signal herein).
In this embodiment of the application, when the AD chip configures the register according to the first target format and detects that the received video signal is locked, the AD chip may stop format selection and register configuration and determine that the format of the received video signal is the first target format.
The detecting, by the AD chip, that the received video signal is locked may include detecting that both a line synchronization signal lock (HLOCK) and a field synchronization signal lock (VLOCK, which may also be referred to as a frame synchronization signal lock) of the received video signal are locked by the AD chip.
The specific implementation of the AD chip determining whether the line synchronization signal lock or the field synchronization signal lock of the video signal is locked may refer to related descriptions in the related art, and details of the embodiment of the present application are not repeated herein.
In one embodiment of the present application, the configuring the register according to the system of each target video signal, and detecting whether the received video signal is locked may include:
determining the priority of the system of each target video signal;
and according to the sequence of the priority from high to low, sequentially configuring registers according to the system of each target video signal, and detecting whether the received video signal is locked.
In this embodiment, when the AD chip determines that the read format value is shared by target video signals of a plurality of formats, the AD chip may determine the format priority of each target video signal.
For example, the AD chip may determine the priority of the system of each target video signal in accordance with the usage probability of the system of each target video signal.
The use probability of the system of each target video signal can be an empirical value and can be configured in an AD chip in advance; the higher the probability of use of the target video signal, the higher its priority.
In this embodiment, after determining the priority of each target video signal, the AD chip may poll each target video signal in order of priority from high to low, configure the registers in sequence according to the format of each target video signal, and detect whether the received video signal is locked.
For example, assuming that the format value read by the AD chip is V1, the format value is shared by video signals of format 1 and format 2, and the usage probability of format 1 is higher than that of format 2, the AD chip may determine that the priority of format 1 is higher than that of format 2, and accordingly, the AD chip may configure a register according to format 1 first and detect whether the received video signal is locked, and if so, determine that the format of the received video signal is format 1; if not, the register is configured according to the system 2, whether the received video signal is locked is detected, and if the received video signal is locked, the system of the received video signal is determined to be the system 2.
It should be noted that, in this embodiment of the application, when the AD chip configures the register according to the system of each target video signal, and detects that the received video signal is unlocked, the AD chip may identify the system of the received video signal for a certain number of times (which may be set according to an actual scene) again according to the manners described in step S100 to step S120, or identify the system of the received video signal according to other policies, and a specific implementation manner of the application is not limited in this application.
Further, in this embodiment, after the AD chip configures the register according to a certain system, even if the system of the video signal received by the AD chip is the same as the system, the AD chip may need a certain time to detect that the video signal is locked.
Accordingly, in an implementation manner of this embodiment, the configuring the registers according to the format of each target video signal in sequence from high priority to low priority, and detecting whether the received video signal is stable may include:
the system configuration registers of the ith target video signal are sorted according to the priority, until the received video signal is locked, or when the frequency of the system configuration registers of the ith target video signal is sorted according to the priority reaches Ni, the received video signal is not locked; wherein the initial value of i is 1;
let i be i +1 and repeat the above steps until the received video signal is locked, or i be n.
In this embodiment, the number of times of the configuration register according to the system of the target video signal of each priority may be configured in the AD chip.
The number of times of system configuration registers of the ith target video signal is sorted according to the priority is Ni; the larger i is, the lower the priority is (i.e., sorted in order of priority from high to low), i is 1 ≦ n, and n is the number of formats of the target video signal.
In this embodiment, the AD chip may first prioritize the 1 st (i.e., highest priority) target video signal format configuration register until the received video signal is locked, or when the number of times of prioritizing the 1 st target video signal format configuration register reaches N1, the received video signal is still unlocked.
After the register is configured each time, the AD chip can determine whether the received video signal is locked, and when it is detected that the received video signal is unlocked, continue the next configuration and determination.
In this embodiment, when the number of times of the format configuration register of the target video signal of the AD chip 1 in the priority order reaches N1 and the received video signal is still unlocked, the AD chip may lock the format configuration register of the target video signal of the AD chip 2 in the priority order (i.e., the priority order is the second highest) until the received video signal is locked, or when the number of times of the format configuration register of the target video signal of the AD chip 2 in the priority order reaches N2, the received video signal is still unlocked.
And analogizing in sequence, until the number of times that the AD chip configures the register according to the nth (i.e., lowest priority) target video signal in the priority order reaches Nn and the received video signal is still unlocked, the AD chip may identify the format of the received video signal a certain number of times (which may be set according to an actual scene) again according to the manner described in the embodiment, or identify the format of the received video signal according to other policies, which is not limited in the specific implementation manner of the present application.
Preferably, Ni > 1.
In one example, the larger i, the larger Ni, that is, the higher priority system of the target video signal, the more times the register is configured in accordance with the system of the target video signal.
For example, assuming that the format value read by the AD chip is V1, the format value is shared by video signals of the formats 1 and 2, and the usage probability of the format 1 is higher than that of the format 2, the AD chip may determine that the priority of the format 1 is higher than that of the format 2, and accordingly, the number of times that the AD chip configures the register according to the format 1 is greater than that of times that the AD chip configures the register according to the format 2, for example, the number of times that the AD chip configures the register according to the format 1 is 6 times, and the number of times that the AD chip configures the register according to the format 2 is 3 times.
Further, in the embodiment of the present application, in practical applications, when the AD chip configures the registers according to the system of each target video signal respectively in the above manner, and detects whether the received video signal is locked, a situation that the video signal is locked by mistake may occur.
For example, taking the standards 4M12.5 and 720P25 as examples, the two standards share the same standard value, and the video signals of the two standards have the same line length.
If the signal currently received by the AD chip is 4M12.5, but the AD chip configures the register according to the system 720P25, and then detects that both the HLOCK and the VLOCK of the received video signal are locked, at this time, the AD chip considers that the system of the received signal is 720P25, and false locking occurs, and further, in the subsequent flow, video signal processing is abnormal due to a video signal system identification error, so that when the video signal system identification is performed according to the above manner, it is necessary to determine whether there is a video signal false locking condition.
Correspondingly, in one embodiment of the present application, when the register is configured according to the first target format and it is detected that the received video signal is locked, the determining that the format of the received video signal is the first target format may further include:
detecting whether a color carrier of the received video signal is locked;
if the color carrier of the received video signal is locked, determining to execute the step of determining the format of the received video signal to be a first target format;
and if the color carrier of the received video signal is not locked, determining that the received video signal is wrongly locked.
In this embodiment, it is considered that when the video signal is mis-locked, the color carrier of the video signal is usually not locked (i.e., the SLOCK is not locked), and therefore, whether the video signal is mis-locked can be determined according to whether the color carrier is locked.
Correspondingly, when the AD chip configures the register according to the first target system and detects that the received video signal is locked, the AD chip can detect whether the color carrier of the received video signal is locked; if the color carrier is locked, determining the system of the received video signal as a first target system; and if the color carrier wave is not locked, determining that the received video signal is wrongly locked.
In this embodiment of the application, when the AD chip determines that the received video signal is locked incorrectly, the AD chip may perform format identification on the received video signal again according to the above-described manner, or identify the format of the received video signal according to other strategies, and specific implementation thereof is not described herein again.
Further, in this embodiment, considering that the SLOCK cannot be locked immediately due to the color carrier fading when the signal is accessed through a long line, the SLOCK needs to be locked after the gain is automatically or manually adjusted to compensate for the fading. Therefore, before the fading compensation is completed, it cannot be determined whether the SLOCK is not locked because of the video signal mislocking or not because the SLOCK is not locked because of a long line.
Accordingly, in an implementation manner of this embodiment, if the color carrier of the received video signal is not locked, before determining that the received video signal is mis-locked, the method may further include:
setting the range of gain adjustment to be maximum, and adjusting the gain to be maximum;
detecting whether a color carrier of the received video signal is locked;
and if the color carrier of the received video signal is not locked, determining to execute the step of determining that the video signal is locked by mistake.
In this embodiment, when the AD chip determines that the color carrier of the received video signal is not locked, the AD chip may set the range of gain adjustment to maximum and adjust the gain to maximum to avoid the SLOCK being unable to lock due to the color carrier fading, and detect whether the color carrier of the received video signal is locked.
If the color carrier of the received video signal is not locked, the AD chip can determine that the received video signal is locked by mistake; if the color carrier of the received video signal is locked, the AD chip may determine that the received video signal is locked, and determine the system of the received video signal according to the register configuration.
In another embodiment of the present application, when the register is configured according to a first target format and it is detected that the received video signal is locked, the determining that the format of the received video signal is before the first target format may further include:
if the frame rate of the first target video signal is half of that of other target video signals, reading the voltage value of a target row of one frame of the first target video signal; the target line is any one line among a preset number of lines from top to bottom in the middle of a frame of the first target video signal;
if the voltage value of the target line is a non-negative value, determining to execute the step of determining that the format of the received video signal is a first target format;
and if the voltage value of the target row is a negative value, determining that the received video signal is locked by mistake.
In this embodiment, when the frame rate of the first target video signal is half of the frame rates of the other target video signals, that is, the duration of each frame of the first target video signal is twice the duration of each frame of the other target video signals, two frames of the other target video signals are present in the duration of one frame of the first target video signal. The very middle of a frame of the first target video signal corresponds to the beginning of a frame of the other target video signals.
Since the start of a frame of video signal is a field sync signal, the field sync signal is a low level (i.e., the voltage value is negative). And the middle of one frame of video signal is image information, and the voltage is a non-negative level value (i.e. the voltage value is a non-negative value), therefore, it can be determined whether the format of the received video signal is the first target format according to the voltage value of any line (referred to as target line herein) between the upper and lower preset number of the middle line of the first target video signal (which can be determined according to the number of lines of image information area and the number of lines of blanking area of the first target video signal and other target video signals), and further, it is determined whether the received video signal is mistakenly locked.
For example, taking the standards 4M12.5 and 720P25 as examples, the 4M12.5 signal is 12.5 frames per second, i.e. one frame is 80ms, the 720P25 signal is 25 frames per second, i.e. one frame is 40M; thus, for a duration of 80ms, there is one frame of the 4M12.5 video signal or two frames of the 720P25 video signal. In a frame 4M12.5, at the very middle of the 4M12.5 frame, there is a beginning of a 720P25 frame, which is schematically shown in fig. 2.
Assuming that the AD chip configures the register according to 4M12.5 (i.e. the first target format is 4M12.5), and detects that the received video signal is locked, at this time, the AD chip reads the voltage value of the middle line of the first target video signal of one frame.
If the voltage value of the right middle line is a non-negative value, the AD chip can determine that the standard of the received video signal is 4M 12.5;
if the voltage value in the middle is a negative value, the AD chip may determine that the format of the received video signal is not 4M12.5, that is, the received video signal is mis-locked.
Further, in the embodiment of the present application, in consideration that in an actual application scenario, when video signals of multiple formats share the same format value, the line lengths of the multiple video signals may be different, and at this time, the formats of the multiple video signals may be identified according to the line lengths of the multiple video signals.
Correspondingly, in one embodiment of the present application, when the read format value is shared by target video signals of multiple formats, before configuring the register according to the format of each target video signal, the method may further include:
determining line lengths of a plurality of target video signals;
if the line lengths of the various target video signals are the same, determining to execute the step of respectively configuring the registers according to the system of each target video signal;
and if the line lengths of the various target video signals are different, determining the system of the received video signal according to the line lengths of the various target video signals and the line length of the received video signal.
In this embodiment, when the AD chip determines that the read format value is shared by target video signals of multiple formats, the AD chip may determine the line length of the target video signals of the multiple formats.
If the line lengths of the plurality of target video signals are the same, the AD chip may identify the format of the target video signal in the manner described in steps S110 to S120.
If the line lengths of the plurality of target video signals are different, the AD chip may determine the format of the received video signal according to the line lengths of the plurality of target video signals and the line length of the received video signal.
It should be noted that, in the embodiment of the present application, when the line lengths of the plurality of types of target video signals are different, the AD chip may also identify the format of the target video signal in the manner described in step S110 to step S120.
In addition, when the number of the target video signals is three or more and the line lengths of the multiple target video signals are not completely the same (i.e., the line lengths of some target video signals are the same and the line lengths of some target video signals are different), the AD chip may first identify the format of the received video signal according to the line lengths, and further perform video signal format identification in the manner described in step S110 to step S120 when the format of the received video signal cannot be identified according to the line lengths (i.e., there are multiple target video signals having the same line length as the received video signal); alternatively, the AD chip may directly perform video signal format recognition in the manner described in step S110 to step S120.
In an implementation manner of this embodiment, the determining the format of the received video signal according to the line lengths of the plurality of target video signals and the line length of the received video signal includes:
reading a line length value of a register;
and determining the system of the received video signal according to the line length value and the line length of each target video signal.
In this embodiment, the AD chip may determine the line length of the received video signal by reading the line length value of the register, compare the line length of the received video signal with the line lengths of the respective target video signals, and determine the format of the target video signal that is the same as the line length of the received video signal as the format of the received video signal.
The specific implementation of the AD chip determining the line length of the received video signal by reading the line length value of the register may refer to related descriptions in the related art, and details of the embodiment of the present application are not repeated herein.
In order to make those skilled in the art better understand the technical solutions provided in the embodiments of the present application, the following describes the technical solutions provided in the embodiments of the present application with reference to specific examples.
In this embodiment, the formats of the video signals include NTSC, PAL, 720P25/30, 720P50/60, 1080P25/30, 1080P HALF25/30, 3M18, 4M12.5/15, 4M25/30, 4M HALF25/30, 5M12, 5M20, 5M HALF 20, 8M12.5/15, 8M HALF 12.5/15 as an example, wherein 3M18, 5M12 and 5M20 share one format value, the line lengths of the video signals of the three formats are the same, and at most two formats in the remaining formats share one format value, for example, 4M25 and 720P 50; 4M30 and 720P 60; 1080P25 and 8M 12.5; 1080P30 and 8M 15; NTSC and PAL; 4M12.5 and 720P 25; 4M15 and 720P30, wherein the line lengths of these video signals of the two formats sharing one format value are the same.
In this embodiment, a video signal format identification scheme implementation flow may be as shown in fig. 3, which may include the following steps:
and step S300, reading the standard value of the register.
Step S310, judging whether the standard value is shared by the video signals of the three standards. If yes, go to step S320; otherwise, go to step S330.
Step S320, identifying the format of the received video signal by using a line length determination method.
In this embodiment, when the AD chip determines that the read format value is common to the video signals of the three formats, the AD chip may determine that the format of the received video signal is 3M18, 5M12, or 5M 20.
At this time, the AD chip may recognize the format of the received video signal using a line length method, that is, the AD chip may read a line length value of a register to determine the line length of the received video signal, compare the line length of the received video signal with the line lengths of the video signals of 3M18, 5M12, and 5M20, respectively, and determine the format of the received video signal using a format in which the line length (3M18, 5M12, or 5M20) is the same as the line length of the received video signal.
And step S330, judging whether the standard value is shared by the video signals of the two standards. If yes, go to step S340; otherwise, go to step S350.
And step S340, identifying the format of the received video signal by using a priority polling method.
In this embodiment, when the AD chip determines that the read format value is shared by video signals of three formats, the AD chip may identify the format of the received video signal by using a priority polling method, that is, the AD chip may first determine the priority of the video signal of two formats corresponding to the format value, first configure the register according to the format of the video signal with the higher priority, and detect whether the received video signal is locked, and if not, configure the register according to the format of the video signal with the lower priority, and detect whether the received video signal is locked.
For example, taking standards 4M25 and 720P50 as examples (assuming the standard value is v1), since the probability of using 4M25 is much higher than 720P50, 4M25 has higher priority than 720P 50. When the format value of the register acquired by the AD chip is v1, the AD chip may determine that the format value is shared by 4M25 and 720P50, and at this time, a specific implementation that the AD chip identifies the format of the received video signal by using a priority polling method may be as shown in fig. 4, where the specific implementation may include the following steps:
step S400, judging whether the count value of the counter is less than 6; if yes, go to step S410; otherwise, go to step S430.
Step S410, configure the register according to 4M25, and increment the count value of the counter by 1.
Step S420, detecting whether the received video signal is locked. If yes, determining the format of the received video signal to be 4M 25; otherwise, go to step S400.
In this example, it is assumed that during one priority polling process, the register is configured according to 4M25, and whether the received video signal is locked is detected; if not, continuing to configure the register according to 4M25 and detecting whether the received video signal is locked or not until the received video signal is locked or the received video signal is not locked when the number of times of configuring the register according to 4M25 reaches 6 times.
Step S430 configures the register according to 720P50, and increments the counter value of the counter by 1.
Step S440, detecting whether the received video signal is locked. If yes, determining the format of the received video signal to be 720P 50; otherwise, go to step S450.
Step S450, judging whether the count value of the counter is less than 9; if yes, go to step S430; otherwise, the priority polling is finished.
In this example, if the number of times the register is configured by 4M25 reaches 6 times and the received video signal is not locked yet, the AD chip may configure the register by 720P50 and detect whether the received video signal is locked; if not, the register is continuously configured according to 720P50, and whether the received video signal is locked or not is detected until the received video signal is locked, or the received video signal is not locked when the register is configured according to 720P50 for 3 times.
It should be noted that, in this example, when the count value of the counter reaches 9 (that is, the number of times of configuring the register according to 4M25 reaches 6 times, and the number of times of configuring the register according to 720P50 reaches 3 times), and the received video signal is still unlocked, the AD chip may clear 0 from the counter, re-determine the format value of the received video signal, and start to identify the format of the video signal for a new time according to the above-mentioned manner, or implement the identification of the format of the video signal according to other policies, which is not limited in this embodiment of the application.
In addition, when the AD chip detects that the received video signal is locked, the counter can be cleared.
Step S350, configuring a register according to the system corresponding to the system value, and detecting whether the received video signal is locked; if so, determining the system of the received signal as the system corresponding to the system value; otherwise, ending the video signal system identification.
In this embodiment, if the AD chip determines that the read format value is not shared by the video signals of multiple formats, the AD chip may directly configure the register according to the format corresponding to the format value and detect whether the received video signal is locked, and if so, determine that the format of the received signal is the format corresponding to the format value.
It should be noted that, in this embodiment, when the AD chip does not recognize the format of the received video signal in the manner described in steps S300 to S350, the AD chip may perform a new video signal format recognition in the manner described in steps S300 to S350 again, or implement the video signal format recognition according to other strategies, which is not limited in this embodiment of the application.
In the embodiment of the application, by determining the standard value of the received video signal, when the standard value is shared by target video signals of multiple standards, registers are respectively configured according to the standard of each target video signal, and whether the received video signal is locked is detected; when the register is configured according to the first target system and the received video signal is detected to be locked, the system of the received video signal is determined to be the first target system, and the accuracy of video signal system identification is improved.
The methods provided herein are described above. The following describes the apparatus provided in the present application:
referring to fig. 5, a schematic structural diagram of a video signal format recognition apparatus provided in an embodiment of the present application is shown, where the video signal format recognition apparatus may be applied to an AD chip in the foregoing method embodiment, and as shown in fig. 5, the video signal format recognition apparatus may include:
a reading unit 510, configured to obtain a standard value of a received video signal;
a configuration unit 520, configured to configure registers according to the system of each target video signal when the system value is shared by target video signals of multiple systems;
a detecting unit 530 for detecting whether the received video signal is locked;
a determining unit 540, configured to determine, when the configuration unit configures the register according to a first target format and the detecting unit detects that the received video signal is locked, that the format of the received video signal is the first target format; wherein the first target format is a format of a first target video signal among the plurality of target video signals.
In an optional implementation manner, the determining unit 540 is further configured to determine a priority of a system of each target video signal;
the configuration unit 520 is specifically configured to configure the registers according to the system of each target video signal in sequence from high priority to low priority.
In an optional implementation manner, the configuration unit 520 is specifically configured to configure the system configuration register of the ith target video signal according to a priority, until the detection unit detects that the received video signal is locked, or when the number of times of configuring the system register of the ith target video signal according to the priority reaches Ni, the detection unit detects that the received video signal is still unlocked; wherein, the initial value of i is 1, and the larger i is, the lower the priority is; making i equal to i +1, and repeating the previous step until the detection unit detects that the received video signal is locked, or i equal to n; wherein n is the number of systems of the target video signal.
In an alternative embodiment, the larger i, the smaller Ni.
In an optional implementation manner, the detecting unit 530 is further configured to detect whether a color carrier of the received video signal is locked when the configuring unit 520 configures the register according to the first target system and detects that the received video signal is locked;
the determining unit 540 is specifically configured to determine, if the color carrier of the received video signal is locked, that the format of the received video signal is the first target format;
the determining unit 540 is further configured to determine that the received video signal is mis-locked if the color carrier of the received video signal is not locked.
In an alternative embodiment, as shown in fig. 6, the apparatus further comprises:
an adjusting unit 550, configured to set a range of gain adjustment to be maximum and adjust the gain to be maximum if the color carrier of the received video signal is not locked;
the detecting unit 530 is further configured to detect whether a color carrier of the received video signal is locked;
the determining unit 540 is specifically configured to determine that the received video signal is mis-locked if the color carrier of the received video signal is not locked.
In an optional implementation manner, the reading unit 510 is further configured to, when the configuration unit 520 configures the register according to a first target system and the detection unit 530 detects that the received video signal is locked, read a voltage value of a target row of a frame of the first target video signal if the frame rate of the first target video signal is half of the frame rates of other target video signals; wherein the target line is any one line between a preset number of lines above and below the middle line of the frame of the first target video signal;
the determining unit 540 is specifically configured to determine, if the voltage value of the target row is a non-negative value, that the format of the received video signal is the first target format;
the determining unit 540 is further configured to determine that the received video signal is mistakenly locked if the voltage value of the target row is a negative value.
In an alternative embodiment, the determining unit 540 is further configured to determine line lengths of the plurality of target video signals;
the configuration unit 520 is specifically configured to configure the register according to the system of each target video signal if the line lengths of the multiple target video signals are the same;
the determining unit 540 is further configured to determine, if the line lengths of the multiple types of target video signals are different, a format of the received video signal according to the line lengths of the multiple types of target video signals and the line length of the received video signal.
In an alternative embodiment, the reading unit 510 is further configured to read a line length value of a register;
the determining unit 540 is further configured to determine a format of the received video signal according to the line length value and the line length of each target video signal.
Fig. 7 is a schematic diagram of a hardware structure of an electronic device according to an embodiment of the present disclosure. The electronic device may include a processor 701, a communication interface 702, a memory 703, and a communication bus 704. The processor 701, the communication interface 702, and the memory 703 communicate with each other via a communication bus 704. Wherein, the memory 703 is stored with a computer program; the processor 701 may execute the video signal format identification method described above by executing a program stored on the memory 703.
The memory 703, as referred to herein, may be any electronic, magnetic, optical, or other physical storage device that can contain or store information such as executable instructions, data, and the like. For example, the memory 702 may be: a RAM (random Access Memory), a volatile Memory, a non-volatile Memory, a flash Memory, a storage drive (e.g., a hard drive), a solid state drive, any type of storage disk (e.g., an optical disk, a dvd, etc.), or similar storage medium, or a combination thereof.
The embodiment of the present application also provides a machine-readable storage medium, such as the memory 703 in fig. 7, storing a computer program, which can be executed by the processor 701 in the electronic device shown in fig. 7 to implement the video signal format identification method described above.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the scope of protection of the present application.
Claims (16)
1. A method for identifying a video signal format, comprising:
reading the standard value of the received video signal by reading the standard value of the register;
when the standard value is shared by target video signals of multiple standards, a register is configured according to at least one standard in the standards of each target video signal until the received video signal is locked;
when the register is configured according to a first target system and the received video signal is locked, determining the system of the received video signal as the first target system; wherein the first target format is a format of a first target video signal among the plurality of target video signals.
2. The method according to claim 1, wherein said configuring the register in at least one of the formats of the respective target video signals comprises:
and sequentially selecting the system in the systems of the target video signals, and configuring the register according to the selected system of the target video signals.
3. The method of claim 2, wherein said sequentially selecting the format of each target video signal format, configuring the registers according to the selected target video signal format, comprises:
determining the priority of the system of each target video signal;
and sequentially selecting the modes in the modes of the target video signals according to the sequence of the priority from high to low, and configuring the register according to the selected modes of the target video signals.
4. The method according to claim 3, wherein said sequentially selecting the formats in the formats of the respective target video signals in order of priority from high to low, configuring the register according to the selected format of the target video signal, comprises:
the system configuration registers of the ith target video signal are sorted according to the priority, until the received video signal is locked, or when the frequency of the system configuration registers of the ith target video signal sorted according to the priority reaches Ni, the received video signal is not locked; wherein, the initial value of i is 1, and the larger i is, the lower the priority is; i is more than or equal to 1 and less than or equal to n;
i +1, and repeating the previous step until the received video signal is locked, or i n; wherein n is the number of systems of the target video signal.
5. The method of claim 4, wherein the larger i, the smaller Ni.
6. The method according to any one of claims 1 to 5, wherein, when the register is configured according to a first target standard and the received video signal is locked, the determining that the standard of the received video signal is the first target standard comprises:
and if the color carrier of the received video signal is locked, determining the format of the received video signal as the first target format.
7. The method according to any one of claims 1-5, wherein after the registers are configured according to the first target format and the received video signal is locked, the method further comprises:
and if the color carrier of the received video signal is not locked, determining that the received video signal is wrongly locked.
8. The method of claim 7, wherein after determining that the color carrier of the received video signal is not locked, and before determining that the received video signal is mis-locked, further comprising:
adjusting the gain to compensate for the attenuation;
and if the color carrier of the received video signal is not locked, determining to execute the step of determining that the received video signal is locked by mistake.
9. The method of claim 8, wherein the adjusting the gain comprises:
the range of gain adjustment is set to maximum and the gain is adjusted to maximum.
10. The method according to any one of claims 1 to 5, wherein after the registers are configured according to a first target format and the received video signal is locked, the method further comprises before determining that the format of the received video signal is the first target format:
if the frame rate of the first target video signal is half of that of other target video signals, reading the voltage value of a target row of one frame of the first target video signal; wherein the target line is any one line between a preset number of lines above and below the middle line of the frame of the first target video signal;
if the voltage value of the target row is a non-negative value, determining to execute the step of determining that the format of the received video signal is the first target format;
and if the voltage value of the target line is a negative value, determining that the received video signal is locked by mistake.
11. The method according to any one of claims 1 to 5, wherein, after determining that the format value is shared by target video signals of a plurality of formats, before configuring the register in accordance with at least one format of formats of the respective target video signals, further comprises:
determining line lengths of the plurality of target video signals;
if the line lengths of the multiple target video signals are the same, determining to execute at least one mode configuration register in the modes according to each target video signal;
and if the line lengths of the various target video signals are different, determining the system of the received video signals according to the line lengths of the various target video signals and the line length of the received video signals.
12. The method of claim 11, wherein determining the format of the received video signal according to the line lengths of the plurality of target video signals and the line length of the received video signal comprises:
reading a line length value of a register;
determining the line length of the received video signal according to the line length value;
and determining the system of the received video signals according to the line length of the received video signals and the line length of each target video signal.
13. The method according to any of claims 1-5, wherein said locking of the received video signal comprises:
the line sync signal lock and the field sync signal lock of the received video signal are both locked.
14. A video signal format identifying apparatus, comprising:
the reading unit is used for reading the standard value of the received video signal by reading the standard value of the register;
the configuration unit is used for configuring a register according to at least one system in the system of each target video signal until the received video signal is locked when the system value is shared by the target video signals of multiple systems;
the determining unit is used for determining the format of the received video signal as the first target format when the configuration unit configures the register according to the first target format and the received video signal is locked; wherein the first target format is a format of a first target video signal among the plurality of target video signals.
15. The apparatus of claim 14,
the configuration unit is specifically configured to sequentially select the systems in the systems of the target video signals, and configure the register according to the selected system of the target video signal;
the configuration unit is specifically configured to determine priorities of systems of the target video signals; sequentially selecting the system in the systems of the target video signals according to the sequence of the priority from high to low, and configuring a register according to the system of the selected target video signal;
the configuration unit is specifically configured to configure a system configuration register of an ith target video signal according to a priority, until the received video signal is locked, or, when the number of times of the system configuration register of the ith target video signal according to the priority reaches Ni, the received video signal is still unlocked; wherein, the initial value of i is 1, and the larger i is, the lower the priority is; i is more than or equal to 1 and less than or equal to n; i +1, and repeating the previous step until the received video signal is locked, or i n; wherein n is the number of systems of the target video signal;
wherein, the larger i is, the smaller Ni is;
and/or the presence of a gas in the gas,
the determining unit is specifically configured to, when the configuration unit configures the register according to a first target standard and the received video signal is locked, determine that the standard of the received video signal is the first target standard if a color carrier of the received video signal is locked;
and/or the presence of a gas in the gas,
the determining unit is further configured to determine that the received video signal is mistakenly locked if a color carrier of the received video signal is unlocked after the configuration unit configures the register according to the first target system and the received video signal is locked;
wherein the apparatus further comprises:
an adjusting unit for adjusting a gain to compensate for attenuation after the determining unit determines that the color carrier of the received video signal is unlocked;
the determining unit is specifically configured to determine that the received video signal is locked by mistake if the color carrier of the received video signal is still unlocked;
the adjusting unit is specifically configured to set a range of gain adjustment to be maximum, and adjust the gain to be maximum;
and/or the presence of a gas in the gas,
the reading unit is further configured to, when the configuration unit configures the register according to a first target system and the received video signal is locked, read a voltage value of a target row of a frame of the first target video signal if the frame rate of the first target video signal is half of the frame rates of other target video signals; wherein the target line is any one line between a preset number of lines above and below the middle line of the frame of the first target video signal;
the determining unit is specifically configured to determine that the format of the received video signal is the first target format if the voltage value of the target row is a non-negative value;
the determining unit is further configured to determine that the received video signal is mistakenly locked if the voltage value of the target row is a negative value;
and/or the presence of a gas in the gas,
the determining unit is further configured to determine line lengths of the plurality of types of target video signals;
the configuration unit is specifically configured to configure the register according to at least one system type in the system types of the target video signals if the line lengths of the plurality of target video signals are the same;
the determining unit is further configured to determine, if the line lengths of the multiple target video signals are different, a format of the received video signal according to the line lengths of the multiple target video signals and the line length of the received video signal;
the reading unit is also used for reading the line length value of the register;
the determining unit is further configured to determine the line length of the received video signal according to the line length value and the line length of each target video signal, and determine the format of the received video signal according to the line length of the received video signal and the line length of each target video signal;
and/or the presence of a gas in the gas,
the received video signal lock, comprising:
the line sync signal lock and the field sync signal lock of the received video signal are both locked.
16. A video processing device, characterized in that it comprises an AD chip for implementing the method of any one of claims 1-13.
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