CN1698387A - Video signal processing circuit and video signal processing method - Google Patents
Video signal processing circuit and video signal processing method Download PDFInfo
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- CN1698387A CN1698387A CN 200480000185 CN200480000185A CN1698387A CN 1698387 A CN1698387 A CN 1698387A CN 200480000185 CN200480000185 CN 200480000185 CN 200480000185 A CN200480000185 A CN 200480000185A CN 1698387 A CN1698387 A CN 1698387A
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Abstract
In a digital chroma demodulating system, when directly outputting A/D converted composite signals, while switching system clock frequencies to determine the signal format, images to be displayed in accordance with the composite signals are prevented from varying and becoming unsightly due to the switching of system clock frequencies. As to the system clock frequency (m)(= fsc*n) for synchronization with a color burst signal, its coefficient (n) is changed in accordance with the format (a color burst signal frequency), thereby confining the system clock frequency (m) for formats within a given range. As a result, a nearly constant sampling frequency can be used to perform A/D conversions of the composite signals, so that sampling conditions such as the sampling frequency and sampling points will not significantly vary.
Description
Technical field
The present invention relates to video processing circuit, it has and is used for for example isolating luminance signal and carrier chrominance signal from vision signal (composite video signal) by so-called YC separating treatment, from the carrier chrominance signal of separating like this being carried out the circuit arrangement of demodulation process, the present invention also relates to the method for described treatment circuit.
Background technology
In television receiver, be provided with surveillance equipment and similar devices, for example chrominance demodulation system is used for isolating luminance signal (Y-signal) and carrier chrominance signal (C signal) from the composite video signal of input, and further from described chrominance demodulation color difference signal.In recent years, above-mentioned chrominance demodulation system is made of digital circuit, the chrominance demodulation that has therefore proposed and realized carrying out with Digital Signal Processing.
Above-mentioned digital color demodulating system is for example carried out Y/C and is separated, be used for after the composite video signal with input is converted to digital signal, being separated into luminance signal and carrier chrominance signal, also the carrier chrominance signal of separating is carried out chrominance demodulation and handle, thereby generate color difference signal Cb, Cr.As a result, the output of digital color demodulating system shows essential luminance signal and color difference signal for coloured image.
Then, the system clock as the above-mentioned digital color demodulating system of operation in order to extract the needs of color difference signal, carries out an operation with synchronous with the burst signal that is superimposed upon on the composite video signal.In this case, synchronous by executable operations the PLL Circuit lock is decided to be with the burst signal of extracting from composite video signal, generate the system clock that is used for described digital color demodulating system.
In addition, in many cases, the frequency that is used for the system clock of aforesaid digital color demodulating system is set to 4fsc, just four of the frequency f sc of burst signal times.This be because, when considering in described digital color demodulating system, to carry out described sampling when obtaining for described luminance signal and color difference signal sufficiently high quality, as the frequency that obtains after the frequency f sc that multiply by described burst signal, 4fsc is minimum essential frequency.
The block diagram schematic illustrations of Fig. 7 according to an example of the digital color demodulating system of above-mentioned configuration.
Here, as the chrominance demodulation system, known have a kind of system, and it is designed to decodable, not only corresponding to the input of the composite video signal by a specific television system (standard), and corresponding to the input of the composite video signal by multiple television system (standard).It is designed to carry out decoding processing, and for example corresponding to any composite video signal of the various standards of importing, described standard for example has TSC-system formula (system), pal mode (system) and Sequential Color and Memory system formula (system) etc. to this decoding processing.
Therefore, here to the explanation of the digital color demodulating system that is shown in Fig. 7 based on such hypothesis: it also uses the configuration corresponding to the multiple input of above-mentioned composite video signal.
System clock CLK is imported into the digital color demodulating system 100 that is shown in Fig. 7.According to the timing based on this system clock CLK, operation constitutes A/D converter 101, y/c separation circuit 103 and the chrominance demodulation circuit 104 of described digital color demodulating system 100.Here, this system clock CLK exports from the PLL circuit that described chrominance demodulation circuit 104 comprises.This PLL circuit generates and output and the synchronous system clock of described burst signal by being operating as corresponding to the burst signal of the composite video signal of described input and locked.Then, the frequency of system clock CLK in this case is assumed to 4fsc, as mentioned above.
For example, when importing the composite video signal of TSC-system formula, because the frequency f sc of burst signal is 3.58MHz, system clock frequency is 14.32MHz (=4 * 3.58MHz).In addition, when importing the composite video signal of pal mode, the frequency f sc of burst signal is 4.43MHz.Like this, system clock frequency is 17.72MHz (=4 * 4.43MHz).
The composite video signal that is input to digital color demodulating system 100 at first is imported into A/D converter 101.The composite video signal of 101 pairs of inputs of this A/D converter is carried out the A/D conversion according to the operation timing of determining according to the system clock of 4fsc, and digital composite video signal is outputed to the terminal T1 and the y/c separation circuit 103 of switching circuit 102.
The composite video signal of 103 pairs of inputs of this y/c separation circuit is carried out as the operation that for example forms the comb filter of digital circuit, thus luminance signal of being separated into (Y-signal) and carrier chrominance signal (C signal).Described luminance signal is output to the terminal T2 of commutation circuit 102, and described carrier chrominance signal is output to described chrominance demodulation circuit 104.
This chrominance demodulation circuit 104 carries out decoding processing by a Digital Signal Processing to the carrier chrominance signal of input, output color difference signal Cr and Cb.
Described commutation circuit 102 is carried out and is switched, and makes terminal T3 alternately be connected to terminal T1 or terminal T2.Under general case, terminal T3 is connected to terminal T2.
Thereby, luminance signal and color difference signal Cr, Cb that 100 outputs of digital color demodulating system are extracted from the composite video signal of input.
Here, the setting of commutation circuit 102 is corresponding to such fact: the configuration of digital color demodulating system 100 that is shown in Fig. 7 is corresponding to a plurality of inputs of composite video signal.
Under the situation corresponding to a plurality of inputs of composite video signal, have such situation: the television system of the input composite video signal that import for example switches to pal mode from the TSC-system formula.
Like this, when the television system of the composite video signal that will import is switched, when having changed the frequency of the color that will import, perhaps when burst signal did not have to insert the composite video signal that will import, described digital color demodulating system 100 entered the television system decision.
Carry out as mentioned above television system judgement during be under the situation that can not generate the system clock CLK that meets the input composite video signal.Like this, owing to can not separate and the chrominance demodulation processing by correct execution Y/C, can not export luminance signal and color difference signal Cr, Cb.
Therefore, during the decision of carrying out television system, in commutation circuit 102, terminal T1 and terminal T2 couple together.Thereby, replacing luminance signal, the composite video signal (CVBS signal) after the A/D conversion is directly outputed to the video signal processing system in the back one-level.Like this, for example,, also can keep showing output based on the image of vision signal although be the black and white image screen.
Here, a briefly description is done in the execution of aforesaid television system decision below.
For example, suppose the composite video signal of beginning, perhaps do not insert the composite video signal of burst signal to the digital color demodulating system 100 inputs television system different with previous television system.
In these cases, in digital color demodulating system 100 1 sides, the frequency of system clock switched to presupposes the pairing frequency of television system (4fsc) that every several vertical-scan period will import, with judge described input composite video signal based on television system (system).
For example, at first, to the frequency setting of system clock CLK 4fsc frequency 14.32MHz, operand word chrominance demodulation system 100 corresponding to the TSC-system formula.Because this operation, as mentioned above, chrominance demodulation circuit 104 included PLL circuit are surveyed it and whether can be locked into burst signal.Here, if the composite video signal of input is based on the TSC-system formula, then described PLL circuit obtains the convergence operation so that be locked into burst signal, and judges that the composite video signal of current input is based on the TSC-system formula.Afterwards, based on the system clock CLK of this 14.32MHz, operand word chrominance demodulation system 100.
On the contrary, even in the past corresponding to after the vertical-scan period several times,, next, for example, the frequency of system clock is switched to 4fsc=17.72MHz corresponding to the PAL system if the PLL circuit can not obtain to be locked into the state of burst signal.Be similar to above-mentioned situation, whether the PLL circuit is surveyed can be locked into burst signal in corresponding to the described vertical-scan period several times.
Here, according to the explanation in conjunction with Fig. 7, during finishing the decision of television system, from described digital color demodulating system 100, the composite video signal that is converted to digital signal by A/D converter 101 is directly exported by commutation circuit 102.Then, just become situation about showing by this composite video signal carries out image.
Then, at this moment, as mentioned above, carry out the switching of system clock frequency according to described television system.But, in the TSC-system formula, be 14.32MHz for example as the system clock frequency of 4fsc, in pal mode 17.72MHz.Just, when reality was carried out the decision of television system, even at least between TSC-system formula and pal mode, system clock frequency changed 20% or more in each vertical-scan period corresponding to several times.
Then, change significantly in response to system clock frequency is aforesaid, sampled point in the A/D converter 101, sample frequency etc. change, thereby this causes the variation of observed image by the composite video signal that is used for showing after the output A/D conversion.
Particularly, change apparent frequency characteristic (appearance frequencycharacteristic) with expansion or give up it.In addition, can change because the appearance of returning the corrugated portion that causes of high-frequency signal part.Then, during corresponding to each vertical-scan period of several times, frequently change the variation in the aforesaid image.Like this, on the shown image vision with regard to variation.
Especially insert under the situation of black and white composite video signal for example not inserting the burst signal signal, above-mentioned phenomenon can become serious problem.
In other words, by whether judging burst signal, carry out aforesaid decision about television system at lock-out state.Like this, if burst signal is not inserted as the black and white composite video signal the then switching of duplicated system clock frequency constantly.Like this, in this case, the image of the variation visually of the demonstration frequent variations that continues.
Like this, in the digital color demodulating system that disposes corresponding to a plurality of inputs of composite video signal, the switching of the system clock frequency that for example, is associated with the decision of television system, carry out has inevitably caused when the switched system clock frequency interference to display image.
Summary of the invention
Therefore, in the present invention, consider the problems referred to above, designed video processing circuit as described below.
In other words, this video processing circuit comprises: analog-digital commutator, can import the frequency of burst signal of standard different close vision signal, be used for: sample by using, thereby the composite video signal as analog signal that will import is converted to the composite video signal as digital signal according to the sample frequency of system clock; Apparatus for processing of video signals, be used for, according to predetermined timing based on described system clock, the YC separating treatment of luminance signal and carrier chrominance signal is isolated in execution from the described composite video signal as described digital signal, and the chrominance demodulation processing of the described carrier chrominance signal that described YC separating treatment is obtained being carried out demodulation; And system clock generating means, be used to generate and the synchronous described system clock of burst signal that extracts from described composite video signal, and be configured to standard according to the described composite video signal that is input to described apparatus for processing of video signals and change and a coefficient n is set, make, in the frequency of described burst signal is that fsc, coefficient are that the frequency m of n and described system clock is expressed as under the situation of fsc * n=m, and frequency m falls into the preset range between the described different systems.
In addition, designed a kind of video signal processing method, as described below.
In other words, this video signal processing method is designed to carry out: analog-to-digital conversion process, can import the different composite video signal of frequency of the burst signal of standard, be used for: sample by using, thereby the composite video signal as analog signal of described input is converted to composite video signal as digital signal according to the sample frequency of system clock; Vision signal is handled, be used for, according to predetermined timing based on described system clock, the YC lock out operation of luminance signal and carrier chrominance signal is isolated in execution from the described composite video signal as described digital signal, and the chrominance demodulation operation of the described carrier chrominance signal that described YC separating treatment is obtained being carried out demodulation; And system clock is handled, be used to generate and the synchronous described system clock of burst signal that extracts from described composite video signal, and be configured to standard according to the described composite video signal that is input to described apparatus for processing of video signals and change and a coefficient n is set, make, in the frequency of described burst signal is that fsc, coefficient are that the frequency m of n and described system clock is expressed as under the situation of fsc * n=m, and frequency m falls into the preset range between the described different systems.
In above-mentioned configuration, at first,, can carry out the Digital Signal Processing of carrying out chrominance demodulation corresponding to a plurality of inputs (in composite video signal, type is difference with the difference of the frequency of burst signal) of composite video signal.
Then, under this configuration, the frequency of the system clock that is used for the chrominance demodulation processing that following setting and described burst signal are synchronous.Just, (fsc is the frequency of burst signal when system clock frequency m is expressed as m=fsc * n, n is a coefficient) time, by changing corresponding to type (burst signal frequency f sc) and coefficient n being set, attempt making dissimilar between the frequency m of system clock drop in the constant scope.In other words, no matter the type of composite video signal, the frequency m of system clock is set to about equally.
Thereby even the composite video signal of importing as the target of chrominance demodulation processing by Digital Signal Processing is any kind (in other words, any burst signal frequency), it can be changed by A/D according to the sample frequency of substantial constant.In addition, for this reason, sampling condition such as sample frequency, sampled point etc., does not have big variation between dissimilar separation signals.
Description of drawings
The block diagram illustration of Fig. 1 as a configuration example of the digital color demodulating system of embodiments of the invention;
Fig. 2 is a sequential chart, illustrates 1/5 fen sample to composite video signal of carrying out and handle in the digital color demodulating system of this embodiment;
Fig. 3 is a sequential chart, illustrates 1/4 fen sample to composite video signal of carrying out and handle in the digital color demodulating system of this embodiment;
The block diagram illustration of Fig. 4 be the configuration of the digital color demodulating system of 4fsc according to system clock, corresponding to a configuration example under the situation of the input of composite video signal;
The block diagram illustration of Fig. 5 be the configuration of the digital color demodulating system of 4fsc according to system clock, corresponding to a configuration example under the situation of the input of composite video signal;
The view of Fig. 6 is used for explaining each television system of the digital color demodulating system correspondence of present embodiment, burst signal frequency f sc, 4fsc and system clock frequency;
The block diagram illustration of Fig. 7 as a configuration example of traditional digital color demodulating system.
Embodiment
The chrominance demodulation system as video processing circuit as one embodiment of the present of invention is described below.
The chrominance demodulation system of present embodiment for example is included in the television receiver and surveillance equipment, be designed to: as demodulation process composite video signal, carry out Y/C separating treatment and chrominance demodulation processing by Digital Signal Processing, thereby output is as the color difference signal of the luminance signal of digital signal.
In addition, the chrominance demodulation system of present embodiment is corresponding to a plurality of inputs of composite video signal.In other words, it is designed to the input corresponding to the composite video signal of different television systems, carries out the demodulation process (Y/C separating treatment and chrominance demodulation are handled) of composite video signal.
Following explanation is carried out according to following order:
1. system clock frequency;
2. the configuration of digital color demodulating system;
3. the pairing configuration of a plurality of inputs of component signal.
1. system clock frequency
Here, in the digital color demodulating system that is configured to corresponding to a plurality of inputs of the composite video signal of describing in the prior art before this, it is said that the interference to image that switching by the system clock frequency relevant with the decision operation of television system causes is from following factor.
In other words, based on the frequency difference of the system clock between the television system, the sampled point when A/D changes and the deviation of sample frequency have been amplified to the degree that visually can be identified as the interference of image.
Therefore, only need to be provided with system clock frequency, make the sampled point when carrying out the A/D conversion and the deviation of sample frequency be reduced to the degree that visually is not aware of the interference of image corresponding to each television system.
In other words, this means that for the system clock frequency of each television system, the sampled point when making the A/D conversion and the departure of sample frequency drop in the necessary scope, even its difference on the frequency can be set in the predetermined scope.
Below in conjunction with accompanying drawing 6 setting to the system clock frequency of each television system is described as mentioned above.
Here, as the digital color demodulating system of present embodiment should be corresponding the television system of composite video signal, for example, as shown in Figure 6, suppose to have 7 kinds: NTSC, NTSC-443, PAL, PAL-M, PAL-N, PAL-60 and SECAM.
Find then, belong to 3.58MHz and 4.43MHz any group corresponding to each the frequency f sc of burst signal of described television system.So, as the digital color demodulating system, be used as the system clock synchronous with described burst signal from the output of the PLL circuit of the frequency f sc that locks onto this burst signal.Like this, system clock need be the multiple of frequency f sc.
Therefore, as system clock frequency, when burst signal fsc=3.58MHz and fsc=4.43MHz are carried out respectively predetermined multiplication and relatively they the time.All drop on the result who obtains under the situation in the above-mentioned preset range as shown in Figure 6 two frequencies.
In other words, as system clock frequency, for burst signal frequency f sc=3.58MHz, fsc be multiply by 20, be increased to 71.6MHz (=20fsc), for burst signal frequency f sc=4.43MHz, fsc be multiply by 16, be increased to 70.88MHz (=16fsc).In this case, the difference between two frequencies is 0.72MHz, and mutual rate of change is about 1%.
In this case, as the system clock frequency of the two, for example, when as the composite video signal after the image output A/D conversion, under the situation that the annoyance level with image compares, they approximately are 71MHz, can be regarded as substantial constant.
As a comparison, in Fig. 6, also illustrate the prior art system clock frequency (=4fsc).Being 14.32MHz under the situation of fsc=3.58MHz, is 17.72MHz under the situation of fsc=4.43MHz, and difference is 3.4MHz, and this shows about 20% rate of change.Just, has difference on the frequency greater than the situation of this embodiment.In other words, the difference on the frequency of the system clock among this embodiment is very little.
In addition, the system clock frequency of setting in this embodiment as mentioned above is 71.6MHz=20fsc and 70.88MHz=16fsc.But they can be represented as:
20fsc＝5×4fsc
16fsc＝4×4fsc
In them any one can obtain by 4fsc being multiply by an integer.Thereby the processing such as chrominance demodulation in the digital color demodulating system of this embodiment that will describe below designed to be able to also that use can be at the available circuit of the clock work of 4fsc.
2. the configuration of digital color demodulating system.
Then, at first describe digital color demodulating system among this embodiment in conjunction with Fig. 1, it is designed to the system clock work at the about 71MHz (71.6MHz or 70.88MHz) that is provided with as mentioned above.
Be shown in the configuration of digital color demodulating system 1 application of Fig. 1 corresponding to the input of the composite video signal of the various television systems that for example are shown in Fig. 6.
Although to the composite video signal of digital color demodulating system 1 input as analog signal, the actual simulation LPF (low pass filter) 2 that is imported into the previous stage that places digital color demodulating system 1 of this composite video signal.
Here, digital color demodulating system 1 is based on the system clock CLK work of about 71MHz (71.6MHz or 70.BBMHz), and the sample frequency of the A/D converter that will describe is approximately 71MHz below.For this reason, the frequency band of the analog composite video signal that import need roughly be in half Nyquist frequency (Nyquistfrequency) scope of about 35MHz of 71MHz.The setting of described simulation LPF2 is in order to eliminate high fdrequency component, so that analog composite video signal drops in about 35MHz or the following frequency band.For this reason, be set to simulate the cut-off frequency of LPF2 near the desired value of 35MHz.
Analog composite video signal by this simulation LPF2 is imported in the A/D converter 11 of digital color demodulating system 1, sample frequency based on aforesaid about 71MHz (71.6MHz or 70.88MHz) is converted into digital signal, is output to the digital LPF12 in the back one-level then.
As cut-off frequency, described digital LPF12 eliminates frequency and is higher than band component as the frequency band of luminance signal from described composite video signal, by the signal that obtains corresponding to the about 7MHz that is included in the luminance signal in the described composite video signal in setting.Thereby,, suitably carry out the Y/C separating treatment by the following y/c separation circuit that will describe.
Composite video signal by described digital LPF12 is branched and is input to the terminal T1 of commutation circuit 13 and divides sample circuit 14.
Here, the operation that the chrominance demodulation that the Y/C separating treatment of being carried out by y/c separation circuit 15 that will describe below and chrominance demodulation circuit 16 are carried out is handled be not based on system clock CLK71.6MHz corresponding to burst signal frequency f sc=3.58MHz (=20fsc) or corresponding to the 70.88MHz of burst signal frequency f sc=4.43MHz (=16fsc), but they are configured to the clock work based on 4fsc.
In other words, as shown in Figure 7, traditionally, the execution that Y/C separating treatment and chrominance demodulation are handled is based on the system clock of 4fsc.For those y/c separation circuits 15 and chrominance demodulation circuit 16, the operation of the type that present embodiment uses is based on the 4fsc system clock that is used to use the technology that existing Y/C separating treatment and chrominance demodulation handle.Like this, because main hardware does not require that cost increase has correspondingly just been avoided corresponding to the configuration of new system clock frequency.
But, be about 71MHz (71.6MHz or 70.88MHz) to the sample frequency of composite video signal sampling, this frequency is system clock CLK.Like this, in the previous stage of Y/C separating treatment, need handle so that meet with respect to the coupling of sample frequency based on the Y/C separating treatment and the chrominance demodulation of 4fsc clock.
At first, the burst signal frequency f sc for the composite video signal of importing at first describes the operation of branch sample circuit 14 under the situation of fsc=3.85MHz in conjunction with Fig. 2.
In this case, after multiply by fsc=3.58MHz with 20, the frequency of system clock CLK be 71.6MHz (=20fsc).So, in by the A/D converter 11 A/D sampled data (CV0 is to CV15...) according to the composite video signal after carrying out digitlization based on the sample frequency of this system clock CLK, sample is corresponding to each cycle of system clock CLK, as shown in Figure 2.
Here, the clock of input 4fsc is enabled signal EN as what produce sampling timing, is imported into branch sample circuit 14.The clock of 4fsc becomes 4 * 3.58MHz=14.32MHz in this case.
Then, for example can use divider (not shown) that system clock CLK is divided into 1/5 and obtain this 4fsc clock.Perhaps, because the oscillator signal from VCO23 output that will be described below is 4fsc, this signal can be used as clock signal.
Here, when 20fsc relatively (=71.6MHz) system clock and 4fsc (=14.32MHz) enable signal EN the time, enable cycle of 1/5 that signal EN has burst signal, be shown below:
20fsc/4fsc＝5
In other words, for example, suppose constantly A/D sampled data CVO to be sampled in the rising of enabling signal E N at moment t1.Then, at the rising of enabling signal EN as next one moment t2 constantly, the 5th A/D sampled data CV5 from A/D sampled data CV0 is sampled.
Afterwards, similarly,, the 5th A/D sampled data CV10 from A/D sampled data CV5 is sampled at the rising of enabling signal EN as next one moment t3 constantly.Then, at the rising of enabling signal EN as next one moment t4 constantly, the 5th A/D sampled data CV15 from A/D sampled data CV10 is sampled.
Because above-mentioned sampling operation as shown in Figure 2, as the sampled data row after handling through undue sample, is told sampled data by per five data from original A/D sampled data row and is obtained, such as sampled data CV0, CV5, CV10, CV15 ...In other words, original A/D sampled data being carried out 1/5 fen sample handles.The sampled data that obtains after minute sample is handled is equivalent to the data based on the sample frequency sampling acquisition of 4fsc so, by this way.
Next, the burst signal frequency f sc that describes when the composite video signal that will import in conjunction with Fig. 3 is the operation of fsc=4.43MHz time-division sample circuit 14.
In this case, by fsc=4.43MHz being multiply by the frequency of 16 acquisition system clock CLK.Then, for this situation, the A/D sampled data (CV0 is to CV15...) of A/D converter 11 digitized composite video signals is sampled based on sample frequency according to system clock CLK.Like this, as shown in Figure 3, sampling is corresponding to each cycle of system clock CLK.
As mentioned above, be input to the clock that signal EN has 4fsc of enabling of branch sample circuit 14.So, in this case, 4fsc=4 * 4.43MHz=17.72MHz.
So, in this case, when 16fsc relatively (=71.6MHz) system clock and 4fsc (=14.32MHz) enable signal EN the time, enable cycle of 1/4 that signal EN has burst signal CL, be shown below:
4fsc/16fsc＝1/4
Like this, because described minute sample circuit 14 carried out sampling constantly in this rising of enabling signal, A/D sampled data (CV0 is to CV15...) is carried out 1/4 fen sample handle.
In other words, for example, suppose constantly A/D sampled data CVO to be sampled in the rising of enabling signal EN at moment t1.Then, at the rising of enabling signal EN as next one moment t2 constantly, the 4th A/D sampled data CV4 from A/D sampled data CV0 is sampled.Afterwards, similarly,, another the 4th A/D sampled data CV8 from A/D sampled data CV4 is sampled at the rising of enabling signal EN as next one moment t3 constantly.Then, at the rising of enabling signal EN as next one moment t4 constantly, the 4th A/D sampled data CV12 from A/D sampled data CV8 is sampled.
Like this, as the sampled data row after handling through undue sample, tell sampled data by per four data from original A/D sampled data row and obtain, such as sampled data CV0, CV4, CV8, CV12....Press, even in this case, the sampled data that obtains after minute sample is handled is equivalent to the data based on the sample frequency sampling acquisition of 4fsc.
Return Fig. 1 below.
The composite video signal (sampled data) that obtains in minute sample circuit 14, sample based on the sample frequency of 4fsc as mentioned above is imported into y/c separation circuit 15.
As mentioned above, in the moment based on the clock of 4fsc, the composite video signal of 15 pairs of inputs of this y/c separation circuit is carried out the Y/C separating treatment, and output luminance signal (Y-signal) and carrier chrominance signal (C signal).
Described luminance signal is output to the terminal T1 of commutation circuit 13.Described carrier chrominance signal is output to the chrominance demodulation circuit 16 in the chrominance demodulation module 30.This carrier chrominance signal also is output to burst signal RAM21.
This chrominance demodulation module 30 has chrominance demodulation circuit 16 and PLL module 31, as shown in Figure 1.
The carrier chrominance signal of 16 pairs of inputs of this chrominance demodulation circuit is carried out demodulation process in the moment based on the clock of 4fsc.Like this, here, it produces and output color difference signal Cb, Cr.
In addition, described PLL module 31 is formed by burst signal RAM21, LPF22, VCO23 and PLL circuit 24, constitute so-called APC (automatic phase control, Auto PhaseControl), wherein, as the operation of PLL Circuits System, it is locked into the burst signal that is comprised in the carrier chrominance signal.
Here, for the frequency of system clock CLK among this embodiment, as mentioned above, be 20fsc=71.6MHz corresponding to burst signal frequency f sc=3.58MHz, and corresponding to the 16fsc=71.6MHz of fsc=4.44MHz.But any one in them can obtain by multiply by 4fsc (* 5 or * 4) with an integer.
Like this, as mentioned above, based on the y/c separation circuit 15 of the clock work of 4fsc, chrominance demodulation circuit 16 etc. easily based on the system clock CLK work of present embodiment.
In other words, in practice, when system clock CLK is 20fsc=71.6MHz, for example, can obtain the clock of 4fsc with execution such as divider 1/5 division.Like this, if because the integral multiple of system clock CLK 4fsc, can use based on the configuration of the signal processing of 4fsc and without any special problem.
Described burst signal RAM21 storage is as the burst signal of the sampled data of sampling based on the 4fsc sample frequency of input.Cun Chu sampled data has the phase information of described burst signal like this.
Then, restricted band to be enabling stable phase angle as the sampled data of this burst signal by the LPF22 based on predetermined cut-off frequency and detect by making, and is imported into VCO23.Thereby operation VCO23 is with the oscillator signal of the Frequency Synchronization of output frequency and described burst signal.Additional disclosure, here, the frequency of oscillation of exporting from VCO23 is set to 4fsc.But, if the Frequency Synchronization of it and burst signal, then 4fsc not necessarily.But, enable signal EN from what above-mentioned explanation was appreciated that the clock of 4fsc is used to branch sample circuit 14, and further be used in during Y/C separating treatment and chrominance demodulation handle.Like this, for this point, if the frequency of oscillation of hypothesis VCO23 is 4fsc, described oscillator signal preferably is used as clock with its initial condition.Be imported into PLL circuit 24 from the oscillator signal of the 4fsc of VCO23 output.Operation PLL circuit 24, with the oscillator signal of locking from the 4fsc of VCO23 input, thus the synchronous system clock CLK of generation and output and burst signal.
Here, generate the frequency of the oscillator signal that is input to described PLL circuit 24 based on the described burst signal component of the composite video signal of carrying out 1/5 fen sample or 1/4 fen sample by described minute sample circuit 14.
Thereby, corresponding to the system clock CLK of following situation generation 20fsc=71.6MHz.This situation is: the burst signal frequency of supposing the composite video signal that will import is fsc=3.58MHz, then divides sample circuit 14 to carry out 1/5 fen sample and handles, multiply by 5 from the oscillator signal of the 4fsc of VCO23 input.
In addition, generate the system clock CLK of 16fsc=70.88MHz corresponding to following situation.This situation is: the burst signal frequency of supposing the composite video signal that will import is fsc=4.43MHz, then divides sample circuit 14 to carry out 1/4 fen sample and handles, multiply by 4 from the oscillator signal of the 4fsc of VCO23 input.
Like this, the digital color demodulating system 1 in the present embodiment is designed to: switch to divide in branch sample operation in the sample circuit 14 and the PLL circuit 24 multiplication to the oscillator signal of 4fsc in linkage.
Then, under the situation of the input that switches to the different composite video signal of burst signal frequency f sc, for example under the situation of the television system of switching the composite video signal of importing between TSC-system formula and the pal mode, can be by having above-mentioned configuration carry out television system decision (colored judge color determination) corresponding to the digital color demodulating system 1 of a plurality of inputs of described composite video signal.
In addition, for example,, also carry out the operation of judging television system even when the common composite video signal of inserting burst signal (colour-video signal) switches to the input of the black-and-white video signal that does not insert burst signal.In other words, if condition (such as whether having burst signal, perhaps frequency in the composite video signal that will import) changes, then can not obtain between system clock CLK and the burst signal synchronously.In this case, the television system of the composite video signal that import is regarded as having changed, and advances to the decision of television system.
The execution of the decision of television system is for example as described below.
Whether the DSP (Digital Signal Processor, digital signal processor) 3 that is shown in Fig. 1 for example can discern PLL circuit 24 at lock-out state.Then, when DSP3 identified described PLL circuit 24 and becomes unlocked state in response to the switching of the composite video signal that will import, it began the decision of television system.Then, as the decision of television system, DSP3 controls the oscillation signal frequency of exporting from VCO23 corresponding to each scan period switching in several vertical-scan periods as 4fsc.Here, for each scan period, the frequency of the oscillator signal of the VCO23 that switch be corresponding to digital color demodulating system 1 should be corresponding the 4fsc of burst signal of television system.
Operate described PLL circuit 24 with the oscillator signal of input, and synchronously lock with the sampled data of the burst signal that will be input to burst signal RAM21 from the 4fsc of this VCO23.
Additional disclosure, especially in the present embodiment, described television system is corresponding to 7 kinds of standards, equally as shown in Figure 6.But,, have only two kinds: fsc=3.58MHz and 4.43MHz as the burst signal in the composite video signal that is inserted in these 7 kinds of television systems.Like this, as the oscillator signal of 4fsc, also have two kinds: 14.32MHz (=4 * 3.58MHz) and 17.72MHz (=4 * 4.43MHz).Like this, DSP3 reality is carried out such control to VCO23, feasible oscillator signal to each scan period output 4fsc=14.32MHz and 4fsc=17.72MHz.
Here, for example, suppose under the control of DSP3 that at first, VCO23 exports the oscillator signal of 4fsc=14.32MHz in a scan period.At this moment, if the frequency of the burst signal of the composite video signal of input is fsc=3.58MHz, then PLL circuit 24 is locked in the state of the system clock CLK of output 71.6MHz, rather than is locked in fsc=3.58MHz (for example fsc=4.43MHz).
In fact, if PLL circuit 24 is locked in this scan period, afterwards, be fixed from the oscillator signal output of the 4fsc=14.32MHz of VCO23, thereby this continues the operation of digital color demodulating system 1 based on the system clock CLK of 71.6MHz.
On the contrary, if when the oscillator signal of VCO23 output 4fsc=14.32MHz in this scan period PLL circuit 24 not locked, then DSP3 will switch to 17.72MHz from 14.32MHz from the oscillator signal of the 4fsc of VCO23 output.Under this condition, be similar to above-mentionedly, judge whether PLL circuit 24 becomes lock-out state.
Like this, for the judgement of television system,, and carry out scan operation and judge whether PLL circuit 24 is locked into the burst signal of the composite video signal that will import the switching of each scan period execution clock frequency.Then, before PLL circuit 24 is locked, repeat this operation.
So, because above-mentioned scan operation, described digital color demodulating system 1 is worked on the basis of the system clock CLK of the television system that meets composite video signal.So, more specifically, the judgement of for example following execution television system.Here, for purposes of simplicity of explanation, between as the TSC-system formula of television system and pal mode, to judge as an example.
Under the composite video signal of importing the TSC-system formula, PLL circuit 24 blocked states, for example, owing to sample by the clock of 4fsc in minute sample circuit 14, for example, the value of the sampled data of R-Y component is near 0.
On the contrary, if the composite video signal of pal mode is carried out sampling based on the clock of 4fsc, then PLL circuit 24 is locked in the states of phase place with respect to situation skew 90 degree of NTSC.For this reason, in the amplitude peak value of the value advancing color synchronizing signal of the sampled data of the situation R-Y of pal mode component.In addition, in pal mode, the phase place of carrier chrominance signal is inverted for each horizontal scanning period.Like this, each horizontal scanning period of range value as the sampled data in the R-Y component also is being inverted aspect the positive negative value.
Subsequently, DSP3 visits the sampled data that each horizontal scanning period (1H) is input to the burst signal of burst signal RAM21.Then, for example,, then be judged to be the TSC-system formula if the integrated value of the sampled data of R-Y component is 0 in each horizontal scanning period.
On the contrary, if reverse, thereby the integrated value of the sampled data of R-Y component is-A (A represents the actual integration value) in certain horizontal scanning period, and the integrated value of the sampled data of the R-Y component in the next horizontal scanning period is+A (A represents the actual integration value), then is judged to be pal mode.
But, may have such situation: have error among the actual frequency fsc of the burst signal in the composite video signal that import.In this case, for example, in the TSC-system formula, the sampled data of R-Y component not necessarily accurately is 0, but one is different from 0 value.In addition, the sampled data of R-Y component also has the value different with normal value in the pal mode.
But under the situation of TSC-system formula, at each horizontal scanning period, it is the same that the error of the sampled data of above-mentioned R-Y component becomes.Like this, for each horizontal scanning period, the error amount of the sampled data of R-Y component becomes constant, for example is 0+ α ((α is worth accordingly with error).Therefore, if calculate poor between the integrated value of sampled data of previous horizontal scanning period and each R-Y component of present level in the scan period,, then can be judged to be the TSC-system formula if this difference is 0.
On the contrary, in pal mode, for each horizontal scanning period, the error amount of the sampled data of R-Y component is-A-β and+A+ β (β is the value corresponding to error).Like this, every a horizontal scanning period be-A-β or+A+ β, roughly be constant.Therefore, when poor between the integrated value of the sampled data of calculating previous horizontal scanning period and each R-Y component of present level scan period, if the value that calculates be not 0 and also previous horizontal scanning period and present level between the scan period positive negative value opposite, can be judged to be pal mode.
In other words, even have error among the burst signal frequency f sc, also can carry out the judgement of television system accurately.
Here, in being shown in the digital color demodulating system 1 of Fig. 1, in 24 lockings of PLL circuit generally, suitably carry out Y/C separating treatment and chrominance demodulation processing by y/c separation circuit 15, chrominance demodulation circuit 16 etc.Under this state, obtain normal brightness signal and color difference signal Cb, Cr.
At this time, terminal T2 and terminal T3 are connected to commutation circuit 13.Thereby, be output from terminal T3 by the composite video signal of input is suitably carried out the luminance signal that the Y/C separating treatment obtains.Then, with color difference signal Cb, the Cr from chrominance demodulation circuit 16 outputs, suitably display image.On the contrary, for example, under the pattern of the decision of carrying out television system, be appreciated that not locking of PLL circuit 24 from above-mentioned explanation, this causes obtaining the system clock CLK synchronous with burst signal.Therefore, digital color demodulating system 1 can not correctly be carried out Y/C separating treatment, chrominance demodulation processing etc.In other words, owing to can not export normal brightness signal and color difference signal, these signals can not be used for showing and exporting normal coloured image.
Therefore, when carrying out the decision of television system, switch described commutation circuit 13 so that terminal T1 and terminal T3 are connected.
Thereby digital color demodulating system 1 is exported digitized composite video signal (CVBS signal) by A/D converter 11 → digital LPF12, and this composite video signal makes the image demonstration to continue.
From as can be known above-mentioned, during the decision of television system, under the state of direct output composite video signal, digital color demodulating system 1 is carried out the operation of the frequency of switched system clock CLK as mentioned above (just from the 4fsc of VCO23 oscillation signal frequency).
Aforesaid operations even undertaken by conventional digital chrominance demodulation system corresponding to a plurality of inputs.But traditionally, because the frequency of system clock CLK is restricted to 4fsc, the difference on the frequency of the 4fsc that switch is very big.Therefore, the degree of state of the curl of the signal that each time during the frequency of switched system clock CLK, it changes to the variation that can visually perceive frequency characteristic, return etc.This is because the sample frequency when A/D changes composite video signal, sampled point etc. have very big deviation based on the difference on the frequency of aforesaid system clock CLK.
So, such problem is highly significant under the situation of input black-and-white video signal (wherein, not inserting burst signal in compound signal).In other words, under the situation of input black-and-white video signal, because the mechanism of the decision of television system, not existing of burst signal causes carrying out continuously the frequency handover operation, as described television system decision.In this case, traditionally, the variation of aforesaid image (for example corresponding to several vertical-scan periods each time) continually takes place, the image that this causes display quality continuously to be degenerated.On the contrary, in the digital color demodulating system 1 of present embodiment, as mentioned above, system clock CLK be specially corresponding to the 71.6MHz of burst signal frequency f sc=3.58MHz (=20fsc), and corresponding to the 70.88MHz of burst signal frequency f sc=4.43MHz (=16fsc).As a result, the difference on the frequency as sharing system clock CLK drops in the constant scope.
Therefore, when carrying out the switching of the system clock CLK relevant with the television system decision, compare with traditional situation, the deviation of the sample frequency of A/D converter 11, sampled point etc. has reduced.
The result, in this embodiment, because the composite video signal of exporting from digital color demodulating system 1 during the television system decision is as the image of actual displayed and output, because the interference that the switching of the frequency of system clock CLK causes is suppressed to visually imperceptible degree.
In addition, as the television system decision of the digital color demodulating system 1 among this embodiment, when input during black-and-white video signal, the handover operation of executive system clock CLK continuously.But in this embodiment, even under these circumstances, because the interference in the display image that the switching of the frequency of system clock CLK causes also is difficult to take place, thereby image becomes visuality is arranged very much.
In addition, because less corresponding to the difference on the frequency of the system clock CLK of each television system, the digital color demodulating system 1 among this embodiment has following advantage.
As shown in Figure 1, digital color demodulating system 1 comprises that the composite video signal that is used to make after A/D changes meets the digital LPF12 of the frequency band of luminance signal.
Here, because its configuration, the cut-off frequency and the clock frequency of digital filter change pro rata.Like this, for example, be similar to traditional situation, because the frequency of system clock CLK is set to 4fsc, if the difference on the frequency of the system clock CLK of each television system is bigger, cut-off frequency that then should numeral LPF is bigger for the variation of each television system.For this reason, in practice, need to use the mechanism that special digital LPF is provided corresponding to each frequency of the system clock CLK that will switch.In this case, use such mechanism and can make the circuit yardstick become bigger, this for example causes expense correspondingly to increase.
On the contrary, in this embodiment, very approaching near 71MHz corresponding to the frequency of the system clock CLK of each television system.Like this, even the frequency of switched system clock CLK, the cut-off frequency among the digital LPF12 is also in less level, thereby can be not influential to the use of reality.Therefore, in the present embodiment, even for internal digital filter etc., also can be so that an element is used jointly by the composite video signal of different television systems.
3. corresponding to the configuration of a plurality of inputs of composite video signal
Simultaneously, as the vision signal that is different from composite video signal, for example also know important signal.Therefore, in the digital color demodulating system, can consider such configuration: add the function of not only handling composite video signal but also handling component signal to it.
Thereby, at first, in Fig. 4, illustrate and in the digital color demodulating system 100 of the traditional example of conduct shown in Figure 7, added a kind of configuration example of handling the function of component signal.Additional disclosure in being shown in the digital color demodulating system 100 of Fig. 4, has been omitted the chrominance demodulation circuit configuration that is used for composite video signal shown in Figure 7, just selects and illustrates the part relevant with the processing of composite video signal.
For example, in practice, by the component signal of system handles shown in Figure 4 between 480i and 720p.In this case, for example, if be example with luminance signal (Y-signal), the kind as Dot Clock frequency (dot clock frequencies) (sample frequency) has three kinds, such as 13.5MHz, 27MHz and 74.25MHz.For this reason, in order to carry out the sampling that is used for the A/D conversion corresponding to these three kinds of Dot Clock frequencies, the previous stage in the A/D conversion corresponding to these three kinds of Dot Clock frequencies each, need make signal band drop on the simulation LPF within the Nyquist frequency scope.But, in practice, not using the 27MHz sampling of 480p, and be configured to sample at 72MHz, this makes it possible to use under corresponding to the situation of 480p the simulation LPF corresponding to 74.25MHz Dot Clock frequency.Thereby,, can provide two simulation LPF corresponding to the Dot Clock frequency of 13.5MHz and 74.25MHz as the simulation LPF of the previous stage that is arranged on A/D converter.
For this reason, system's use each in luminance signal (Y-signal), color difference signal Cb and the color difference signal Cr of the component signal that the previous stage of A/D converter is imported conduct shown in Figure 4 comprises the configurations of described two simulation LPF.At first, analog luminance signal is branched and is input to Y/SD simulation LPF201 and Y/HD simulation LPF202.Described Y/SD simulation LPF201 is that its cut-off frequency is about 7MHz corresponding to the simulation LPF as the luminance signal of the SD (standard resolution) of the Dot Clock (dot clock) with 13.5MHz.
Described Y/HD simulation LPF202 is that its cut-off frequency is about 33MHz corresponding to the simulation LPF as the luminance signal of the HD (high-resolution) of the Dot Clock (dot clock) with 74.25MHz.Be output to the terminal T1 of commutation circuit 204 by the luminance signal of described Y/SD simulation LPF201.
Luminance signal by described Y/HD simulation LPF202 after with amplifier 203 it being scheduled to the amplification of amplification factor, is output to the terminal T2 of commutation circuit 204.The gain loss of the luminance signal by Y/HD simulation LPF202 is greater than the luminance signal by Y/SD simulation LPF201.Therefore, in order to compensate gain inequality, provide above-mentioned amplifier 203 by the luminance signal of Y/HD simulation LPF202.
The switching of described commutation circuit 204 makes among terminal T3 alternate selection terminal T1, the T2 any one.In digital color demodulating system 100, terminal T3 is connected to the input of A/D converter 101A.If the component signal of input is the signal corresponding to SD, by the terminal T3 in splicing ear T1 and the commutation circuit 204, the luminance signal of simulating LPF201 by Y/SD is imported into A/D converter 101A.In addition, if the component signal of input is the signal corresponding to HD, by the terminal T3 in splicing ear T2 and the commutation circuit 204, the luminance signal of simulating LPF201 by Y/SD is imported into A/D converter 101A.
A/D converter 101A carries out sampling processing and is used for the analog luminance signal of input is converted to digital signal.This A/D converter 101A is according to sampling based on the sample frequency of system clock CLK.According to the type of component signal of input, system clock CLK in this case switches between corresponding to 13.5MHz, the 27MHz of above-mentioned Dot Clock frequency and the optional frequency among the 74.25MHz.Like this, between 13.5MHz, 27MHz and 74.25MHz, switch the sample frequency of A/D converter 101A.
In addition, analog color difference signal Cb is branched and is input to C/SD simulation LPF211 and C/HD simulation LPF212.
For this situation, corresponding to the color difference signal as SD (standard resolution), C/SD simulation LPF211 is the simulation LPF that is provided with the cut-off frequency of about 3MHz.In addition, for C/HD simulation LPF212,, the cut-off frequency of about 17MHz is set corresponding to color difference signal as HD (high-resolution).
Equally, for this situation, be output to the terminal T1 of commutation circuit 214 by the color difference signal Cb of C/SD simulation LPF211.Luminance signal by C/HD simulation LPF212 is output to the terminal T2 of commutation circuit 214 after the amplification of being scheduled to amplification factor by amplifier 213 and after carrying out gain compensation.
In addition, in this case, if the component signal of input is the signal corresponding to SD, by connecting terminal T1 and the terminal T3 in the commutation circuit 214, the color difference signal Cb that simulates LPF211 by C/SD is imported into A/D converter 101B.In addition, if the component signal of input is the signal corresponding to HD, by connecting terminal T2 and the terminal T3 in the commutation circuit 214, the luminance signal 20 of simulating LPF211 by C/SD is imported into A/D converter 101B.
Type according to the component signal that will import, corresponding to the A/D converter 101B of the input of color difference signal Cb according to sampling based on the sampling timing of system clock CLK, thereby with color difference signal Cb digitlization, described system clock CLK is assumed that any among 13.5MHz, 27MHz and the 74.25MHz.
In addition, corresponding to the input of color difference signal Cr, the circuit part that is made of C/SD simulation LPF221, C/HD simulation LPF222, amplifier 223 and commutation circuit 224 is set at inert stage.In addition, corresponding to color difference signal Cr, provide an A/D converter 101C to digital chrominance demodulation system 100.Is similar in the operation of the described circuit part of inert stage and described A/D converter 101C with respect to the situation of above-mentioned color difference signal Cb.
Be appreciated that if will give traditional digital color demodulating system 100 from such configuration, obviously, just become quite complicated as the analog signal processing circuit system of the previous stage of digital color demodulating system 100 to the processing capacity of component signal.In other words, for each signal that forms component signal, the commutation circuit that all needs dual system LPF and be used to select the output of these LPF.And, need in the output of a LPF, insert the amplifier that is used for gain compensation.Then, except the combination of these circuit, also need to safeguard the frequency characteristic as the signal of HD, this makes that actual circuit design is very difficult.
In addition, in Fig. 4,, two simulation LPF are arranged owing to simulate common point clock frequency 27MHz, 74.25MHz among the LPF at one.But for the component signal of 480p, if especially must carry out the request of sampling at 27MHz, the quantity of then simulating LPF becomes 3, and this causes circuit further complicated.On the contrary, add the processing capacity that is used for component signal, then can use following configuration if be shown in the digital color demodulating system 1 of the present embodiment of Fig. 1 to conduct.
Here, under the situation of carrying out as the component signal of HD by input as the sampling of A/D conversion, the system clock CLK (sample frequency) of this moment becomes aforesaid 74.25MHz.
Thereby when input during as the component signal of HD, the digital color demodulating system 1 operation PLL circuit 24 of present embodiment is to generate the system clock CLK of 74.25MHz.Then, during when the input component signal or as the composite video signal of different SD with it, as mentioned above, be designed to generate the appropriate frequency 71.6MHz that is taken as about 71MHz or the system clock CLK of 70.88MHz.
In other words, input for component signal, switched system clock CLK between about 71MHz (71.6MHz or 70.88MHz) and 74.25MHz, and based on according to any one sample frequency among these system clocks CLK the vision signal that will import being carried out the A/D conversion.
Thereby, when the cut-off frequency of considering to make signal band fall into the simulation LPF in the Nyquist frequency scope during, for example, can think that they are about 35MHz corresponding to each of the sample frequency of about 71MHz, 74.25MHz, equal basically.
This means, for example, for component signal, for among luminance signal and color difference signal Cb, the Cr each, no matter the signal that will import is HD or SD, if be set to the LPF of 35MHz by the upper limit, then suitably carry out A/D conversion process in the back one-level corresponding to the cut-off frequency of HD signal.In other words, in component signal input stage, can single simulation LPF be installed corresponding to each of luminance signal and color difference signal Cb, Cr as the previous stage of digital color demodulating system 1.
So, according to providing of single LPF, can cancel the amplifier that is used for the compensating gain balance.
According to above-mentioned thought, can use the configuration that is shown in Fig. 5 corresponding to the digital color demodulating system 1 of component signal input in the present embodiment, be included in the configuration of the simulation LPF of its previous stage.Additional disclosure still in Fig. 5, has been omitted the explanation of the circuit arrangement of the composite video signal that is shown among Fig. 1 chrominance demodulation in relatively, just selects and has pointed out the part relevant with the processing of component signal.
As shown in Figure 5, in the previous stage of digital color demodulating system 1, Y/HD analog filter 2A, D/HD simulation LPF2B and C/HD simulation LPF2C are provided.
In other words, no matter the type of component signal is SD or HD, each signal is only disposed and install a simulation LPF be used to be provided with frequency band boundary in the Nyquist frequency.Additional disclosure is for the cut-off frequency of each setting among these simulations LPF corresponding to HD.
Like this, compare with the situation of traditional circuit shown in Figure 4, present embodiment has the ball bearing made using configuration of previous stage in the digital color demodulating system 1.Thereby, to compare with existing situation, the very easy quality of signals that will be input to digital color demodulating system 1 remains on necessary level.In this case, in Y/HD simulation LPF2A, C/HD simulation LPF2B and C/HD simulation LPF2C,, for example, can use filter with characteristic identical with Y/HD simulation LPF202 among Fig. 4 for the Y/HD analog filter 2A of input luminance signal.In other words,, about 33MHz is set, keeps the digital luminance signal of necessary frequency band then, the frequency band boundary is arranged in the scope of Nyquist frequency as HD as cut-off frequency.
In addition, the cut-off frequency of Y/HD analog filter 2A in this case can be regarded as being substantially equal to the simulation LPF2 that is shown in Fig. 1.Like this, can be with the circuit arrangement Y/HD analog filter 2A that equals to simulate LPF2.In addition, can think that Y/HD analog filter 2A and simulation LPF2 share.
In addition, for C/HD simulation LPF2B and C/HD simulation LPF2C, can be with Fig. 4 in the filter of C/HD simulation LPF212,222 with identical characteristics.Like this, for C/HD simulation LPF2B and C/HD simulation LPF2C, about 7MHz is set, corresponding to the digital difference signal Cb of HD, the frequency band of Cr.
Analog luminance signal by Y/HD analog filter 2A is imported into the A/D converter 11A in the digital color demodulating system 1.
This A/D converter 11A is based on sampling with the corresponding sample frequency of system clock CLK, thus the luminance signal of digitlization input.
As mentioned above, when component signal was HD, the frequency of system clock CLK was 74.25MHz, and when component signal was SD, the frequency of system clock CLK was about 71MHz (71.6MHz or 70.88MHz).Like this, the luminance signal of HD is changed by A/D based on the sample frequency of 74.25MHz, and the luminance signal of SD is changed by A/D based on the sample frequency of about 71MHz (71.6MHz or 70.88MHz).
Be branched to by the digitized luminance signal of A/D converter 11A: the path that directly outputs to the terminal T1 of commutation circuit 13A; And output to the path of the terminal T2 of commutation circuit 13A, and be provided by Y/SD numeral LPF35A → minute sample circuit 36A.
Switch described commutation circuit 13A, make terminal T3 alternately be connected to terminal T1 or T2.Selection between aforesaid two paths is to switch by the terminal among the commutation circuit 13A to realize.
When input was the HD component signal, terminal T3 was connected to the terminal T1 among the commutation circuit 13A.Thereby the HD luminance signal is directly outputed to the circuit in the back one-level by A/D converter 11A digitlization.
In other words, the signal processing by Y/HD simulation LPF2A → A/D converter 11A is based on the operation as the frequency bandwidth characteristics of HD luminance signal etc. at first.Like this, when input was the HD luminance signal, the sampling of A/D converter 11A output should be output as digital luminance signal.
On the contrary, when input was the SD component signal, terminal T2 was connected to the terminal T3 among the commutation circuit 13A.Thereby LPF2A → minute sample circuit 36A exports luminance signal by commutation circuit 13A from the Y/SD simulation.
As mentioned above, the signal processing by Y/HD simulation LPF2A → A/D converter 11A meets as the frequency bandwidth characteristics of HD luminance signal etc. at first.But, in the present embodiment, use signal digitalized system jointly for the signal of HD and SD.Like this, if input is the SD signal, then need be based on the frequency band that meets initial SD and the signal of sample frequency (Dot Clock, dot clock) by the digitized luminance signal of A/D converter 11A.For this reason, install from the system of Y/SD numeral LPF35A → minute sample circuit 36A.
For Y/SD numeral LPF35A, cut-off frequency is set to show the frequency bandwidth characteristics that is fit to the SD luminance signal.Then,, divide sample to handle, make the sampled data that obtains equal the sampled data of sampling and obtaining based on the sample frequency of initial SD by a minute sample circuit 36A execution for luminance signal by Y/SD numeral LPF35A.Like this, the luminance signal of exporting from minute sample circuit 36A by commutation circuit 13A has the shape as the suitable digital luminance signal of HD.
Here, in practice, as the SD signal, to have sample frequency be the situation of 13.5MHz and be the situation of 27MHz.The cut-off frequency of Y/SD numeral LPF35A should switch corresponding to described sample frequency.For this reason, in practice, for example, Y/SD numeral LPF35A comprises a coefficients R OM.Then, based on the sample frequency of 13.5MHz, 27MHz, the coefficients R OM that determines the cut-off frequency of LPF can be configured to be switched.In other words, the cut-off frequency of Y/SD numeral LPF35A can easily switch.
In addition, by be similar to as mentioned above circuit corresponding to luminance signal by configuration A/D converter 11B, C/SD numeral LPF35B, divide sample circuit 36B and commutation circuit 13B, in digital color demodulating system 1, form circuit corresponding to the color difference signal Cb by C/HD simulation LPF2B.
In addition, by be similar to as mentioned above circuit corresponding to luminance signal by configuration A/D converter 11C, C/SD numeral LPF35C, divide sample circuit 36C and commutation circuit 13C, in digital color demodulating system 1, form circuit corresponding to the color difference signal Cb by C/HD simulation LPF2C.
Additional disclosure, the operation of each circuit that forms corresponding to color difference signal Cb, Cr that constitutes as mentioned above is substantially similar to as mentioned above the circuit corresponding to luminance signal, for example, the cut-off frequency in C/SD numeral LPF35B, 35C is different from the Y/SD numeral LPF35A.Omit their explanation like this, here.
Because above-mentioned configuration, for color difference signal Cb, Cr, if component signal is HD, digitized HD color difference signal Cb, Cr are directly exported by commutation circuit 13B, 13C by the A/D conversion, if SD, then digital difference signal Cb, the Cr of the shape of sampling suitably for SD by [Y/SD numeral LPF35B → minute sample circuit 36B], [Y/SD numeral LPF35C → minute sample circuit C] output.
In addition, as circuit,, for example, can easily switch cut-off frequency based on the sample frequency of 13.5MHz, 27MHz by handoff factor ROM for Y/SD numeral LPF35B, 35C in color difference signal Cb, Cf one side.
Additional disclosure the invention is not restricted to the configuration of the various embodiments described above.For example, details of the configuration of digital color demodulating system 1 and previous stage thereof etc. can suitably change.
Industrial applicibility
Therefore, as seen from the above description, for example, when the present invention is designed to pass through switched system Clock frequency is carried out type decision, when directly exporting simultaneously the composite video signal after A/D changes, Even as the image that shows and export according to this composite video signal, also can suppress owing to adopt The image disruption that the variation of batten spare causes.
In addition, even in the composite video signal of any type, based on adopting of substantial constant The sample frequency is carried out the A/D conversion. Like this, can come so that the circuit letter by sharing peripheral circuit etc. Listization.
Claims (7)
1. video processing circuit is characterized in that comprising:
Analog-digital commutator, can import the composite video signal of the different different systems of the frequency of burst signal, be used for: sample by using, thereby the composite video signal as analog signal that will import is converted to the composite video signal as digital signal according to the sample frequency of system clock;
Apparatus for processing of video signals, be used for, according to predetermined timing based on described system clock, the YC separating treatment of luminance signal and carrier chrominance signal is isolated in execution from the described composite video signal as described digital signal, and the chrominance demodulation processing of the described carrier chrominance signal that described YC separating treatment is obtained being carried out demodulation; And
The system clock generating means, be used to generate and the synchronous described system clock of burst signal that extracts from described composite video signal, and be configured to standard according to the described composite video signal that is input to described apparatus for processing of video signals and change and a coefficient n is set, make, in the frequency of described burst signal is that fsc, coefficient are that the frequency m of n and described system clock is expressed as under the situation of fsc * n=m, and frequency m falls into the preset range between the described different systems.
2. video processing circuit as claimed in claim 1 is characterized in that comprising:
Low pass filter, wherein, sample frequency according to described analog-digital commutator place is provided with a cut-off frequency, is used for by a frequency band under the described cut-off frequency by the composite video signal as the described input of analog signal, to output to described analog-digital commutator.
3. video processing circuit as claimed in claim 1 is characterized in that comprising:
Low pass filter, to wherein importing from the described composite video signal as digital signal of described analog-digital commutator output, be used for by the composite video signal of the frequency band under a predetermined cut-off frequency, to output to described apparatus for processing of video signals at least by described input.
4. video processing circuit as claimed in claim 1 is characterized in that comprising:
Decision circuit is used for: according under the condition of having switched described system clock frequency with the synchronous regime of the described burst signal of extracting from described composite video signal, the described standard of the described composite video signal that judgement will be imported; And
Signal switching apparatus is used for: during described decision circuit is carried out described decision, after being converted to described digital signal, export composite video signal by described analog-digital commutator, rather than the described luminance signal that obtains by described apparatus for processing of video signals.
5. video processing circuit as claimed in claim 1 is characterized in that:
Described imaging signal processing unit is configured to carry out an operation according to the represented system clock frequency of fsc * a, and wherein, fsc is the frequency of burst signal, and a is that (relation between described coefficient a and the described coefficient n is a＜n) to coefficient; And
Previous stage at described imaging signal processing unit is provided with the branch sampling device, is used for: according to by determined minute sample rate of the relation between described coefficient a and the described coefficient n composite video signal as the described input of digital signal being carried out sampling processing.
6. video processing circuit as claimed in claim 1 is characterized in that:
Described system clock generating means can generated frequency b system clock, this frequency of b is different from the frequency m corresponding to the one-component signal;
Also comprise:
Analog-digital commutator corresponding to described component signal, it is according to the signal setting of the described component signal of formation of every predetermined quantity, be used for: sample by using, will be converted to composite video signal as the composite video signal of the input of analog signal as digital signal according to the sample frequency of the system clock of described frequency of b; And
Low-pass filter corresponding to the one-component signal, be arranged on previous stage corresponding to the described analog-digital commutator of one-component signal, be used for by at the signal of a frequency band below the cut-off frequency by input, being provided with of described cut-off frequency is sample frequency based on corresponding to the described analog-digital commutator of one-component signal;
Wherein, described coefficient n is provided so that: the frequency that described system clock generating apparatus is generated is that the system clock of m has a difference on the frequency in preset range with respect to described frequency of b.
7. video signal processing method is characterized in that comprising:
Analog-to-digital conversion process, can import the composite video signal of the different different systems of the frequency of burst signal, be used for: sample by using, thereby the composite video signal as analog signal of described input is converted to composite video signal as digital signal according to the sample frequency of system clock;
Vision signal is handled, be used for, according to predetermined timing based on described system clock, the YC lock out operation of luminance signal and carrier chrominance signal is isolated in execution from the described composite video signal as described digital signal, and the chrominance demodulation operation of the described carrier chrominance signal that described YC separating treatment is obtained being carried out demodulation; And
System clock is handled, be used to generate and the synchronous described system clock of burst signal that extracts from described composite video signal, and be configured to standard according to the described composite video signal that is input to described apparatus for processing of video signals and change and a coefficient n is set, make, in the frequency of described burst signal is that fsc, coefficient are that the frequency m of n and described system clock is expressed as under the situation of fsc * n=m, and frequency m falls into the preset range between the described different systems.
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| JP2003057005 | 2003-03-04 | ||
| JP057005/2003 | 2003-03-04 | ||
| JP420671/2003 | 2003-12-18 |
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| CN1698387A true CN1698387A (en) | 2005-11-16 |
| CN100342734C CN100342734C (en) | 2007-10-10 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2004800001850A Expired - Fee Related CN100342734C (en) | 2003-03-04 | 2004-02-09 | Video signal processing circuit and video signal processing method |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101902653A (en) * | 2010-06-25 | 2010-12-01 | 杭州爱威芯科技有限公司 | Luminance sample direction prediction-based in-field luminance and chrominance (YC) separation method |
| CN101742345B (en) * | 2008-11-10 | 2012-06-20 | 索尼株式会社 | Transmitter, receiver, signal transmission system, and signal transmission method |
| CN102832875A (en) * | 2011-06-16 | 2012-12-19 | 日立空调·家用电器株式会社 | Control apparatus of AC motor and refrigerating and air conditioning apparatus using same |
| CN112911188A (en) * | 2018-07-25 | 2021-06-04 | 杭州海康威视数字技术股份有限公司 | Video signal system identification method and device, electronic equipment and readable storage medium |
| US11930158B2 (en) | 2018-07-25 | 2024-03-12 | Hangzhou Hikvision Digital Technology Co., Ltd. | Video signal identification method and apparatus, electronic device and readable storage medium |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3572198B2 (en) * | 1998-06-18 | 2004-09-29 | 松下電器産業株式会社 | Video signal processing circuit |
| JP2001095005A (en) * | 1999-09-20 | 2001-04-06 | Matsushita Electric Ind Co Ltd | Clock-generating circuit |
-
2004
- 2004-02-09 CN CNB2004800001850A patent/CN100342734C/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101742345B (en) * | 2008-11-10 | 2012-06-20 | 索尼株式会社 | Transmitter, receiver, signal transmission system, and signal transmission method |
| CN101902653A (en) * | 2010-06-25 | 2010-12-01 | 杭州爱威芯科技有限公司 | Luminance sample direction prediction-based in-field luminance and chrominance (YC) separation method |
| CN101902653B (en) * | 2010-06-25 | 2013-04-24 | 杭州爱威芯科技有限公司 | Luminance sample direction prediction-based in-field luminance and chrominance (YC) separation method |
| CN102832875A (en) * | 2011-06-16 | 2012-12-19 | 日立空调·家用电器株式会社 | Control apparatus of AC motor and refrigerating and air conditioning apparatus using same |
| CN102832875B (en) * | 2011-06-16 | 2014-12-24 | 日立空调·家用电器株式会社 | Control apparatus of AC motor and refrigerating and air conditioning apparatus using same |
| CN112911188A (en) * | 2018-07-25 | 2021-06-04 | 杭州海康威视数字技术股份有限公司 | Video signal system identification method and device, electronic equipment and readable storage medium |
| US11930158B2 (en) | 2018-07-25 | 2024-03-12 | Hangzhou Hikvision Digital Technology Co., Ltd. | Video signal identification method and apparatus, electronic device and readable storage medium |
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| CN100342734C (en) | 2007-10-10 |
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