CN104579323A - Second-level frequency-phase detection charge pump phase-locked loop - Google Patents
Second-level frequency-phase detection charge pump phase-locked loop Download PDFInfo
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- CN104579323A CN104579323A CN201410416799.2A CN201410416799A CN104579323A CN 104579323 A CN104579323 A CN 104579323A CN 201410416799 A CN201410416799 A CN 201410416799A CN 104579323 A CN104579323 A CN 104579323A
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Abstract
The invention discloses a charge pump phase-locked loop which can be locked quickly. A second-level frequency-phase detector is adopted in the charge pump phase-locked loop; the output of a first-level frequency-phase detector is buffered and filtered and then is subjected to frequency-phase detection; a current charge pump is driven and adjusted coarsely, and the output of the first-level frequency-phase detector directly drives and finely adjusts the current charge pump at the same time; the control voltage at a control end of a voltage-controlled oscillator is adjusted. The output noise of the charge pump phase-locked loop is reduced while the lock speed of the charge pump phase-locked loop is increased.
Description
Technical field
The present invention relates to integrated circuit, be specifically related to the carrier signal of data communication system and Digital Signal Processing and the generation of clock signal.
Background technology
The development of current data communication and Digital Signal Processing, proposes new requirement to spectrum of carrier, channel switch speed and clock jitter.In charge pump phase lock loop frequency synthesizer, what detect due to phase detection discriminator is the saltus step of reference signal and feedback signal, its frequency is higher, in out-of-lock condition, the state frequent variations of phase detection discriminator, so that constantly On/Off charge pump, causes filter charge/discharge discontinuous, produce impulse disturbances.This will cause the fluctuation of voltage controlled oscillator control voltage, makes output signal produce shake, increases the noise of output signal, and reduce lock speed.
Summary of the invention
The deficiency large for current charge pump PLL noise and locking time is long, the present invention proposes secondary phase demodulation frequency discrimination charge pump phase lock loop.
For achieving the above object, the present invention takes following technical scheme to realize:
A kind of secondary phase demodulation frequency discrimination charge pump phase lock loop, is characterized in that, comprise a second level frequency discrimination phase discriminator, a gross adjustment currents charge pump, fine tuning current charge pump, loop filter, voltage controlled oscillator and a frequency divider.In out-of-lock condition, use gross adjustment currents charge pump to regulate the control voltage of voltage controlled oscillator, make charge pump phase lock loop have large bandwidth, improve its lock speed; In synchronizing process, use fine tuning current charge pump to regulate the control voltage of voltage controlled oscillator, make charge pump phase lock loop bandwidth less, improve its noiseproof feature.
In such scheme, described second level frequency discrimination phase discriminator is made up of two buffers, two filters and two phase frequency detectors.The phase difference of first order phase frequency detector reference signal detection and feedback signal, two export after two buffer isolation, by its pulse duration of filter detection, when pulse duration is greater than a certain value, start second level phase frequency detector, drive gross adjustment currents charge pump.When pulse duration is less than a certain value, second level phase frequency detector does not work.
In such scheme, the pull-up current of described gross adjustment currents charge pump and pull-down current are all comparatively large, to increase the bandwidth of phase-locked loop, improve lock speed.When second level phase frequency detector has output, this gross adjustment currents charge pump, regulates the control voltage of voltage controlled oscillator together with fine tuning current charge pump.
In such scheme, pull-up current and the pull-down current of described fine tuning current charge pump are all less, to reduce the bandwidth of phase-locked loop, improve in-band noise.
The present invention changes according to the dynamic situation of loop by making the pull-up current of charge pump phase lock loop and pull-down current simultaneously, regulation loop bandwidth, while raising locking performance, keep noiseproof feature.
Accompanying drawing explanation
Fig. 1 is second level frequency discrimination phase-demodulating principle figure
Fig. 2 is second level frequency discrimination phase demodulation charge pump phase locking loop circuit schematic diagram of the present invention.
Embodiment
Below in conjunction with drawings and the specific embodiments, the present invention is described in detail.
Fig. 1 is second level frequency discrimination phase-demodulating principle figure, comprises first order phase frequency detector (10) and second level phase frequency detector (20).
In Fig. 1, ref and fb meets ref1 and fb1 of first order phase frequency detector (10) respectively; Output up1 and dn1 of first order phase frequency detector (10) meets input ref2 and fb2 of second level phase frequency detector (20) respectively; Output up1 and dn1 of second level phase frequency detector (20) picks out up and dn respectively.
Fig. 2 is second level frequency discrimination phase-demodulating principle figure, comprise first order phase frequency detector (10), buffer (30,50), filter (40,60), second level phase frequency detector (20), first order charge pump (80), second level charge pump (70), loop filter (90), voltage controlled oscillator (100), frequency divider (110).
In Fig. 2, the output of first order phase frequency detector (10) connects first order charge pump (80), connects buffer (30,50) simultaneously, avoids the impact that filter (40,60) exports first order phase frequency detector (10).The output of buffer (30,50) connects filter (40,60), the burst pulse that filtering first order phase frequency detector (10) produces respectively.The output of filter (40,60) connects second level phase frequency detector (20).The output of second level phase frequency detector (20) connects second level charge pump (70), starts second level charge pump (70) when input exists difference on the frequency or phase difference is larger, increases loop bandwidth, reduces start-up time.Output T-Ring path filter (90) simultaneously of first order charge pump (80) and second level charge pump (70), the magnitude of voltage on regulation loop filter (90).The output of loop filter (90) connects voltage controlled oscillator (100), controls the frequency of oscillation of voltage controlled oscillator (100).Voltage controlled oscillator (100) produces the oscillator signal needed.Voltage controlled oscillator (100) connects frequency divider (110), produces fractional frequency signal.The output of frequency divider (110) connects first order phase frequency detector (10), to carry out frequency and phase discrimination to reference signal and feedback signal.
Above content is the further description done the present invention in conjunction with concrete execution mode; can not assert that the specific embodiment of the present invention is only limitted to this; for general technical staff of the technical field of the invention; without departing from the inventive concept of the premise; some simple deduction or replace can also be made, all should be considered as belonging to the present invention by submitted to claims determination scope of patent protection.
Claims (3)
1. a second level frequency discrimination phase demodulation charge pump phase lock loop, comprise secondary phase detection discriminator, fine tuning current charge pump, gross adjustment currents charge pump, loop filter, voltage controlled oscillator and frequency divider, it is characterized in that: described secondary phase detection discriminator is when input signal exists difference on the frequency or phase difference is larger, start second level phase frequency detector, drive gross adjustment currents charge pump, improve the loop bandwidth of charge pump phase lock loop, reduce start-up time.
2. a kind of second level frequency discrimination phase demodulation charge pump phase lock loop as claimed in claim 1, it is characterized in that: described secondary phase detection discriminator is made up of first order phase detection discriminator, buffer, filter and second level phase detection discriminator, first order phase detection discriminator is connected with buffer, filter and second level phase detection discriminator.
3. a kind of second level frequency discrimination phase demodulation charge pump phase lock loop as claimed in claim 1, is characterized in that: in described secondary phase detection discriminator, first order phase detection discriminator drives fine tuning current charge pump, and second level phase detection discriminator drives gross adjustment currents charge pump.
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CN201410416799.2A CN104579323A (en) | 2014-08-22 | 2014-08-22 | Second-level frequency-phase detection charge pump phase-locked loop |
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CN201410416799.2A CN104579323A (en) | 2014-08-22 | 2014-08-22 | Second-level frequency-phase detection charge pump phase-locked loop |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105842537A (en) * | 2016-03-18 | 2016-08-10 | 山东交通学院 | Method and circuit for measuring phase difference based on integrated phase frequency discriminator |
CN105846817A (en) * | 2016-03-24 | 2016-08-10 | 中国电子科技集团公司第二十四研究所 | Lower-sampling type phase discriminator and charge-pump circuit with gain control |
CN105871372A (en) * | 2016-03-24 | 2016-08-17 | 中国电子科技集团公司第二十四研究所 | Downsampling phase locked loop for preventing in-band noise from being amplified to square times of frequency dividing ratio |
CN114362748A (en) * | 2022-03-18 | 2022-04-15 | 深圳通锐微电子技术有限公司 | Current adjusting method of charge pump, current adjusting circuit and phase-locked loop circuit |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6384690B1 (en) * | 1997-10-10 | 2002-05-07 | Telefonaktiebolaget Lm Ericsson (Publ) | Phase locked loop control via inner and outer feedback control circuits |
CN1980064B (en) * | 2005-11-29 | 2010-10-06 | 中芯国际集成电路制造(上海)有限公司 | Cock-phase-ring indicator |
CN101931399A (en) * | 2009-06-24 | 2010-12-29 | 中国科学院微电子研究所 | Phase-locked loop frequency synthesizer |
CN103312372A (en) * | 2012-03-15 | 2013-09-18 | 晨星软件研发(深圳)有限公司 | Frequency correcting method |
CN204089772U (en) * | 2014-08-22 | 2015-01-07 | 魏建军 | A kind of second level frequency discrimination phase demodulation charge pump phase lock loop |
-
2014
- 2014-08-22 CN CN201410416799.2A patent/CN104579323A/en active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6384690B1 (en) * | 1997-10-10 | 2002-05-07 | Telefonaktiebolaget Lm Ericsson (Publ) | Phase locked loop control via inner and outer feedback control circuits |
CN1980064B (en) * | 2005-11-29 | 2010-10-06 | 中芯国际集成电路制造(上海)有限公司 | Cock-phase-ring indicator |
CN101931399A (en) * | 2009-06-24 | 2010-12-29 | 中国科学院微电子研究所 | Phase-locked loop frequency synthesizer |
CN103312372A (en) * | 2012-03-15 | 2013-09-18 | 晨星软件研发(深圳)有限公司 | Frequency correcting method |
CN204089772U (en) * | 2014-08-22 | 2015-01-07 | 魏建军 | A kind of second level frequency discrimination phase demodulation charge pump phase lock loop |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105842537A (en) * | 2016-03-18 | 2016-08-10 | 山东交通学院 | Method and circuit for measuring phase difference based on integrated phase frequency discriminator |
CN105842537B (en) * | 2016-03-18 | 2018-09-04 | 山东交通学院 | Method for measuring phase difference based on integrated phase detection discriminator and circuit |
CN105846817A (en) * | 2016-03-24 | 2016-08-10 | 中国电子科技集团公司第二十四研究所 | Lower-sampling type phase discriminator and charge-pump circuit with gain control |
CN105871372A (en) * | 2016-03-24 | 2016-08-17 | 中国电子科技集团公司第二十四研究所 | Downsampling phase locked loop for preventing in-band noise from being amplified to square times of frequency dividing ratio |
CN114362748A (en) * | 2022-03-18 | 2022-04-15 | 深圳通锐微电子技术有限公司 | Current adjusting method of charge pump, current adjusting circuit and phase-locked loop circuit |
CN114362748B (en) * | 2022-03-18 | 2022-05-27 | 深圳通锐微电子技术有限公司 | Current adjusting method of charge pump, current adjusting circuit and phase-locked loop circuit |
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