JP5177905B2 - CDR circuit - Google Patents

Description

  The present invention relates to a CDR circuit that regenerates a clock that is phase-synchronized with input data and performs retiming of input data using this clock.

  In the PON (Passive Optical Network) system, which is being developed as a means for realizing FTTH (Fiber To The Home), it is necessary to handle burst data. In these systems, a CDR (Clock Data Recovery) circuit that instantaneously establishes phase synchronization with respect to burst data received asynchronously on the station side, extracts a clock, and retimes data in synchronization with this clock is provided. It is essential. This type of circuit can be referred to in Non-Patent Document 1, for example.

  FIG. 8 shows a configuration example of a CDR circuit used for such a purpose. When input data 4 is input to a main VCO (Voltage Controlled Oscillator) 11, the main VCO 11 uses the timing of the input data 4, that is, the voltage value shift point as a trigger, and the oscillation phase of the input data 4 It is adjusted to match the phase. The phase-adjusted oscillation signal is output from the main VCO 11 as a recovered clock 7 in phase with the input data 4. The reproduction clock 7 is input to a clock terminal of a flip-flop (hereinafter referred to as F / F) 3 and used for retiming of input data 4 input to a data input terminal of F / F 3. As a result, the reproduction data 6 is output from the F / F 3.

  On the other hand, the sub VCO 12 having the same configuration as the main VCO 11 forms a PLL (Phase-Locked Loop) together with the frequency comparator 2. The sub VCO 12 oscillates at the same frequency as the reference clock 5 having a frequency equal to the data rate of the input data 4 or the reference clock 5 having a frequency that is a fraction of that frequency. The frequency comparator 2 compares the frequency of the output clock output from the sub-VCO 12 with the frequency of the reference clock 5. If the frequency of the output clock of the sub-VCO 12 is higher than the frequency of the reference clock 5, the frequency comparator 2 determines the oscillation frequency of the sub-VCO 12. A control signal (control voltage) 8 for controlling to be lowered is output, and if the frequency of the output clock of the sub VCO 12 is lower than the frequency of the reference clock 5, a control signal (control voltage) for controlling to raise the oscillation frequency of the sub VCO 12 8 is output. The control signal (control voltage) 8 output from the frequency comparator 2 is supplied to the frequency control terminal of the main VCO 11 at the same time as being supplied to the frequency control terminal of the sub VCO 12. As a result, the frequency of the clock output from the sub VCO 12 and the frequency of the recovered clock 7 output from the main VCO 11 are controlled to be the same.

  According to the conventional configuration shown in FIG. 8, since the data rate of the input data 4 and the frequency of the reproduction clock 7 output from the main VCO 11 always coincide with each other, the main VCO 11 is in phase when the input data 4 is input. It can be expected that the synchronization with the input data 4 is instantly established.

  However, in order for such a configuration to operate ideally, the main VCO 11 and the sub VCO 12 need to be exactly the same. Even if these VCOs are integrated on the IC with the same configuration, it is impossible to form exactly the same VCO due to process variations. Therefore, in the configuration shown in FIG. 8, there is a possibility that a deviation occurs between the oscillation frequency of the sub-VCO 12 and the frequency of the regenerated clock 7 output from the main VCO 11, thereby causing an increase in jitter. Further, even if the VCO can be configured with exactly the same VCO, the oscillation frequency of the main VCO 11 is controlled by feedforward, so that the oscillation frequency can be kept strictly constant, unlike the sub-VCO 12 that is PLL-controlled. However, there is an essential problem that jitter increases due to frequency error. Further, the configuration shown in FIG. 8 has a problem that the power consumption and the circuit scale increase due to the use of the VCO dedicated to the frequency control loop.

  As means that can be expected to solve such problems, Non-Patent Document 2 proposes a circuit configuration as shown in FIG. In the configuration of the CDR circuit shown in FIG. 9, the sub VCO 12 is removed from the configuration shown in FIG. 8, and the recovered clock 7 output from the main VCO 11 is input to the frequency comparator 2 instead of the output clock of the sub VCO 12. By performing PLL control (feedback control) on the main VCO 11, in addition to reducing power consumption and circuit scale, it can be expected to obtain a clock signal with very high frequency stability.

  The operation of the CDR circuit shown in FIG. 9 is as follows. The gating circuit 10 outputs an edge pulse when the input data 4 transitions from “0” to “1” or “1” to “0”. The VCO 11 oscillates at the same frequency as the reference clock 5 having the same frequency as the data rate of the input data 4. The VCO 11 is provided with a gate circuit capable of controlling the oscillation start timing in a normal ring oscillation circuit composed of multistage variable delay inverters.

  The phase of the recovered clock 7 output from the VCO 11 is controlled by the output pulse of the gating circuit 10. That is, the VCO 11 is reset when, for example, an edge pulse having a value of “0” is output from the gating circuit 10, outputs “0”, the output of the edge pulse ends, and the output of the gating circuit 10 becomes “ Oscillation starts as soon as it becomes “1”, and oscillation continues while the output of the gating circuit 10 is “1”. Thus, in the VCO 11, the phase of the reproduction clock 7 is adjusted so as to match the phase of the input data 4.

Y. Ota, et al., “High-speed, burst mode, packet-capable optical receiver and instantaneous clock recovery for optical bus operation”, J. Lightwave Technol., Vol.12, no.2, p.325-331 , Feb.1994 J. Terada, et al., “A 10.3 Gb / s Burst-Mode CDR Using a ΔΣ DAC”, IEEE J. Solid-State Circuits, vol. 12, p.2921-2928, Dec.2008

  However, the configuration shown in FIG. 9 has a new problem that it is difficult to cope with the dual rate PON system that is currently being standardized. In the PON system, the upstream signal from each subscriber side device to the station side device becomes an intermittent optical signal, but in the dual rate PON system, upstream signals of 1.25 Gbps and 10.3125 Gbps are mixed and transmitted. Therefore, as shown in FIG. 10, the 1.25 Gbps (1 G) burst signal 100 and the 10.3125 Gbps (10 G) burst signal 101 are output from the optical receiver of the station side device in a mixed form. When the input data 4 in which the 1G burst signal 100 and the 10G burst signal 101 are mixed is input to the CDR circuit shown in FIG. 9, the following problem occurs.

  For example, when input data 4 of 1.25 Gbps is input to the CDR circuit for 10.3125 Gbps, an edge pulse of 10 Gbps (= 1.25 Gbps × 8) lower than the desired speed is output from the gating circuit 10 to the VCO 11. Is input. In this case, since the oscillation frequency of the VCO 11 approaches 10 GHz, a control signal (control voltage) 8 that increases the oscillation frequency so that the oscillation frequency becomes the same frequency as the reference clock 5 in the PLL control is continuously output. The control voltage at this time is different from the control voltage when the input data 4 of 10.3125 Gbps is input. Thus, when 10.3125 Gbps input data 4 is input in a state different from the optimum control voltage for 10.3125 Gbps input, it takes time for frequency synchronization, and the response time becomes very long. Problem arises.

  Conversely, when 10.3125 Gbps input data 4 is input to the CDR circuit for 1.25 Gbps, an edge of 1.289 Gbps (= 10.3125 Gbps ÷ 8) faster than the desired speed from the gating circuit 10. A pulse is input to the VCO 11. In this case, since the oscillation frequency of the VCO 11 approaches 1.289 GHz, the control signal (control voltage) 8 that continuously decreases the oscillation frequency so that the oscillation frequency becomes the same frequency as the reference clock 5 in the PLL control is continuously output. Become. The control voltage at this time is different from the control voltage when the input data 4 of 1.25 Gbps is input. Thus, when input data 4 of 1.25 Gbps is input in a state different from the optimum control voltage for 1.25 Gbps input, there arises a problem that the response time becomes very long.

  Further, even when low-frequency noise is output from an amplifier or the like before the CDR circuit when no signal is input, a low-speed or high-speed edge pulse corresponding to the frequency component of the noise is input from the gating circuit 10 to the VCO 11. Therefore, the control signal (control voltage) 8 is different from the case where the input data 4 having a desired data rate is input, and the response time when the input data 4 having the desired data rate is input. The problem that becomes very long occurs.

  Such a delay in response time greatly impairs the transmission efficiency of the PON system, particularly the dual rate PON system. If a control signal from MAC (Media Access Control) is used, it is possible to prevent one of the dual rate signals from being output from the optical receiver so as to avoid this problem of delay in response time. In addition to the deterioration of transmission efficiency due to the insertion of a control signal, a problem arises that fine timing adjustment is required.

  An object of the present invention is to solve the above-mentioned conventional problems, and in a PON system that handles dual rate signals, synchronization with input data is instantly established without a control signal from the MAC, and frequency stability is high and jitter is low. It is an object of the present invention to provide a low power consumption CDR circuit capable of generating a reproduction clock.

The CDR circuit according to the present invention includes a gating circuit that outputs a pulse when input data transitions, and adjusts the phase of a reproduction clock so as to match the timing of the output pulse of the gating circuit. A first voltage-controlled oscillator that outputs a reproduction clock having a proper timing; a data identification circuit that performs data identification of the input data based on the reproduction clock; an output terminal of the gating circuit; and the first voltage control. A first filter provided between the input terminal of the oscillator and a signal having a desired data rate frequency is passed. The first voltage controlled oscillator is desired at the frequency control terminal of the first voltage controlled oscillator. And a frequency control circuit that supplies a frequency control signal that oscillates at the data rate frequency .
Further, one configuration example of the CDR circuit of the present invention further includes a second voltage controlled oscillator provided between an output terminal of the gating circuit and an input terminal of the first filter, 2 of the voltage controlled oscillator, by adjusting the phase of the clock to match the timing of the output pulses of said gating circuit, outputs suits a clock of said input data and timing to said first filter, said frequency The control circuit supplies the frequency control signal to a frequency control terminal of the second voltage controlled oscillator .
Further, one configuration example of the CDR circuit of the present invention further includes a second filter provided between an output terminal of the gating circuit and an input terminal of the second voltage controlled oscillator, The second filter is characterized in that a signal having a desired data rate frequency is passed by using the output of the gating circuit as an input.

Further, one configuration example of the CDR circuit according to the present invention may further include a third circuit provided between the output terminal of the gating circuit and the input terminal of the second voltage controlled oscillator or the second filter. A voltage controlled oscillator, wherein the third voltage controlled oscillator adjusts the phase of the clock to match the timing of the output pulse of the gating circuit, so that the clock that matches the timing of the input data is the second The frequency control circuit supplies the frequency control signal to a frequency control terminal of the third voltage controlled oscillator .
Further, one configuration example of the CDR circuit of the present invention further includes a third filter provided between an output terminal of the gating circuit and an input terminal of the third voltage controlled oscillator, The filter No. 3 is characterized in that a signal having a desired data rate frequency is passed by using the output of the gating circuit as an input.
Also, one configuration example of the CDR circuit of the present invention is characterized in that at least one of the filters is replaced with an attenuator or a buffer amplifier.
In one configuration example of the CDR circuit of the present invention, the filter is any one of a low-pass filter, a high-pass filter, and a band-pass filter.

In one configuration example of the CDR circuit of the present invention, the frequency control circuit includes a frequency divider that divides the recovered clock into 1 / n (n is a positive integer), 1 / n of a desired data rate frequency. The frequency comparator is configured to compare the reference clock of n frequency with the output of the frequency divider and output the frequency control signal.

  According to the present invention, a gating circuit that outputs a pulse when input data transitions, and a phase of a reproduction clock that matches a timing of an output pulse of the gating circuit, the timing of the input data is matched. A first voltage controlled oscillator for outputting a reproduction clock; and a data identification circuit for performing data identification of input data based on the reproduction clock; and an output terminal of the gating circuit and an input terminal of the first voltage controlled oscillator; By providing a first filter for passing a signal of a desired data rate frequency between the first voltage controlled oscillator and the input of the desired data rate frequency, the first voltage controlled oscillator is linked only to the input data of the desired data rate frequency. When no data is input, the first voltage controlled oscillator maintains a self-sustained oscillation with high frequency stability. Door can be. As a result, according to the present invention, in the dual rate PON system, it is not necessary to provide the optical receiver with a mechanism that removes one of the data rates of the dual rate signal using a control signal from the MAC. Even without a control signal from the MAC, synchronization with the input data can be instantly established, and a reproduction clock with high frequency stability and low jitter can be generated.

  Further, according to the present invention, it is possible to generate a recovered clock having a higher frequency stability by providing the second voltage controlled oscillator between the output terminal of the gating circuit and the input terminal of the first filter. become.

  Further, according to the present invention, it is possible to generate a reproduction clock with higher frequency stability by providing a second filter between the output terminal of the gating circuit and the input terminal of the second voltage controlled oscillator. become.

  Further, according to the present invention, it is possible to generate a recovered clock having a higher frequency stability by providing a third voltage controlled oscillator between the output terminal of the gating circuit and the input terminal of the second filter. become.

  Further, according to the present invention, it is possible to generate a reproduction clock with higher frequency stability by providing a third filter between the output terminal of the gating circuit and the input terminal of the third voltage controlled oscillator. become.

  In the present invention, even when at least one of the filters is replaced with an attenuator or a buffer amplifier, the same effect as that in the case of using the filter can be obtained.

  In the present invention, the frequency control circuit compares the frequency divider that divides the recovered clock by 1 / n with the reference clock having a frequency 1 / n of the desired data rate frequency and the output of the frequency divider. Since the operation speed required for the frequency comparator can be reduced by configuring the frequency comparator to output the frequency control signal, the power consumption of the frequency comparator can be reduced. As a result, the CDR circuit Power consumption can be reduced.

1 is a block diagram showing a configuration of a CDR circuit according to a first embodiment of the present invention. FIG. 3 is a circuit diagram showing an example of a configuration of a VCO in the CDR circuit according to the first embodiment of the present invention. It is a block diagram which shows the structure of the CDR circuit which concerns on the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the CDR circuit which concerns on the 3rd Embodiment of this invention. It is a block diagram which shows the structure of the CDR circuit which concerns on the 4th Embodiment of this invention. It is a block diagram which shows the structure of the CDR circuit which concerns on the 5th Embodiment of this invention. It is a block diagram which shows the structure of the CDR circuit which concerns on the 6th Embodiment of this invention. It is a block diagram which shows the structure of the conventional CDR circuit. It is a block diagram which shows the structure of another conventional CDR circuit. It is a schematic diagram which shows an example of the upstream signal in a dual rate PON system.

[First Embodiment]
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a CDR circuit according to the first embodiment of the present invention. The CDR circuit of the present embodiment includes a frequency comparator 2, an F / F 3, a gating circuit 10, a VCO 11, and a frequency divider inserted between the output terminal of the VCO 11 and the input terminal of the frequency comparator 2. And a band-pass filter (hereinafter referred to as BPF) 40 inserted between the output terminal of the gating circuit 10 and the input terminal of the VCO 11. The frequency comparator 2 and the frequency divider 25 constitute a frequency control circuit. 9 differs from the conventional CDR circuit shown in FIG. 9 in that a frequency divider 25 is inserted between the output terminal of the VCO 11 and the input terminal of the frequency comparator 2, and the output terminal of the gating circuit 10 and the VCO 11 That is, the BPF 40 is inserted between the input terminals.

  The frequency divider 25 divides the reproduction clock 7 by 1 / n (n is a positive integer). The band of the BPF 40 is set so that, for example, when the CDR circuit is for 1.25 Gbps, a signal of 1.25 GHz is passed and signals of other frequency bands are suppressed. Further, the band of the BPF 40 is set such that when the CDR circuit is for 10.3125 Gbps, for example, a 10.3125 GHz signal is allowed to pass and signals in other frequency bands are suppressed.

  The CDR circuit of the present embodiment has only input data 4 of a desired data rate (for example, 1.25 Gbps input data 4 if the CDR circuit is for 1.25 Gbps, 10.3125 Gbps input if it is for 10.3125 Gbps). When data 4) is input, the same operation as in the conventional example shown in FIG. 9 is performed. When the input data 4 transitions from “0” to “1”, the gating circuit 10 outputs, for example, a pulse having a width of T / 2 (T is a cycle of the input data). Alternatively, the gating circuit 10 may output a pulse when the input data 4 transitions from “1” to “0”. The edge pulse output from the gating circuit 10 passes through the BPF 40 and is input to the input terminal of the VCO 11.

  The recovered clock 7 output from the VCO 11 is frequency-divided by 1 / n by the frequency divider 25 and input to the frequency comparator 2. In the present embodiment, a reference clock 5 having a frequency 1 / n of the data rate of the input data 4 is input to the frequency comparator 2. The PLL composed of the frequency comparator 2, the VCO 11, and the frequency divider 25 performs closed-loop control so that the oscillation frequency of the VCO 11 matches the frequency n times that of the reference clock 5. Therefore, in the case of a CDR circuit for 10.3125 Gbps, the VCO 11 oscillates at 10.3125 GHz, and in the case of a CDR circuit for 1.25 Gbps, the VCO 11 oscillates at 1.25 GHz. In this embodiment, since the operating speed required for the frequency comparator 2 can be reduced by providing the frequency divider 25, the power consumption of the frequency comparator 2 can be reduced, resulting in the consumption of the CDR circuit. Electric power can be reduced.

  The phase of the recovered clock 7 output from the VCO 11 is controlled by a pulse input from the gating circuit 10 via the BPF 40. That is, the VCO 11 is reset and outputs “0” when, for example, a pulse with a value “0” is output from the BPF 40, and as soon as the pulse output ends and the output of the BPF 40 becomes “1”. Oscillation is started and continues while the output of the BPF 40 is “1”. In the CDR circuit for 10.3125 Gbps, when 10.3125 Gbps input data 4 is input, the gating circuit 10 outputs a pulse synchronized with the edge of the input data 4, and this edge pulse is in the 10.3125 GHz band. Since it is input to the VCO 11 via the BPF 40, the reproduction clock 7 phase-synchronized with the edge of the input data 4 can be output instantaneously.

  VCO 11 is preferably a gated VCO. The VCO 11 is configured by including a gate circuit capable of controlling the timing of oscillation start in a normal ring oscillation circuit composed of, for example, a multistage variable delay inverter. FIG. 2 is a circuit diagram showing an example of the configuration of the VCO 11. The VCO 11 has one input terminal connected to the input terminal of the VCO 11 and the other input terminal to which the output of the VCO 11 is input, the inverter 110 having the output of the NAND 110 as an input, and the output of the inverter 111 as inputs. An inverter 112 whose output terminal is connected to the output terminal of the VCO 11, one end is connected to the output terminal of the inverter 111 and the input terminal of the inverter 112, and a capacity control terminal (not shown) is connected to the frequency control terminal of the VCO 11. And a variable capacitor 113.

  The F / F 3 serving as a data identification circuit retimes the input data 4 at a predetermined timing of the reproduction clock 7 (for example, the rising edge of the reproduction clock 7), and outputs the reproduction data 6.

  Next, the operation of the CDR circuit when connected to the subsequent stage of a dual rate optical receiver that receives optical signals of different data rates in a mixed manner will be described. For example, when 10.3125 Gbps input data 4 is input to the CDR circuit for 1.25 Gbps, the output of the gating circuit 10 is input to the VCO 11 as it is as in the configuration of the CDR circuit shown in FIG. Then, an edge pulse of 1.289 Gbps (= 10.3125 Gbps ÷ 8) faster than a desired speed is input from the gating circuit 10 to the VCO 11. In this case, since the oscillation frequency of the VCO 11 approaches 1.289 GHz, the control signal (control voltage) 8 that continuously decreases the oscillation frequency so that the oscillation frequency becomes the same frequency as the reference clock 5 in the PLL control is continuously output. Become. The control voltage at this time is different from the control voltage when the input data 4 of 1.25 Gbps is input. Thus, when input data 4 of 1.25 Gbps is input in a state different from the optimum control voltage for 1.25 Gbps input, there arises a problem that the response time becomes very long.

  On the other hand, in the CDR circuit of the present embodiment, the presence of the BPF 40 that allows signals only in the vicinity of 1.25 GHz to pass through can suppress the 1.289 GHz frequency component input from the gating circuit 10 to the VCO 11. As in the conventional CDR circuit, the control signal (control voltage) 8 is not different from the value when the input data 4 of 1.25 Gbps is input. Accordingly, it becomes possible to stably maintain the control voltage when the input data 4 of 1.25 Gbps is input, and to continuously set the oscillation frequency of the VCO 11 to a desired data rate frequency of 1.25 GHz. it can. Therefore, even when the input data 4 of 1.25 Gbps is input immediately after the input data 4 of 10.3125 Gbps, it is possible to output the 1.25 GHz recovered clock 7 with little jitter and phase-synchronized instantaneously.

  In addition, when 1.25 Gbps input data 4 is input to the CDR circuit for 10.3125 Gbps, the CDR circuit according to the present embodiment causes the gating due to the presence of the BPF 40 that allows signals only in the vicinity of 10.3125 GHz to pass. Since the 10 GHz frequency component input from the circuit 10 to the VCO 11 can be suppressed, the control voltage when the 10.3125 Gbps input data 4 is input can be maintained, and the oscillation frequency of the VCO 11 can be reduced. The desired data rate frequency can be continuously set to 10.3125 GHz. Therefore, even when the 10.3125 Gbps input data 4 is input immediately after the 1.25 Gbps input data 4, it is possible to output the 10.3125 GHz recovered clock 7 with little jitter and phase-synchronized instantaneously.

  Further, in the CDR circuit of the present embodiment, even if low-frequency noise is output from a previous stage amplifier or the like (not shown) when no signal is input, a low-speed or high-speed edge pulse corresponding to the frequency component of the noise. Is suppressed by the BPF 40. Therefore, it becomes possible to maintain the control voltage when the input data 4 having a desired data rate is input, and the oscillation frequency of the VCO 11 can be continuously set to the desired data rate frequency. Therefore, in this embodiment, it is possible to avoid an increase in response time due to low frequency noise input.

  As described above, in the present embodiment, in the dual rate PON system, the dual rate signal can be input to the CDR circuit as it is, so one of the dual rate signals using the control signal from the MAC or the like. It is not necessary to provide the optical receiver with a mechanism that removes a signal having a data rate of 2. Further, in the present embodiment, even in a small and power-saving CDR circuit that does not require a sub-VCO dedicated to the frequency control loop as in the conventional example shown in FIG. Therefore, it is possible to reduce the power consumption of the apparatus and improve the quality of the output waveform. As a result, this embodiment can contribute to low power consumption, no adjustment, and economy of the dual rate PON system receiver without impairing transmission efficiency.

  In the present embodiment, the output of the frequency comparator 2 is directly connected to the VCO 11. However, the present invention is not limited to this. In order to stabilize the operation of the PLL loop, the output between the frequency comparator 2 and the VCO 11 is not limited. A charge pump and a low-pass filter may be provided to slow down the change rate of the control signal 8.

[Second Embodiment]
Next, a second embodiment of the present invention will be described. FIG. 3 is a block diagram showing the configuration of the CDR circuit according to the second embodiment of the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals. In the present embodiment, a low pass filter (hereinafter referred to as LPF) 41 is provided between the output terminal of the gating circuit 10 and the input terminal of the VCO 11 instead of the BPF 40 of the first embodiment. The band of the LPF 41 is set so that, for example, when the CDR circuit is for 1.25 Gbps, a signal of 1.25 GHz is passed and a signal of a frequency band higher than 1.25 GHz is suppressed.

  This embodiment is a modification of the first embodiment, and is suitable for a low-speed signal side CDR circuit connected to a subsequent stage of an optical receiver of a dual rate PON system. That is, it is assumed that the CDR circuit of this embodiment is for 1.25 Gbps, for example, and the cutoff frequency of the LFP 41 is 1.25 GHz or more and 1.289 GHz or less. When the 10.3125 Gbps input data 4 is input to this CDR circuit, the presence of the LPF 41 can suppress the 1.289 GHz frequency component input from the gating circuit 10 to the VCO 11, so 1.25 Gbps. The control voltage when the input data 4 is input can be maintained, and the oscillation frequency of the VCO 11 can be continuously set to the desired data rate frequency of 1.25 GHz. Therefore, even when the input data 4 of 1.25 Gbps is input immediately after the input data 4 of 10.3125 Gbps, it is possible to output the 1.25 GHz recovered clock 7 with little jitter and phase-synchronized instantaneously. Thus, in this embodiment, the same effect as that of the first embodiment can be obtained.

[Third Embodiment]
Next, a third embodiment of the present invention will be described. FIG. 4 is a block diagram showing the configuration of a CDR circuit according to the third embodiment of the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals. In this embodiment, a high pass filter (hereinafter referred to as HPF) 42 is provided between the output terminal of the gating circuit 10 and the input terminal of the VCO 11 instead of the BPF 40 of the first embodiment. The band of the HPF 42 is set such that when the CDR circuit is for 10.3125 Gbps, for example, a 10.3125 GHz signal is passed and a signal in a frequency band lower than 10 GHz is suppressed.

  This embodiment is a modification of the first embodiment, and is suitable for a high-speed signal side CDR circuit connected to a subsequent stage of an optical receiver of a dual rate PON system. That is, when the CDR circuit of this embodiment is for 10.3125 Gbps and the cutoff frequency of the HFP 42 is 10 GHz, even if the input data 4 of 1.25 Gbps is input, the gating circuit 10 Since the 10 GHz frequency component input to the VCO 11 can be suppressed, the control voltage when the 10.3125 Gbps input data 4 is input can be maintained, and the oscillation frequency of the VCO 11 can be set to a desired value. The data rate frequency can be constantly set to 10.3125 GHz. Therefore, even when the 10.3125 Gbps input data 4 is input immediately after the 1.25 Gbps input data 4, it is possible to output the 10.3125 GHz recovered clock 7 with little jitter and phase-synchronized instantaneously. Thus, in this embodiment, the same effect as that of the first embodiment can be obtained.

[Fourth Embodiment]
Next, a fourth embodiment of the present invention will be described. FIG. 5 is a block diagram showing the configuration of a CDR circuit according to the fourth embodiment of the present invention. The same components as those in FIGS. 1 and 4 are given the same reference numerals. The main difference between the present embodiment and the third embodiment is that the HPF 42 and the VCO 13 are provided after the VCO 11. Here, the cutoff frequency of the HPF 42 is set so as to pass a signal having a desired data rate frequency and suppress a signal having a frequency band lower than the desired data rate frequency.

  The VCO 13 basically has the same configuration as that of the VCO 11 shown in FIG. However, the VCO 13 is configured such that one input terminal of the NAND 110 in FIG. 2 is pulled up, and the clock signal from the VCO 11 passing through the HPF 42 and the reproduction clock of the VCO 13 itself are simultaneously input to the other input terminal. . With this configuration, the reproduction clock 7 synchronized with the output clock of the VCO 11, that is, the reproduction clock 7 synchronized with the phase of the input data 4 is output from the VCO 13. The recovered clock 7 output from the VCO 13 is frequency-divided by 1 / n by the frequency divider 25 and input to the frequency comparator 2. In the present embodiment, a reference clock 5 having a frequency 1 / n of the data rate of the input data 4 is input to the frequency comparator 2. The PLL composed of the frequency comparator 2, the VCO 13, and the frequency divider 25 performs closed-loop control so that the oscillation frequency of the VCO 13 matches the frequency n times the reference clock 5. Since the control signal 8 generated by this closed loop control is also input to the VCO 11, the VCO 11 oscillates at the same frequency as the VCO 13, that is, a desired data rate frequency.

  This embodiment is suitable for a high-speed signal side CDR circuit connected to a subsequent stage of an optical receiver of a dual rate PON system. That is, when the CDR circuit of this embodiment is for 10.3125 Gbps and the cutoff frequency of the HFP 42 is 10 GHz, even if the input data 4 of 1.25 Gbps is input, the gating circuit 10 10 GHz frequency component input to the VCO 11 can be suppressed. Furthermore, the transmission of the 10 GHz frequency component to the PLL-controlled VCO 13 can be significantly suppressed by the filter and buffer effect due to the free-running oscillation of the VCO 11 itself. Therefore, even when 1.25 Gbps input data 4 is input, the control voltage when 10.3125 Gbps input data 4 is input can be kept highly stable, and the oscillation frequency of VCO 13 can be set to a desired value. The data rate frequency can be constantly set to 10.3125 GHz.

  Furthermore, in this embodiment, since the HFP 42 is also provided between the VCO 11 and the VCO 13, it is possible to significantly suppress the transmission of the 10 GHz frequency component to the VCO 13. As a result, even when the 10.3125 Gbps input data 4 is input immediately after the 1.25 Gbps input data 4, the 10.3125 GHz recovered clock 7 with little jitter and phase-locked can be output instantaneously.

  Further, in the CDR circuit of the present embodiment, even if low-frequency noise is output from a previous stage amplifier or the like (not shown) when no signal is input, a low-speed or high-speed edge pulse corresponding to the frequency component of the noise. Is suppressed by the BPF 40, it becomes possible to continue setting the oscillation frequency of the VCO 13 to a desired frequency. Therefore, in this embodiment, it is possible to avoid an increase in response time due to low frequency noise input.

As described above, according to the present embodiment, even when a filter having a steep cutoff characteristic cannot be integrated on a semiconductor substrate by using multiple stages of filters, sufficient suppression of unnecessary frequency components input to the VCO 13 is achieved. This makes it possible to output the recovered clock 7 with higher frequency stability and less jitter as compared with the third embodiment.
In the present embodiment, two HPFs 42 are used. However, the present invention is not limited to this, and a configuration in which at least one of the two HPFs 42 is replaced with BPF or LPF may be used.
In the present embodiment, since there is a filter and buffer effect by the VCO 11, one of the two HPFs 42 may be omitted.

[Fifth Embodiment]
Next, a fifth embodiment of the present invention will be described. FIG. 6 is a block diagram showing the configuration of a CDR circuit according to the fifth embodiment of the present invention. The same components as those in FIGS. 1, 4 and 5 are denoted by the same reference numerals. In the present embodiment, the HPF 42 between the VCO 11 and the VCO 13 in the fourth embodiment is replaced with a buffer amplifier 14.

  As the buffer amplifier 14, a buffer amplifier whose driving power is preferably weaker than that of the final stage buffer (inverter 112 in the example of FIG. 2) of the VCO 13 is used. In the present embodiment, the provision of the buffer amplifier 14 makes it possible to suppress transmission of unnecessary signal components such as jitter to the VCO 13, and as in the fourth embodiment, noise and a desired data rate can be suppressed. Even when input data 4 other than the input data 4 is input, it is possible to continue to set the reproduction clock 7 to a desired data rate frequency, and input of a desired data rate immediately after the input data 4 other than the desired data rate. Even when data 4 is input, it is possible to output a recovered clock 7 with little jitter that is instantaneously phase-synchronized.

[Sixth Embodiment]
Next, a sixth embodiment of the present invention will be described. FIG. 7 is a block diagram showing a configuration of a CDR circuit according to the sixth embodiment of the present invention. The same reference numerals are given to the same configurations as those in FIGS. 1 and 4 to 6. This embodiment shows a modification of the fifth embodiment illustrated in FIG. The difference from the fifth embodiment is that a VCO 15 is provided between the VCO 11 and the VCO 13, the HPF 42 between the gating circuit 10 and the VCO 11 is deleted, the HPF 42 between the VCO 11 and the VCO 15, and the attenuator 30 between the VCO 15 and the VCO 13. It is to have established.

  The VCO 15 has the same configuration as the VCO 13, and the control signal 8 from the frequency comparator 2 is supplied to the frequency control terminal as in the VCO 11. As a result, the VCO 15 oscillates at the same frequency as the VCO 13, that is, a desired data rate frequency.

  The attenuator 30 has a function of attenuating the output of the VCO 15 and inputting it to the VCO 13. In the present embodiment, by providing the attenuator 30, transmission of unnecessary signal components such as jitter to the VCO 11 can be suppressed as in the case where the buffer amplifier 14 is provided. As the attenuator 30, a passive element such as a resistance element can be used. The attenuator 30 that can be configured with passive elements has the advantage that it can be configured to be very compact with zero power consumption. Furthermore, in the present embodiment, the addition of the VCO 15 makes it possible to further suppress the transmission of unnecessary signal components such as jitter to the VCO 13.

In the fifth and sixth embodiments, the HPF 42 and the buffer amplifier 14 (or attenuator 30) may be interchanged with each other. Further, a form using a buffer amplifier or an attenuator instead of the HPF 42, or a form using an HPF instead of the buffer amplifier 14 or the attenuator 30 may be used. Furthermore, BPF or LPF may be used instead of HPF 42.
In the sixth embodiment, at least one of a filter, a buffer amplifier, and an attenuator may be provided in the subsequent stage of the gating circuit 10.

  The present invention can be applied to a technique for reproducing a clock that is phase-synchronized with input data and performing retiming of the input data using this clock.

  2 ... frequency comparator, 3 ... flip-flop, 4 ... input data, 5 ... reference clock, 6 ... reproduction data, 7 ... reproduction clock, 8 ... control signal, 10 ... gating circuit, 11, 13, 15 ... VCO, 14 ... buffer amplifier, 25 ... frequency divider, 30 ... attenuator, 40 ... BPF, 41 ... LPF, 42 ... HPF.

Claims (8)

A gating circuit that outputs a pulse when input data transitions;
A first voltage-controlled oscillator that outputs a reproduction clock that matches the input data by adjusting the phase of the reproduction clock so as to match the timing of the output pulse of the gating circuit;
A data identification circuit for performing data identification of the input data based on the recovered clock;
A first filter that is provided between an output terminal of the gating circuit and an input terminal of the first voltage-controlled oscillator and passes a signal having a desired data rate frequency ;
A CDR circuit comprising: a frequency control circuit that supplies a frequency control signal for causing the first voltage controlled oscillator to oscillate at a desired data rate frequency to a frequency control terminal of the first voltage controlled oscillator . The CDR circuit of claim 1,
And a second voltage controlled oscillator provided between the output terminal of the gating circuit and the input terminal of the first filter.
The second voltage controlled oscillator adjusts the phase of the clock so as to match the timing of the output pulse of the gating circuit, thereby outputting a clock that matches the timing of the input data to the first filter ,
The CDR circuit , wherein the frequency control circuit supplies the frequency control signal to a frequency control terminal of the second voltage controlled oscillator . The CDR circuit of claim 2,
And a second filter provided between the output terminal of the gating circuit and the input terminal of the second voltage controlled oscillator.
The CDR circuit, wherein the output of the gating circuit is input and the signal of a desired data rate frequency is passed through the second filter. The CDR circuit according to claim 2 or 3,
A third voltage controlled oscillator provided between the output terminal of the gating circuit and the second voltage controlled oscillator or the input terminal of the second filter;
The third voltage controlled oscillator adjusts the phase of the clock so as to match the timing of the output pulse of the gating circuit, thereby outputting a clock that matches the timing of the input data to the second filter ,
The CDR circuit , wherein the frequency control circuit supplies the frequency control signal to a frequency control terminal of the third voltage controlled oscillator . The CDR circuit according to claim 4, wherein
A third filter provided between the output terminal of the gating circuit and the input terminal of the third voltage controlled oscillator;
The CDR circuit, wherein the output of the gating circuit is input and the signal of a desired data rate frequency is passed through the third filter. The CDR circuit according to any one of claims 1 to 5,
A CDR circuit, wherein at least one of the filters is replaced with an attenuator or a buffer amplifier. The CDR circuit according to any one of claims 1 to 6,
The CDR circuit is any one of a low-pass filter, a high-pass filter, and a band-pass filter. The CDR circuit of claim 1 ,
The frequency control circuit includes:
A frequency divider that divides the recovered clock by 1 / n (n is a positive integer);
A CDR circuit comprising a reference clock having a frequency 1 / n of a desired data rate frequency and a frequency comparator for comparing the output of the frequency divider and outputting the frequency control signal.

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