CN110429935B - Frequency-cutting phase-locked loop and algorithm applied by same - Google Patents

Abstract

The invention relates to the technical field of phase-locked loops, in particular to a frequency-cut phase-locked loop and an algorithm applied by the same, wherein the frequency-cut phase-locked loop comprises a voltage control oscillator and a digital correction circuit, and a frequency divider arranged between the voltage control oscillator and the digital correction circuit, the voltage control oscillator comprises an oscillating circuit and a switching frequency capacitor, the oscillating circuit outputs different frequencies through the switching frequency capacitor, the digital correction circuit is used for setting a switching frequency capacitance value, cutting a large range of frequencies into a plurality of intervals, and the digital correction circuit selects a correct frequency interval to lower the voltage control slope of an operation and meet the frequency requirement of the frequency interval, so that the area of a loop filter is greatly reduced, the output phase noise is improved, and the frequency-cut phase-locked loop can be packaged in a chip with smaller size.

Description

Frequency-cutting phase-locked loop and algorithm applied by same

Technical Field

The invention belongs to the technical field of phase-locked loops, and particularly relates to a frequency-cutting phase-locked loop and an algorithm applied by the frequency-cutting phase-locked loop.

Background

The phase-locked loop is a loop for locking the phase, and is a typical feedback control circuit, which uses an externally input reference signal to control the frequency and the phase of an internal oscillation signal of the loop, so as to realize the automatic tracking of the frequency of an output signal to the frequency of an input signal. A typical pll is shown in fig. 1, which includes a phase frequency detector (Phase and Frequency Detector, PFD), a Charge Pump (CP), a Loop filter (Loop PASS FILTER, LPF), a voltage controlled oscillator (Voltage Controlled Oscillator, VCO) and a frequency divider (Frequency Divider). The frequency divider is operated to down-convert the output of the voltage controlled oscillator to generate a signal FFB, the phase frequency detector generates a leading signal (UP) and a trailing signal (DN) according to the reference frequency FREF and the feedback frequency FFB, and the charge pump converts the signal into a charge to be injected into the loop filter to control the oscillator. Finally, the phase-locked loop will operate in a stable state, and the output frequency is the multiplying factor of the frequency divider by the input frequency.

In applications requiring a wide range of frequency support, the tuning range of a conventional vco must cover all frequency points, and thus a very large vco frequency slope is required. However, such designs are computationally expensive to produce as large noise and large area loop filters. The present patent proposes a design architecture that cuts the supporting frequency range into several small intervals and proposes a digital correction circuit that allows the overall system to select the correct frequency interval.

In a phase locked loop of US 20050264330A1, voltage levels (401, 405, 403, 407) are generated in an analog manner, and the locked voltage VC of each segment is compared with the voltage VC to determine whether the segment is correct, as shown in fig. 2. The implementation mode has three main problems that 1. The mode is free from cutting off the whole loop and is easy to be interfered, and excessive simulation components cannot effectively reduce the area requirement; 2. the manner in which the VC voltage is re-locked increases the correction time by a long period; 3. mismatch between analog components (401, 405, 403, 407, 421, 423, 425, 427) can affect the accuracy of the correction.

Disclosure of Invention

In order to overcome the shortcomings of the prior art, the invention provides a design architecture for cutting the supporting frequency range into a plurality of small sections and a digital correction circuit for the whole system to select the correct frequency section.

In order to achieve the above objective, the present invention provides a frequency-cut phase-locked loop, which includes a voltage-controlled oscillator and a digital correction circuit, and a frequency divider disposed between the voltage-controlled oscillator and the digital correction circuit, wherein the voltage-controlled oscillator includes an oscillating circuit and a switching frequency capacitor, the oscillating circuit outputs different frequencies through the switching frequency capacitor, and the digital correction circuit is used for setting the switching frequency capacitor value.

As a further improvement of the tangential phase-locked loop of the present invention: the digital correction circuit comprises a frequency counter and an algorithm comparator, wherein the frequency counter is provided with a first frequency counter and a second frequency counter, the first frequency counter and the second frequency counter are used for respectively inputting a reference frequency and a voltage control oscillator output frequency, and the algorithm comparator is used for comparing the input reference frequency and the voltage control oscillator output frequency to determine a switching frequency capacitance value to be set.

As a further improvement of the tangential phase-locked loop of the present invention: the set switching frequency capacitance value is recorded in the chip through the recording port by the recording circuit, the recording circuit comprises a system control module, an instruction control module, a variable corresponding module, a delta-sigma modulator, a recording control module and a correction core circuit, the system control module and the instruction control module are used for issuing correction instructions to the correction core circuit of the chip, the variable corresponding module and the delta-sigma modulator are used for setting divisors of the frequency divider, and the correction core circuit calculates the correct switching frequency capacitance value to be recorded in the chip.

An algorithm applied to the tangential phase-locked loop comprises the following steps,

H. Setting the switching frequency interval of the switching frequency capacitor to be SW=1 to SW=N;

i. setting the set voltage of the oscillator to be a fixed voltage VA;

j. the oscillator obtains output frequencies F1-FN in different frequency intervals under the fixed voltage VA;

k. the oscillator obtains output frequencies FFB 1-FFBN through a frequency divider;

Inputting the output frequencies FFB 1-FFBN obtained by the frequency divider into a first frequency counter of a digital correction circuit within a fixed time, inputting the reference frequency FREF into a second frequency counter of the digital correction circuit, and respectively obtaining FFB 1-N.CODE and FREF-CODE by the first frequency counter and the second frequency counter within a fixed time;

comparing FFB 1-N. CODE with FREF-CODE respectively, and obtaining absolute value difference CODE 1-N;

And N, a comparison algorithm of the digital correction circuit selects the minimum value of the absolute value differences CODE 1-N, and determines a switching frequency interval SW of the minimum difference, wherein the value of the SW is the SW set value closest to the ideal locking interval.

Advantageous effects

The phase-locked loop of the invention cuts a large range of frequencies into a plurality of sections, and the digital correction circuit selects the correct frequency section to lower the voltage control slope of the operation and meet the frequency requirement, thereby greatly reducing the area of the loop filter and improving the phase noise of the output, and being packaged in a chip with smaller size.

Drawings

Fig. 1 is a schematic diagram of a general phase-locked loop in the background art of the invention;

Fig. 2 is a schematic diagram of a phase locked loop according to the prior art;

FIG. 3 is a schematic diagram of a phase locked loop according to the present invention;

FIG. 4 is a schematic diagram of an oscillator according to the present invention;

FIG. 5 is a schematic diagram of a frequency bin correction structure according to the present invention;

FIG. 6 is a schematic diagram of an algorithm of the present invention;

FIG. 7 is a schematic diagram of a recording circuit according to the present invention;

FIG. 8 is a schematic diagram of the algorithm recording process according to the present invention;

In the figure: 1. phase frequency detector 2, charge pump 3, loop filter 4, voltage controlled oscillator 401, switching frequency capacitor 5, frequency divider 6, digital correction circuit 7, recording circuit.

Detailed Description

The technical scheme of the invention is further described below by the specific embodiments with reference to the accompanying drawings.

The design of the switching section of the vco is shown in fig. 4, which not only has the oscillation function, but also integrates the functions of the loop filter 3 and the charge pump 2 before the vco 4 in a common pll, i.e., filtering and capacitance, wherein the capacitance is a switching frequency capacitance 401 for controlling the output frequency of the vco 4, and fig. 4 is an example of a double switching frequency capacitance 401. However, as shown in fig. 5, assuming that the system needs to support the RING OSC, if the system is designed directly, an excessive voltage control frequency slope will be caused, a large area loop filter and poor noise output will be caused, so that we design the method to divide the region of the RING OSC into several regions of the LC OSC, so that the voltage control slope of the operation can be suppressed while the same frequency requirement range can be satisfied. However, such a design must include a digital correction circuit 6 that selects the correct interval, which would result in a loop lock error. The design is as shown in fig. 3, in operation, the digital correction circuit 6 sequentially switches the values of the frequency-switched capacitor 401 with different SW values, and the different SW values will make the voltage-controlled oscillator 4 output different frequencies, and then obtain different FFBs, i.e. feedback frequencies, through the operation of the frequency divider 5. The digital correction circuit 6 calculates the error between the different feedback frequencies FFB and the ideal value, selects the frequency interval with the smallest error, namely the correct frequency interval, and when the specific operation is performed, the correct frequency interval SW obtained after the frequency interval correction is performed initially, and sends the value to the recording port, and the recording circuit 7 records the value in the chip.

Specifically, a frequency-cutting phase-locked loop comprises a voltage-controlled oscillator 4 and a digital correction circuit 6, and a frequency divider 5 arranged between the voltage-controlled oscillator 4 and the digital correction circuit 6, wherein the voltage-controlled oscillator 4 comprises a switching frequency capacitor 401, the digital correction circuit 6 comprises a frequency counter and an algorithm comparator, and the frequency counter is provided with a first frequency counter and a second frequency counter.

Specifically, the recording circuit 7 includes a system control module, an instruction control module, a variable correspondence module, a delta-sigma modulator, a recording control module and a correction core circuit, as shown in fig. 7, where the system control module and the instruction control module are configured to issue a correction instruction to the correction core circuit of the chip, the variable correspondence module and the delta-sigma modulator are configured to set a divisor of the frequency divider, the digital correction circuit calculates a correct capacitance value of the switching frequency, and records the capacitance value into the chip, and a recording flow is shown in fig. 8.

Specifically, the algorithm applied to the frequency-cut phase-locked loop, as shown in fig. 6, is used to confirm the correct frequency interval SW, and includes the following steps,

A. Setting the switching frequency interval of the switching frequency capacitor 401 to sw=1 to sw=n;

b. Setting the set voltage of the voltage control oscillator 4 to be a fixed voltage VA;

c. The voltage control oscillator 4 obtains output frequencies F1-FN in different frequency intervals under the fixed voltage VA;

d. The voltage control oscillator 4 obtains output frequencies FFB 1-FFBN through the frequency divider 5;

e. The output frequencies FFB 1-FFBN obtained by the frequency divider 5 are input into a first frequency counter of the digital correction circuit 6 within a fixed time, the reference frequency FREF is input into a second frequency counter of the digital correction circuit 6, and the first frequency counter and the second frequency counter respectively obtain FFB 1-N.CODE and FREF-CODE within a fixed time;

f. comparing FFB 1-N. CODE with FREF-CODE respectively, and obtaining absolute value differences CODE 1-N;

g. the comparison algorithm of the digital correction circuit 6 selects the smallest value of the absolute value differences CODE1 to N, determines the switching frequency interval SW of the smallest difference, and the value of SW is the SW set value closest to the ideal lock interval.

For applications requiring large-scale frequency support, the frequency range is divided into several small sections and the digital correction circuit 6 allows the whole system to select the correct frequency section, so that the voltage control frequency slope can be reduced, large-area loop filtering and poor noise output can be avoided, and the pll can be packaged in a smaller-sized chip.

The present invention is not limited to the above-mentioned embodiments, but is intended to be limited to the following embodiments, and any modifications, equivalent changes and variations in the above-mentioned embodiments can be made by those skilled in the art without departing from the scope of the present invention.

Claims (2)

1. A frequency-cutting phase-locked loop, characterized by: the frequency divider is arranged between the voltage control oscillator and the digital correction circuit, the voltage control oscillator comprises an oscillating circuit and a switching frequency capacitor, the oscillating circuit outputs different frequencies through the switching frequency capacitor, and the digital correction circuit is used for setting the switching frequency capacitor value;

The digital correction circuit comprises a frequency counter and an algorithm comparator, wherein the frequency counter is provided with a first frequency counter and a second frequency counter, the first frequency counter and the second frequency counter are used for respectively inputting a reference frequency and a voltage control oscillator output frequency, and the algorithm comparator is used for comparing the input reference frequency and the voltage control oscillator output frequency to determine a switching frequency capacitance value to be set;

The set switching frequency capacitance value is recorded in the chip through the recording port by the recording circuit, the recording circuit comprises a system control module, an instruction control module, a variable corresponding module, a delta-sigma modulator, a recording control module and a correction core circuit, the system control module and the instruction control module are used for issuing correction instructions to the correction core circuit of the chip, the variable corresponding module and the delta-sigma modulator are used for setting divisors of the frequency divider, and the correction core circuit calculates the correct switching frequency capacitance value to be recorded in the chip.

2. An algorithm for use in a tangential phase locked loop as claimed in claim 1, wherein: comprises the steps of,

A. Setting the switching frequency interval of the switching frequency capacitor to be SW=1 to SW=N;

b. Setting the set voltage of the voltage control oscillator to be a fixed voltage VA;

c. The voltage control oscillator obtains output frequencies F1-FN in different frequency intervals under the fixed voltage VA;

d. The voltage control oscillator obtains output frequencies FFB 1-FFBN through a frequency divider;

e. The output frequencies FFB 1-FFBN obtained by the frequency divider are input into a first frequency counter of the digital correction circuit within a fixed time, the reference frequency FREF is input into a second frequency counter of the digital correction circuit, and the first frequency counter and the second frequency counter respectively obtain FFB 1-N.CODE and FREF-CODE within a fixed time;

f. Comparing FFB 1-N. CODE with FREF-CODE respectively, and obtaining absolute value differences CODE 1-N;

g. The comparison algorithm of the digital correction circuit selects the minimum value of the absolute value differences CODE 1-N, determines the switching frequency interval SW of the minimum difference, and the value of the SW is the SW set value closest to the ideal locking interval.