JPH01212918A - Digital pll circuit - Google Patents

Abstract

PURPOSE:To reduce an initial locking time and to suppress jitter of an output clock by detecting a phase difference between a reference clock and an output clock, deciding the quantity, setting a phase control speed of the output clock when the phase difference is large and setting the phase control speed lower when the phase difference is small. CONSTITUTION:A counter 20 and an up-down counter 21 apply count in the same direction in the transient state where the phase difference between the reference clock REFCLK and the output clock CMPCLK is increasing. As a result, the count of the counter 21 reaches 0 or 15 earlier and a selector 23 selects a control pulse of a differentiating circuit 47 to apply phase control continuously. When the phase of the output clock CMPCLK is nearly coincident with the phase of the reference clock REFCKL, the phase control is not applied till the count of the up-down counter 21 reaches 0 or 15. Thus, the locking time is reduced remarkably in the initial operation and when the locking is finished once, jitter is suppressed sufficiently.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Field of Application Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Action Examples Effects of the Invention [Summary] The present invention provides a digital PLL (phase The purpose is to provide a digital PLL circuit that can sufficiently suppress the jitter of the output clock while significantly shortening its initial pull-in time. means for determining the magnitude of the detected phase difference; means for setting a high phase control speed of the output clock when the phase difference is large; and means for determining the phase control speed of the output clock when the phase difference is small; means for setting the control speed low;
It is composed of

[Industrial Application Field 1] The present invention relates to a digital PLL (phase-locked loop).

This type of PLL circuit is used in tuned circuits, etc.
It is required that the initial pull-in time be significantly shortened and that the jitter of the output clock can be sufficiently suppressed.

[Prior Art] FIG. 4 is a block diagram showing the configuration of a conventional example, in which the phase of the output clock CMPCLK is the same as the reference clock REFCLK.
The movement is controlled in the direction that matches the direction.

Master clock M obtained by master clock oscillator 40
CK is given to the 1/2 frequency divider 41, and the frequency divider 41
Then, O-phase and π-phase clocks are generated by dividing the master clock MCK by 172.

These clocks are applied to a selector 42, and any clock selected by the selector 42 is applied to a 1/n frequency divider 44 via a gate 43.

The output clock CMPCLK obtained by this frequency divider 44 is given to a delay circuit 45, and the delay circuit 45 is provided with a selector 4.
The clock selected in step 2 is given as the timing clock.

Further, the output signal of the delay circuit 45 is given to the gate 43 via a gate 46, and the gate 46 is provided with a differentiation circuit 47.
A reference clock REFCLK is applied via the reference clock REFCLK.

Further, the output signal (control pulse) of the differentiating circuit 47 is given to a flip-flop 48 forming a toggle circuit, and the selector 42 is controlled by the output of the flip-flop 48.

The clock selected by the selector 42 is transmitted to the delay circuit 4.
5 is also applied to the differentiating circuit 47, and a gate 46 controlled by the control pulse obtained by the differentiating circuit 47 determines whether or not the selected clock of the selector 42 is outputted at the gate 43.

In the digital PLL circuit configured as described above, the delay circuit 45 and the differentiating circuit 47 form a phase comparator.

Then, when the clock is switched by the selector 42 based on the output of the differentiating circuit 47, one clock pulse is added to the output clock CMPCLK due to this switching, and as a result, the phase of the output clock CMPCLK matches the reference clock REFCLK. and is controlled.

Also during phase delay control, the clock is switched by the selector 42 based on the output of the differentiating circuit 47; The output becomes H level, and the AND gate 43 is closed.

Therefore, one clock pulse output from the selector 42 is masked, and therefore one clock pulse is deleted, and as a result, the phase of the output clock CMPCLK is controlled to be delayed so as to match the reference clock REFCLK.

Furthermore, the pull-in time during initial operation is determined by the master clock MCK and the reference clock REFCLK.

The pull-in time is determined by the phase difference between the output clock CMPCLK and the reference clock REFCLK (
SeC) is the value T, and the frequency of the master clock MCK (H
2) is the value M, and the frequency of the reference clock REFCLK (H
2) is a value R, and when each is shown, it is expressed by the following formula.

Pull-in time = T/(2/M)・1/R=TM/2R・
...Equation (1) Note that the frequency division ratio n of the 1/n frequency divider 44 is expressed by the following equation.

Frequency division ratio n=M/2R... Equation (2) [Problem to be solved by the invention] Here, in order to suppress the jitter of the output clock CMPCLK, the master clock frequency M is set high, and It is necessary to increase the integral constant of the circuit by increasing the interval between phase controls.

In that case, as understood from equation (1) above, the pull-in time T during the initial operation becomes longer.

For this reason, in the past, it was necessary to set the master clocker frequency M and the above-mentioned integral constant by sacrificing or compromising either the pull-in time during initial operation or the suppression of jitter, and therefore a high-performance circuit was required. The problem was that it could not be configured.

The present invention has been made in view of the above-mentioned conventional problems,
The purpose is to provide a high-performance digital PLL that can significantly reduce the pull-in time during initial operation while sufficiently suppressing subsequent jitter.

[Means for Solving the Problems] In order to achieve the above object, the circuit according to the present invention has the following features:
It is configured as shown in the figure.

In the means 10 shown in the figure, the phase difference between the reference clock and the output clock is detected.

The means 12 then determines the magnitude of the phase difference detected by the means 10.

Furthermore, when the means 12 determines that the phase difference is large, the phase control speed of the output clock is set high by the means 14.

Further, when the means 12 determines that the phase difference is small, the phase speed of the output clock is set low by the means 16.

[Function] In the present invention, the phase control speed of the output clock is increased in consideration of the responsiveness of the circuit during transient periods such as initial operation, and the phase control speed is set low during steady operation in consideration of the stability of the circuit. .

Therefore, the transient state immediately shifts to the steady state, and once the steady state is reached, jitter is sufficiently suppressed.

Note that the phase control speed can be set by switching the internal clock or switching the integration constant.

[Embodiments] Hereinafter, preferred embodiments of the circuit according to the present invention will be described based on the drawings.

FIG. 2 shows the configuration of an embodiment in which the integral constant is switched, and the switching is performed by a counter 20. Up/down counter 21. Gate 22, selector 23. Flip-flop24. This is done by gate 25.

Note that the same members as those in FIG. 4 described above are given the same reference numerals, and their explanation will be omitted.

Further, the means 10 in FIG. 1 includes a differentiating circuit 47, the means 12 includes a counter 20 and an up/down counter 21,
4 and counter 20. Up/down counter 21. Gate 22. Selector 23. A flip-flop 24 and a gate 25 connect the means 16 to a counter 20. Up/down counter 21. Gate 22. Selector 23. Flip-flop 24 and gate 25 correspond to each other.

In FIG. 2, the output signal (control pulse) of the differentiating circuit 47 is sent to the counter 20. CLK of up/down counter 21
are respectively given to the inputs, and the up/down counter 21
The output signal of the delay circuit 45 is given to the UP/DWN input of the circuit.

The CARR output and BORR output of the up/down counter 21 are inputted to a selector 23 via a gate 22, and the other input of the selector 23 is connected to a differentiating circuit 4.
7 output signals are given.

Further, the selection output of the selector 23 is applied to a gate 46, and also to a flip-flop 48.

This selector 23 is controlled by the Q output of a flip-flop 24, and the output of the gate 22 is given to the SET input of the flip-flop 24.

The output of the counter 20 is given to the RESET input of the flip-flop 24, and the output is sent to the gate 2.
2 through the gate 25 along with the output of the counter 20.2. They are respectively applied to the LOAD inputs of the up/down counter 21.

This embodiment has the above configuration, and its operation will be explained below.

The counter 20 counts up to a count value of 9, and at this time the count-up signal becomes H level as shown in FIG. 3 (A>).

The up/down counter 21 is preset to a count value of 7, and when the count value reaches O or 15, H level BORR and CARR outputs are obtained as UP/DOWN outputs as shown in FIG. 3 (A>).

Therefore, if the up/down counter 21 counts up or down eight times in a row before the counter 20 counts up, the BORR or CARR output becomes H level.

When the flip 70 knob 24 is set by this, H
The control pulse of the differentiating circuit 47 is selected by the selector 23 at the Q output of the flip 70 knob 24 which has reached the level.

In other words, when the phase of the output clock CMPCLK changes rapidly in the same direction with respect to the reference clock REFCLK, the output pulse C is changed in each phase control period using the phase difference T between the O phase and the π phase of the master clock MCK as a unit.
MPCLK is continuously phase controlled.

Therefore, during a transition period where the phase difference between the reference clock REFCLK and the output clock CMPCLK becomes large, such as during the initial pull-in operation, the counter 20 and the up/down counter 21 count in the same direction, and as a result, the up/down counter 21 count value is O or 1
5, the control pulse of the differentiating circuit 47 is selected by the selector 23, and phase control is performed continuously.

Therefore, as shown in Figure 3 (B), the master clock MCK
The output clock CM is calculated using the phase difference T between the O phase and the π phase as a unit.
PCLK is controlled at high speed in a direction that matches the phase of reference clock REFCKL.

On the other hand, when the output clock CMPCLK is substantially in phase with the reference clock REFCKL, phase control is not performed until the count value of the up/down counter 21 reaches the value O or 15.

Therefore, as shown in FIG. 3(C), the error t accumulates every time the control period T elapses, and when this error t accumulates to a certain extent, the output clock C moves in the direction in which the accumulated error disappears.
Phase control is performed on MPCLK.

Therefore, in the steady state, phase control is performed intermittently.

That is, at this time, the integral constant of the circuit is switched and increased, and as a result, jitter is sufficiently suppressed.

As explained above, according to this embodiment, continuous phase control is performed during transient periods, thereby reducing the integral constant of the circuit and switching to a higher phase control speed, and intermittent phase control is performed during steady state conditions. By doing this, the integral constant of the circuit increases and the phase control speed is switched to a lower one.

Therefore, the pull-in time during initial operation can be significantly shortened, and once the pull-in is completed, jitter can be sufficiently suppressed, making it possible to construct a high-performance circuit.

[Effects of the Invention] As explained above, according to the present invention, the phase control speed of the output clock is increased or decreased depending on the magnitude of the phase difference between the reference clock and the output clock, so the pull-in time during initial operation can be significantly reduced. After that, it is possible to construct a high-performance circuit that can sufficiently suppress the jitter of the output clock while reducing the time to .

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the invention, FIG. 2 is a block diagram showing the configuration of an embodiment, FIG. 3 is a diagram explaining the operation of the embodiment, and FIG. 4 is a block diagram showing the configuration of a conventional example. 40... Master clock oscillator 41... 1/2 frequency divider 42... Selector 43... Gate 44... 1/n frequency divider 45... Delay circuit 46... Gate 47... ...Differential circuit 48...Flip 70 knob 20.21...Counter 23...Selector 24...Flip-flop speed High Speed Low Explanation of the principle of the invention Figure l

Claims (1)

[Scope of Claims] Means (10) for detecting a phase difference between a reference clock and an output clock; means (12) for determining the magnitude of the detected phase difference; and a means (12) for determining whether the phase difference is large. means (14) for setting a high phase control speed of the output clock when the phase difference is small; and means (16) for setting the phase control speed of the output clock low when it is determined that the phase difference is small. A digital PLL circuit comprising: