JPH03270412A - Pll circuit - Google Patents

Abstract

PURPOSE:To pull in a phase at high speed to disturbance without increasing jitter by providing a phase pull-in means to forcedly pull the phase of an output signal from a phase control circuit into the phase of an input signal when phase difference between the input signal and the output signal exceeds a certain range. CONSTITUTION:The phase matching means is composed of an N frequency dividing circuit 6, rise differentiating circuit 7 and AND gate circuit 11 so as to be operated when the disturbance is inputted. The phase matching means is composed of a timer 9 and an AND gate circuit 12 so as to be operated when an operation is initialized. These phase matching means 6, 7 and 11 detect the the leading edge of the input phase, for example, and with this detection signal as a reference, the output phase is set and outputted. Therefore, the output phase is forcedly pulled into the input phase. Thus, without increasing jitter, the phase difference generated by the disturbance can be converged at high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a PLL circuit used in, for example, a transmission device.

[Prior art] PLL (Phase-Looked Loop)
The circuit includes a phase comparator that detects the phase difference between the input signal phase (hereinafter referred to as input phase) and the output signal phase (hereinafter referred to as output phase), and a loop filter that integrates the detected phase difference. , and a phase control circuit that advances or delays the output phase based on the output of the loop filter, and can obtain an output phase synchronized with the input phase. Furthermore, digital PLL circuits have also been developed for the purpose of improving performance and integrating them into ICs.

Note that many proposals have been made regarding PLL circuits. For example, regarding digital PLL, a document summarizing the configuration method of a phase comparator and a loop filter phase control circuit is written by Dr. Roland E Be5 [
rPhase Looked LoopsJl (4
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There is LL).

[Problems to be Solved by the Invention] Incidentally, in a PLL circuit, it is desired that the phase can be pulled in in a short time, and that the convergence time at the initial stage of operation or when a disturbance occurs is short.

Conventionally, in PLL circuits, shortening of phase pull-in time,
Alternatively, as a technique for shortening the convergence time of the output phase when a disturbance occurs, there is a technique for reducing the threshold value for the integral value of the phase error when the loop filter outputs the phase control signal. There is a method of increasing the phase control amount.

However, for the former, phase control is performed even for a slight phase shift, and for the latter,
The problem is that it causes an overshoot for the correction of the phase error, and in both cases increases the jitter of the output phase.

Conventionally, there are the following techniques as techniques for solving this type of purpose.

First, as described in Japanese Patent Application Laid-Open No. 61-196619, initial reset of the divider that divides the output signal of the voltage controlled oscillator VCO by the edge of the reference signal input to the phase comparator circuit when the power is turned on. There is a technique in which the frequency divider output signal is forcibly synchronized with the reference signal, the two human input signals of the phase comparator circuit are phase synchronized, and the phase is instantaneously pulled in.

However, this technique has the problem that it can only cope with instantaneous phase pull-in during initial operation, and does not take disturbances into consideration.

In addition, as described in Japanese Patent Application Laid-Open No. 1-212918, the phase difference between the reference clock and the output clock is detected,
By determining the magnitude and setting the phase control speed of the output clock high when the phase difference is large and setting the phase control speed low when the phase difference is small, the initial pull-in time can be shortened and the jitter of the output clock can be reduced. There are techniques to suppress this.

However, this technique has a problem in that the circuit configuration becomes complicated because the phase and control speed are changed depending on the magnitude of the phase difference. Moreover, this technique merely shortens the phase pull-in time.

There is a problem in that no consideration is given to achieving near-instantaneous retraction during initial operation and during disturbances.

Furthermore, as described in Japanese Patent Application Laid-Open No. 61-265922, the phase difference between the feedback signal and the input signal is divided into certain ranges, and the integration time of the low-pass filter is determined according to the divided phase difference range. By rapidly changing the constant and the amount of phase correction of the voltage controlled oscillator,
There is a technique that aims to shorten the pull-in time and reduce the amount of jitter.

However, this technique has the disadvantage that the circuit configuration is complicated because the integration constant of the low-pass filter is changed or the amount of phase correction of the voltage-controlled oscillator is changed according to the range of the phase difference. Further, this technique, like the technique disclosed in Japanese Patent Application Laid-Open No. 1-212918, has a problem in that it does not take into consideration the realization of rapid pull-in during initial operation and during disturbances.

An object of the present invention is to provide a PLL that can perform rapid phase pull-in in response to disturbances without increasing jitter.
An object of the present invention is to provide a circuit and a PLL control method.

[Means for solving the problem] The above purpose is to detect the difference between the input phase and the output phase, integrate the phase difference, and advance or delay the output phase based on the integral value to perform phase control. In this case, when the phase difference between the input phase and the output phase exceeds a preset range, the edge of the input phase is used to force the output phase to match the input phase. To achieve this, the present invention provides a phase comparator that outputs a phase difference signal proportional to the phase difference between an input phase and an output phase, an integrator that integrates the output of the phase comparator, and an output of the integrator. and a phase control circuit that controls the phase of the output phase, and when the phase difference between the input phase and the output phase exceeds a certain range, the phase adjustment that forcibly matches the output phase of the phase control circuit to the input phase. PL with means
An L circuit is provided.

The phase matching means may be added with a function of forcibly matching the output phase to the input phase at the initial stage of operation.

The PLL circuit can also have a function of initializing the integrator when performing the forced internal phase matching. That is, a function to stop the operation of the integrator can be added. Additionally, a function for holding the current value of the integrator output can be added.

Further, according to the present invention, there is provided a detecting means for detecting an edge of an input signal phase input to a PLL circuit, a determining means for determining whether a phase difference between an input signal and an output signal exceeds a preset range, and the above-mentioned output phase setting means for setting the phase of the output signal in synchronization with the detected edge when the phase difference exceeds a preset range;
A phase-introducing circuit is provided.

[Operation] The phase comparator detects a phase difference between an input phase and an output phase, and outputs, for example, a phase difference signal having a pulse width proportional to this phase difference. The integrator receives this phase difference signal and
Integrate this. Then, when the integral value exceeds a threshold value, a control signal is output.

At this time, since the phase difference signal has opposite polarity to the phase lead and lag, slight fluctuations in phase are ignored. Then, based on the control signal, the phase control circuit, for example,
The output phase is set and output based on a signal obtained by variably dividing a frequency several times higher than the input phase information.

These operations execute phase synchronization control in a steady state.

Here, when the phase difference between the input phase and the output phase becomes large due to a disturbance, the above-mentioned phase synchronization operation is executed.
In this case, rapid retraction cannot be performed.

Therefore, the phase adjustment means 1 detects, for example, the rising edge of the input phase, and sets and outputs the output phase based on this detection signal. As a result, the output phase is forcibly aligned with the input phase. Therefore,
Almost instantaneous phase pull-in becomes possible.

Note that the phase matching means can be configured using, for example, a divider, a differentiating circuit, and a gate circuit, so that the circuit configuration does not become complicated.

In addition, at the initial stage of operation, an external initial setting signal (
For example, by receiving the activation signal and operating the phase matching means as described above, rapid phase pull-in is possible.

Furthermore, by providing a function that stops the integrator operation or holds the current value when the phase difference between the output signal and the input signal exceeds a certain range, it is possible to maintain the integrator operation in a steady state after performing rapid phase pull-in. When performing phase synchronization, it is possible to suppress the occurrence of integration errors.

(Margins below) [Examples] Examples of the present invention will be described below with reference to the drawings.

FIG. 1 shows an example of the configuration of a digital PLL circuit which is an embodiment of the present invention.

The digital PLL circuit shown in FIG. 1 includes a phase comparator 2 that outputs a phase difference signal proportional to the phase difference between an input phase l and an output phase 10, and a signal obtained by integrating the output of the phase comparator 2. A loop filter 3 outputs a control signal that controls the phase of the output phase 10 when a certain value is exceeded, and the input phase 1
a phase control circuit 4 that sets an output phase based on a signal obtained by variably dividing a frequency several times higher than the frequency of the signal using the control signal output from the loop filter 3;
Equipped with.

Further, the PLL circuit of this embodiment detects the rising edge of the input phase 1 and outputs the phase matching reference signal d, and includes a rising differentiation circuit 7 which functions as a phase matching reference signal detecting means and an external Reset signal 8 input from
a timer 9 which is activated by the release of , and outputs an initial setting signal S which remains at a high level for a certain period of time at the initial stage of operation; a phase out-of-phase determination range signal C output from the phase control circuit 4; an AND gate circuit 11 for detecting phase deviation by calculating the AND of the initial setting signal from the timer 9, and an AND gate circuit 11 for calculating the AND of the initial setting signal from the timer 9 and the phase adjustment reference signal d to determine whether or not the initial phase has been pulled in. It includes a gate circuit 12 and an OR gate circuit 13 which takes the logic axis of the outputs of these AND gate circuits 11 and 12 and outputs a load signal a to the phase control circuit. These constitute a phase pull-in circuit at the initial stage of operation and at the time of disturbance input.

The loop filter 3 functions as an integrator.

For example, as shown in FIG. 3, it is constructed using an n-bit 7-up down counter. This up/down counter can load 110 I+ onto the DO~Dnl terminals. This load is applied to the LOAD terminal at the fall of load signal a or reset signal 8 (reset release).
This is done by In addition, the phase difference signals UP and DWN
In response to this, in the case of UP, the clock pulse of frequency f1 is counted up, and in the case of DWN, it is counted down. When the count value overflows, a phase UP signal is output from the OVF terminal, and when the count value underflows, a UDFUP terminal phase DWN signal is output as a phase control signal. The frequency f1 of the clock pulse is set to be several times higher than the frequency of the input phase, for example, about 80 times higher.

Note that the counter used in the loop filter 3 may be provided with an up counter and a down counter separately, and although a loop filter is used in this embodiment, the counter is not limited to this, and may be used similarly as an integrator. As long as it works, it's fine.

The phase control port 11I4 includes a variable division port 15 and an N frequency divider circuit 6.

For example, as shown in FIG. 4, the variable frequency dividing circuit 5 is composed of a counter, receives the phase UP signal and the phase DWN signal, variably divides the clock pulse of one frequency f2, and divides the clock pulse of one frequency f3 into a clock pulse of frequency f3. Output clock pulse. The variable frequency divider circuit 5 is configured to operate as follows with respect to the phase UP signal and the phase DWN signal.

That is, when neither the 1-phase UP signal nor the phase DWN signal is input to the UP terminal and the DWN terminal,
Counts N clock pulses of f2 and outputs f3 clock pulses of f2/N. In this case, output phase 1
The phase of o remains unchanged. Furthermore, when the phase UP signal is input to the UP terminal, it counts N-1 f2 clock pulses and outputs f2/(N-1) f3 clock pulses. In this case, the phase of the output phase 1o will advance. On the other hand, when the phase DWN signal is input to the DWN terminal, N1,01 clock pulses of f2 are counted and f
Outputs 2/(N+1) f3 clock pulses. In this case, the phase of the output phase 1o will be delayed. Note that N is 1 in this embodiment, and is 4.

As shown in FIG. 5, the N frequency divider circuit 6 is constituted by, for example, a ring counter. This counter is
An output terminal outputs a pulse signal (output phase 10) whose high and low states are inverted every time n clock pulses are counted, and a pulse signal (phase It has an O3 terminal that outputs an out-of-range determination range signal C). In addition, in this embodiment, which has terminals DO to Dn2 for loading count values,
When the load signal a is input to the LOAD terminal, the count value n is loaded to the DO=Dn2 terminal. Note that f3 is set to be a frequency N times the frequency of input phase 1. Further, the load value n is set so that the phase difference between the input phase 1 and the output phase 10 is O.

Said N frequency divider circuit 6. The rising differentiation circuit 7 and the AND gate circuit 11 constitute a phase matching means that functions when a disturbance is input. Further, in the case of this embodiment, the timer 9 and the AND gate circuit 12 constitute a phase matching means that functions at the initial stage of operation. These are coupled by an OR gate circuit 13.

Next, the operation of this embodiment configured as described above will be explained with reference to FIG. 2 and FIG. 6 as well.

The phase difference between the manual phase 1 and the output phase 10 is detected by the phase comparator 2 and output to the loop filter 3 as phase difference signals UP and DWN.

The phase difference signals UP and DWN are pulse signals having a pulse width proportional to the phase difference, as shown in FIG. 6(a), and the phase difference signal UP is counted up and the phase difference signal DWN is counted down. will be counted. Further, the subtraction count value between the up count and the down count becomes the integral value of the loop filter 3. When this integral value reaches a preset value (for example, one or several f1 clock pulses) by up-counting, an overflow occurs and a phase UP signal is output from the OVF terminal.

Further, when the count reaches the count value, an underflow occurs and the phase DWN signal is output from the UDF terminal.

When there is almost no phase difference between the input phase 1 and the output phase 10, the variable frequency divider circuit 5 counts four pulses and outputs one period of pulses, as shown in FIG. 6(b). , f2/4 branching is performed. Furthermore, when the above-mentioned phase UP signal is input to the UP terminal, as shown in FIG. The f3 pulse rises in response to the rise of the f2 pulse.

Therefore, the phase of the f3 pulse advances. moreover,
When the phase DWN signal is input to the DWN terminal, Fig. 6 (
As shown in b), for example, if the f2 clock pulse is set to 5
When the phase DWN signal falls at the time of counting, the f3 pulse rises in response to the rise of the next f2 pulse.

Therefore, the phase of the f3 pulse will be delayed.

In this way, the variable frequency divider circuit 5 performs phase synchronization by advancing or delaying the phase of the output phase 10 when a phase difference occurs between the input phase 1 and the output phase 10.

As shown in FIG. 16(c), the N frequency divider circuit 6
3 is frequency-divided by N (N22 in this embodiment), and the result is outputted as an output phase 10, and is also sent to the phase comparator 2 as a comparison phase. It also outputs a phase deviation determination range signal C whose phase is shifted by 174 cycles from the output phase 10, and sends this signal to the AND gate circuit 11.

Further, the rise differentiation circuit 7 differentiates the input phase 1, detects its rise timing, and outputs this as a phase matching reference signal d.

First, the initial state of operation will be described. In this case, since the reset signal 8 is input to the loop filter 3, the loop filter 3 outputs neither the phase UP signal nor the phase DWN signal. Therefore, the variable frequency divider circuit 5 performs N frequency division. Therefore, as shown in FIG. 2, the phase difference between input phase 1 and output phase 10 does not become so small.

Next, when the reset signal becomes low level and the reset is released, timer 9 is activated, and as shown in Figure 2, the output becomes high level for a certain period of time and the initial setting signal is output. . The AND gate circuit 12 uses this initial setting signal S to determine whether or not the initial phase is pulled in.

That is, when the initial setting signal S is at a high level, it is determined that the initial phase is being pulled in, the phase matching reference signal d is passed, and the N frequency dividing circuit 6 is output as the load signal a.
Send it to the LOAD terminal of.

When the load signal a is inputted to the N frequency divider circuit 6, the D
The count value n is loaded into the O to Dn2 terminals.

As a result, as shown in FIG. 6(c), the phase of the output phase 10 is reversed. That is, at this point, the rising edge of the output phase 10 is forced to match the rising edge of the input phase 1. In addition, in the initial stage of operation, considering that the phase difference is considered to be large and that the fluctuation of the phase difference is also large, multiple pulses (for example, The setting is 3 pulses). Therefore, the above phase matching operation is repeated during the period when the initial setting signal is at a high level.

Next, as shown in FIG. 2, the operation will be described when a disturbance is input for some reason and the phase difference between the input phase 1 and the output phase lO becomes large.

In this case, the out-of-phase determination signal C output from the N frequency divider circuit 6 is sent to the AND gate circuit 11. Further, a pulse indicating the rising edge of input phase 1 is inputted to the AND gate circuit 11 from the rising differentiation circuit 7 as the 1 phase matching reference signal d. The phase out-of-phase determination signal C is
As shown in FIG. 6(c), this is a pulse signal having the same waveform as the output phase 10, but with a phase shift of 174 cycles. Therefore, the out-of-phase determination signal C is at a low level in the range before and after the rising edge of the output phase 10, and is at a high level at other positions. Therefore, if the phase matching reference signal d is input while the phase deviation determination signal C is at a high level, it is determined that the input phase and the output phase are significantly out of phase. Therefore, the AND gate circuit 11 inputs the phase matching reference signal d to the LOAD terminal of the N frequency divider circuit 6 as the load signal a via the OR gate circuit 13.

As a result, the next pulse of the output phase 10 rises in accordance with the input of the phase matching reference signal d, and the phase of the output phase 10 is forcibly matched to the input phase 1, as in the case at the initial stage of the operation described above.

In this way, according to this embodiment, the output phase can be forcibly synchronized with the input phase in addition to the normal phase synchronization operation at the initial stage of operation and at the time of disturbance input. Therefore, even when the phase difference between the input phase and the output phase is large, the phase difference can be rapidly converged.

Note that the load signal a is the LOA of the loop filter 3.
It is also input to the D terminal. As a result, loop filter 3
is loaded with O. Therefore, the loop filter 3 has an integral value of O regardless of the phase difference signal of the phase comparator 2. Therefore, when returning to normal phase synchronization control after forced phase matching is performed, the integral error of the loop filter 3 can be suppressed.

In the embodiments described above, the phase matching function and O value loading of the loop filter at the initial stage of operation can be omitted.

Further, in the above embodiment, the phase control circuit 4 is constituted by the variable frequency dividing circuit 5 and the N frequency dividing circuit 6, but by adding the function of the N frequency dividing circuit 6 to the variable frequency dividing mill Mr5. , N frequency dividing circuit may be omitted.

In the above embodiment, an example is shown in which the output phase 10 is forced to match the phase of the input phase 1 using a phase matching reference signal. It is also possible to set the output phase 10 to have any phase relationship with respect to the input phase.

For example, the load value n may be set to a value different from the full count value of the N frequency divider circuit 6. Further, the rising differentiation circuit 7 can also be made into a falling differentiation circuit.

Further, in the above embodiment, the phase deviation determination signal C has the same waveform as the output phase 10, as shown in FIG. 6(Q),
Although pulse signals with a phase shift of 1/4 period are used, the present invention is not limited to this. For example, it is also possible to use pulses with smaller or larger deviations than 1/4 period.

Further, the above embodiment includes a digital PLL circuit having a phase comparator, an integrator, and a phase control circuit, a rise differentiation circuit 7, a timer 9. It can be constructed by adding AND gate circuits 11 and 12 and an OR gate circuit 13. Therefore, cost reduction and space saving can be achieved. Furthermore, all circuit elements can be realized with a simple circuit configuration using digital ICs and gate arrays.

Next, regarding another embodiment of the present invention, FIGS.
This will be explained with reference to the figures.

FIG. 7 and FIG. 8 show respective configuration examples of an analog PLL circuit which is an embodiment of the present invention. In the following description of the embodiment, descriptions of functions similar to or common to those of the embodiment shown in FIG. 1 will be omitted or simplified.

The analog PLL circuit shown in FIG. a low-pass filter 73 that outputs a control voltage signal for controlling the output phase, a phase control circuit 74 that forms an output phase 80 according to the control voltage output from the low-pass filter 73, and detects the rising edge of the input phase 71;
and a rising differentiation circuit 77 which outputs a phase matching reference signal d and functions as a phase matching reference signal detection means.

It is configured to include an AND gate circuit 78 that performs a logical product of the output phase 80 outputted from the phase control circuit 74 and the phase matching reference signal d to detect a phase shift.

The phase control circuit 74 includes a voltage-controlled crystal oscillator (VCXO) 75 that oscillates at a frequency corresponding to the control voltage output from the low-pass filter 73, and a voltage-controlled crystal oscillator (VCXO) 75 that divides the output of the VCXO 75 by N to obtain an output phase of 80. A circumferential circuit 76 is provided.

In addition to the frequency dividing function described above, the N frequency dividing circuit 76 also has a function of outputting a phase deviation determination range signal C and a function of loading a count value n, similarly to the N frequency dividing circuit 6 in the embodiment shown in FIG. have

The N frequency divider circuit 76, rise differentiation circuit 77, and AND gate circuit 78 constitute a phase matching means that functions when a disturbance is input.

Next, a phase matching operation at the time of disturbance according to this embodiment will be explained.

When the out-of-phase determination range signal C is at a high level and the phase matching reference signal d is output, the AND gate circuit 7
8 determines that the phase is largely shifted due to disturbance, and sends the phase adjustment reference signal d to the LOAD terminal of the N frequency divider circuit 76 as the load signal a. In response to this, the N frequency divider circuit 76 loads the count value n. This allows the first
As in the embodiment shown, the output phase 80 rises.

Therefore, the phase of the output phase 80 is forced to match the phase of the input phase 71.

In this way, this embodiment also has the effect of rapidly performing phase pull-in in response to a large phase deviation that occurs during the random input.

Next, the analog PLL circuit shown in FIG. 8 is basically constructed by including the components of the embodiment shown in FIG. 7 above. That is, 1 phase comparison m72 and low pass filter 7
3 and a phase control circuit 74.

It is configured to include a rise differentiation circuit 77 and an AND gate circuit 78. Note that the description of these items will not be repeated.

In addition, the analog PLL circuit of this embodiment has a structure different from that of the embodiment shown in FIG.
The sample and hold circuit 81 is inserted and connected between the phase control amount 11174 and the phase control amount 11174, and a sample and hold control circuit 82 that controls the operation of the sample and hold circuit 81.

The sample and hold circuit 81 includes a switch SWI that turns on and off the input of the control voltage signal from the low-pass filter 73, a capacitor C1 that holds the control voltage signal, and an amplifier AP that amplifies the terminal voltage of the capacitor C1. .

The sample hold control amount Nt82 is set by the load signal a outputted from the AND gate circuit 78, and the flip-flop circuit 83 controls the on/off of the switch SW1 by its Q output, and the out-of-phase determination range signal C is inverted. The AND gate circuit 84 gates the phase matching reference signal d using the signal obtained by gating the phase matching reference signal d to obtain the a' signal, and counts this a' signal until it reaches a predetermined count value, and when the count value is reached, the output goes high. level, and a counter 85 that is reset by the load signal a.

Next, the operation of this embodiment will be explained, focusing on the differences from the embodiment shown in FIG. 7 above.

When the output phase 80 is largely out of phase with the input phase 71 and the load signal a is output from the AND gate circuit 78 as in the embodiment shown in FIG. When sent to the LOAD terminal of the circuit 76,
The N frequency divider circuit 76 loads the count value n. As a result, similarly to the embodiment shown in FIG.
stands up. Therefore, the phase of the output phase 80 is forced to match the phase of the input phase 71.

At the same time, this load signal a is sent to the flip-flop circuit 83 and set.

As a result, the Q terminal of the flip-flop circuit 83 becomes high level, and the switch SW of the sample hold circuit 81
Turn I off. As a result, the input voltage of the VCXO 75 is held.

On the other hand, the counter 85 continues up to a preset count value.
Count the a' signal. This setting value is.

For example, it is set to a value sufficient to secure the time required for forced phase alignment using the load signal a. This counter 85
When the output signal a'' becomes high level, the flip-flop circuit 83 is reset.

Then, the switch SWI of the sample hold circuit 81 is turned on. The control voltage signal of the low-pass filter is now input to the vcxo 75 again.

Note that the counter 85 is reset by the load signal a.

According to this embodiment, in addition to the effects of the embodiment shown in FIG.
This has the effect of suppressing the integration error of 3.

Although the embodiments shown in FIGS. 7 and 8 do not have a phase matching function at the initial stage of operation, it goes without saying that these functions can be provided.

Furthermore, in the embodiments shown in FIGS. 7 and 8 above, v
CXO is used, but the invention is not limited to this, and a wide variety of voltage controlled oscillators (VCOs) can be used.

In each of the above embodiments, when the phase difference between the input phase and the output phase is large, the phases are forcibly matched. Therefore, the threshold value for the integral value of the phase error of the loop filter and the low-pass filter is lowered. , phase control circuit 1
This eliminates the increase in jitter that occurs with conventional means such as increasing the amount of phase control.

The above embodiments are used, for example, in phase synchronization control that requires jitter suppression in a 15DN digital subscriber line transmission device. It is also widely used for other phase synchronization control.

[Effect of the invention] According to the invention, without increasing jitter.

The phase difference caused by disturbance can be rapidly converged.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a configuration example of a digital PLL circuit which is an embodiment of the present invention, FIG. 2 is a timing chart showing the operation of the above embodiment, and FIG. 3 is a diagram of a loop filter used in the above embodiment. A block diagram showing an example,
FIG. 4 is a block diagram showing an example of the variable frequency divider circuit used in the above embodiment, FIG. 5 is a block diagram showing an example of the N frequency divider circuit used in the above embodiment, and FIG. 6 is a block diagram showing an example of the N frequency divider circuit used in the above embodiment. Timing chart showing each operation of the loop filter, variable frequency divider circuit, and N frequency divider circuit, No. 7
FIG. 8 is a block diagram showing an example of the configuration of an analog PLL circuit according to another embodiment of the invention, and FIG. 8 is a block diagram showing another example of the configuration of the analog PLL circuit according to another embodiment of the invention. DESCRIPTION OF SYMBOLS 1... Input phase, 2... Phase comparator, 3... Loop filter, 4... Phase control circuit, 5... Variable frequency divider circuit, 6... N frequency divider circuit, 7...・Rising differential circuit,
8... Reset signal, 9... Timer, 10... Output phase, 11... AND gate circuit, 12... AND gate circuit. 13... OR gate circuit, 71... Input phase, 72
... Phase comparator, 73 ... Low pass filter, 74
... Phase control circuit, 75 ... VCXO (voltage controlled crystal oscillator circuit) 76 ... N frequency division circuit, 77 ... Rise differentiation circuit. 78...AND gate circuit, 80...Output phase, 8
1 sample hold circuit, 82...sample hold control circuit.

Claims (1)

[Claims] 1. A phase comparator that outputs a phase difference signal proportional to the phase difference between the input signal and the output signal, an integrator that integrates the output of the phase comparator, and an output based on the output of the integrator. In a PLL circuit that has a phase control circuit that controls the phase of a signal, when the phase difference between the input signal and the output signal exceeds a certain range, the phase of the output signal of the phase control circuit is forcibly adjusted to the phase of the input signal. 1. A PLL circuit characterized in that it is provided with a phase matching means for adjusting the phase. 2. A phase comparator that outputs a phase difference signal proportional to the phase difference between the input signal and the output signal, an integrator that integrates the output of the phase comparator, and the output of the integrator controls the phase of the output signal. In a PLL circuit having a phase control circuit, when the phase difference between the input signal and the output signal exceeds a certain range, or at the beginning of operation, the phase of the output signal of the phase control circuit is forced to match the phase of the input signal. A PLL circuit characterized in that a matching means is provided. 3. The PLL circuit according to claim 1 or 2, further comprising a function of stopping the operation of the integrator or a function of holding the current value when the phase difference between the output signal and the input signal exceeds a certain range. 4. A phase comparator that outputs a signal value proportional to the phase difference between the input signal and the output signal, and when the output of the phase comparator is integrated and the integrated value exceeds a certain threshold, the output signal phase is determined. a loop filter that outputs a control signal; and a phase control circuit that sets and outputs an output signal phase based on a signal obtained by variably dividing a frequency higher than the input signal using a phase control signal of the loop filter. PL consisting of
In the L circuit, there is a phase matching reference signal detection means that detects the rising or falling edge of the phase of the input signal and outputs a signal that becomes a reference for phase matching, and a phase difference between the input signal and the output signal that detects a preset range. and a phase matching means for matching the output signal phase to the input signal phase based on the phase matching reference signal when the phase matching reference signal exceeds the input signal phase.
LL circuit. 5. A phase comparator that outputs a signal value proportional to the phase difference between the input signal and the output signal, and integrates the output of the phase comparator, and when the integrated value exceeds a certain threshold, the output signal phase a loop filter that outputs a control signal; a frequency divider circuit that variably divides a high frequency input signal according to a phase control signal of the loop filter; and a phase control circuit that delays or advances the phase of the output signal. The PLL circuit consists of a phase matching reference signal detection means that detects the rising or falling edge of the input signal phase and outputs a signal as a reference for phase matching, and a phase difference between the input signal and the output signal that is set in advance. 1. A PLL circuit comprising: phase matching means for matching the phase of the output signal to the phase of the input signal based on the phase matching reference signal when the phase matching range is exceeded or at the initial stage of operation. 6. The PLL circuit according to claim 4 or 5, having a function of initializing the integral value of the loop filter when performing phase matching based on the phase matching reference signal. 7. When performing phase control by detecting the phase difference between the input signal and the output signal, integrating the phase difference, and advancing or delaying the output phase based on the integrated value, the edge of the input signal phase is When the phase difference between the input signal and the output signal exceeds a preset range, the output signal phase is forced to match the input signal phase using the edge of the detected input signal phase as a reference. PLL control method. 8. A phase comparator that outputs a signal value proportional to the phase difference between the input signal and the output signal, a low-pass filter that outputs a control voltage signal based on the output of the phase comparator, and a control voltage output from the low-pass filter. In a PLL circuit that includes a voltage-controlled oscillator circuit that oscillates at a frequency corresponding to the frequency of the input signal, and an N-divider circuit that divides the output of the voltage-controlled oscillator circuit by N to set the output signal phase, A phase matching reference signal detection means detects a rising or falling edge of a phase and outputs a signal serving as a reference for phase matching, and when the phase difference between the input signal and the output signal exceeds a preset range, the phase matching and a phase matching means for matching the output signal phase to the input signal phase based on the reference signal.
LL circuit. 9. A sample and hold circuit inserted and connected between the low-pass filter and the phase control circuit, and a sample and hold control circuit that controls the operation of the sample and hold circuit, and the sample and hold control circuit is configured to control the phase adjustment means. The claim further comprises a function of controlling a sample and hold circuit to maintain the output voltage of the low-pass filter at its current position when performing an operation of matching the output signal phase to the input signal phase based on the phase matching reference signal. Section 8
PLL circuit described. 10. A detection means for detecting an edge of the input signal phase input to the PLL circuit, a determination means for determining whether the phase difference between the input signal and the output signal exceeds a preset range, and a determination means for determining whether the phase difference between the input signal and the output signal exceeds a preset range, and When the range is exceeded,
and output phase setting means for setting the phase of the output signal in synchronization with the detected edge.