JPH0723015A - Destuff circuit - Google Patents

Abstract

PURPOSE:To suppress generation of the jitter by controlling a read-out timing of a buffer in accordance with a result of operation of an average value of every unit period of the number of stuffs, and varying length of the unit period in accordance with a stuff ratio of received data. CONSTITUTION:This circuit is provided with a buffer memory 37 for storing temporarily received data, a write address generating circuit 34 for generating a write timing into the memory 37 in accordance with destuff information inserted into the received data, and a read-out control part 50. A frequency analyzer 46 of the read-out control part 50 operates an average value of every unit period of the number of stuffs inserted into the received data, and a phase comparator 38, a low-pass filter 39, a voltage control oscillator 35 and a read- out address generating circuit 36 control a read-out timing of the data of the memory 37 in accordance with a result of this operation, and a gate pulse control circuit varies lenght of the unit period in accordance with a stuff ratio of the received data. In such a way, a variation of an oscillation frequency of the voltage controlled oscillator is mitigated, and the jitter caused by a sudden oscillation frequency variation is reduced.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention is used in digital communications. In particular, it relates to frequency synchronization or speed conversion technology for digital signals.

[0002]

2. Description of the Related Art In a digital transmission system, there is a stuff multiplex system as a system for synchronizing and transmitting digital signals of different frequencies. For example, SONET (Synchrono
us Optical Network) realizes synchronous transmission by stuff multiplexing in byte units.

A conventional device will be described with reference to FIG. FIG. 4 is a block diagram of a conventional device. A frequency and phase-synchronized signal is transmitted to the reception data line 31 and the reception clock line 32. The destuff control line 33 is transmitted with a signal indicating whether or not the stuff has been inserted by the transmitting unit. This signal is "1" when the receiving side receives the stuff information inserted in the received data at the time of stuffing at the transmitting section,
If there is no staff, it will be "0".

As the stuffing method, there are positive stuff (hereinafter referred to as P stuff) that delays a data signal by inserting dummy data into transmission data and negative stuff (hereinafter referred to as N stuff) that speeds up transmission data. The P staff control in byte units will be described as an example. In the P destuffing process for removing the stuff pulse from the digital signal generated by the P stuff control, the received data excluding the dummy data inserted by the P stuff process on the transmitting side is written in the buffer memory 37 and included in the received data. This is achieved by reading the buffer memory 37 at the correct clock frequency. In FIG. 4, when the destuff control signal is "0", the received data is sequentially transferred to the write address generation circuit 34 according to the sequential buffer memory 3
When the destuff control signal is “1”, the receive clock is continuously skipped by 8 clocks in order to delete the 1-byte dummy data inserted by one P stuff, and the dummy is written. Writing of data to the buffer memory 37 is prohibited. The voltage controlled oscillator 35 is an oscillator for generating a clock signal having an accurate frequency of received data. The read address generation circuit 36 uses the voltage controlled oscillator 35.
The read timing of the buffer memory 37 is generated based on the output clock signal of. The phase comparator 38 performs a phase comparison between the output of the write address generation circuit 34 and the output of the read address generation circuit 36 that include the 8-clock continuous missing component during P stuffing, and the low pass filter 39 detects the high frequency components. After cutting, the oscillation frequency of the voltage controlled oscillator 35 is controlled, and the oscillation frequency of the voltage controlled oscillator 35 is locked to the accurate data frequency of the received data. By this control, the write frequency to the buffer memory 37 and the read frequency become equal, so that the destuffing process in byte units is realized. Further, even if destuffing occurs continuously and the destuffing control signal becomes "1" for N consecutive times, the destuffing process can be performed by continuously missing N × 8 clocks.

[0005]

In the byte destuffing processing circuit shown in FIG. 4, in order to delete the dummy data inserted by the stuffing, a continuous missing bit is generated in the reception clock signal and the read clock Frequency control is performed based on the phase comparison between the continuous missing clock signal and the output of the voltage controlled oscillator. Therefore, the frequency of the output clock of the voltage controlled oscillator fluctuates greatly during continuous tooth loss, and the temporal fluctuation amount of the output data, that is, the jitter, increases sharply.

As a prior art, Japanese Patent Laid-Open No. 63-207229
Although there is a technique disclosed in Japanese Patent Publication, there is no idea of changing the unit period to take a moving average although it refers to a technique for calculating the average value of the number of staffs for each unit period. .

There is a technique disclosed in Japanese Unexamined Patent Publication No. 1-188127, which uses an average of the number of stuffs per unit cycle, but uses two elastic memories. Therefore, the hardware configuration becomes large.

The present invention has been made against such a background, and an object of the present invention is to provide a byte destuff receiving circuit capable of suppressing the occurrence of jitter and realizing a continuously generated destuff process.

[0009]

The present invention is directed to a buffer memory for temporarily storing received data, and a write address generation circuit for generating a write timing to the buffer memory according to destuff information inserted in the received data. And a read address generating means for generating the read timing of the data in the buffer memory with the write timing as an input.

Here, a feature of the present invention is that the read address generating means receives the destuffing information as an input and calculates an average value of the number of stuffs inserted in the received data per unit cycle. The means for controlling the read timing according to the calculation result of this means, and the means for changing the length of the unit cycle according to the stuff rate of the received data are provided.

It is preferable that the changing means includes a means for detecting a phase difference between the write timing and the read timing, and a means for controlling the unit cycle according to a detection result of the detecting means.

The means for controlling the unit cycle preferably includes means for changing the unit cycle in the range of s (second) order to ms (millisecond) order.

[0013]

According to the present invention, the average value of the number of staffs per unit cycle is calculated as a moving average, and the number of staffs is adaptively operated in response to a sudden change.

The stuff pulse inserted on the transmitting side is removed when it reaches the receiving side by prohibiting writing to the buffer memory only at the stuff pulse arrival timing.
Further, the number of stuff pulses is counted from the incoming data, and the average value for each unit cycle is calculated.

In the present invention, the read timing is generated according to the average value regardless of the stuff pulse position inserted on the transmitting side. That is, even if the stuff pulse is continuously inserted on the transmitting side, the read timings that are considered to be evenly distributed and inserted during the unit period are generated and read from the buffer memory.

As a result, the change in the oscillation frequency of the voltage controlled oscillator constituting the read timing generation means is alleviated,
Jitter associated with a sudden change in oscillation frequency is reduced.

Further, the write timing and the read timing are compared, and when the difference is large, the unit cycle is lengthened,
When this difference is small, the unit cycle is shortened. That is,
When this difference is large, the data interval is long, and the average value can be taken for a longer time. However, when this difference is small, the data interval is short, so that data slip (the write address cycle is one cycle earlier than the read address cycle,
Data loss may occur), so control is performed so as to obtain a short average value.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention. FIG. 2 is a block diagram of the frequency analyzer.

The present invention comprises a buffer memory 37 for temporarily storing received data, a write address generating circuit 34 for generating a write timing to the buffer memory 37 according to destuff information inserted in the received data, and the above-mentioned writing. The destuff circuit is provided with a read control unit 50 as a read address generating means for generating a read timing of the data of the buffer memory 37 with the input timing as an input.

Here, the feature of the present invention is that the frequency analyzer 46 of the read control unit 50 inputs the destuffing information as shown in FIG. 2 and the unit cycle of the number of stuffs inserted in the received data. A stuff counter 23 as means for calculating an average value for each, and a phase comparator 38, a low-pass filter 39, a voltage controlled oscillator 35, a read address generation circuit as means for controlling the read timing according to the calculation result of the stuff counter 23. 36 and a gate pulse control circuit 22 as means for changing the length of the unit cycle according to the stuffing rate of the received data.

The gate pulse control circuit 22 comprises means for controlling the unit cycle according to the detection result of the address phase comparison circuit 21, which is means for detecting the phase difference between the write timing and the read timing. The gate pulse control circuit 22 includes means for changing the unit period in the range of s (second) order to ms (millisecond) order.

Next, the operation of the embodiment of the present invention will be described with reference to FIG. FIG. 3 is a diagram showing received data and output data. In FIG. 3, the horizontal axis (time axis) is exaggerated for easy understanding of the description. Received data line 31
The reception data transmitted through the reception clock line 32 and the reception clock are signals that are frequency and phase synchronized.
The destuffing control signal transmitted through the destuffing control line 33 is "1" when the transmitting side receives the stuffing information inserted in the received data at the time of stuffing at the receiving side, and is "0" when there is no stuffing. Here, P-stuff control in byte units will be described as an example.

In FIG. 1, when the destuff control signal is "0", the received data is sequentially written in the buffer memory 37 according to the write address generation circuit 34, while when the destuff control signal is "1", In order to delete the 1-byte dummy data inserted by one P-stuff, the reception clock is skipped continuously for 8 clocks, and writing of the dummy data to the buffer memory 37 is prohibited, so that the buffer memory 37 The data signal is written except for the dummy data inserted in the received data when the stuff is generated.
As shown in FIG. 3A, as the received data, the pulse A,
The case where the stuff pulses S ₁ , S ₂ , and S ₃ arrive within the time T after B and C will be described as an example. The write address generation circuit 34 generates a write clock that prohibits the writing of the buffer memory 37 during the arrival of the stuff pulses S ₁ , S ₂ , and S ₃ to generate the stuff pulses S ₁ , S ₂ ,
Remove S ₃ .

On the other hand, when the read clock is generated from the buffer memory 37, the buffer memory 37 is continuously missing.
In addition to the write clock of, the output of the voltage controlled oscillator 35 controlled based on the output generated by the frequency analyzer 46 in which the missing tooth is smoothed is used. As shown in FIG. 3B, the stuff pulses S ₁ , S ₂ , S ₃ within T time
Is 3. Here, assuming that reading is performed every T time, the read address generation circuit 36 assumes that these three arrive in a distributed manner on average within T time, and generates a read clock when these are removed. To do. That is, since the frequency analyzer shown in FIG. 2 smoothes the output clock of the voltage controlled oscillator 35, smooth tooth gaps are generated and the transmission clock used when transmitting the reception data is faithfully reproduced.

In FIG. 2, registers 24 _{1 to} 24 _n-1.
Constitutes a shift register for shifting the counting result of the stuff counter 23 at the cycle of the gate pulse control signal.
Assuming that the output of the stuff counter 23 is X _n and the output of the register 24 _i is X _ni , the averaging circuit 25 first calculates Y _n = (X _n + X _n-1 + ... + X _nN ) / N to calculate per cycle T. Is calculated, and this staff amount is distributed within the cycle T. For example, the stuff amount is dispersed in the T / Y _n cycle. This output becomes the smoothing destuff control signal.

With the above configuration, the smoothed destuffing control signal based on the time averaging result is obtained and the phase comparator 38 is controlled, whereby the output signal of the voltage controlled oscillator 35 becomes a smooth clock signal. Since the read clock is generated by the read address generating circuit 36 based on the above, the jitter of the output data output from the buffer memory 37 can be suppressed as a result.

The stuff counter 23 counts the destuff control signal at the gate pulse period (T) of the gate pulse control circuit 22. The gate pulse period of the gate pulse control circuit 22 is adaptively changed by sequentially inputting the average value Y _n from a standard initial value. The gate pulse period (T) is also adaptively changed according to the comparison result of the address phase comparison circuit 21. In general, if T is long enough,
It is expected that the output jitter of the output data line 40 will be significantly suppressed, but it has a drawback that the convergence time is delayed because it takes time for learning. The fact that the convergence time is slow means that the write frequency to the buffer memory 37 and the read frequency are significantly different, and therefore data slip (for example, the write address cycle becomes one cycle earlier than the read address cycle in the buffer memory 37. , A loss of data occurs), enormous memory capacity is required. On the other hand, although it is expected that the output jitter characteristics with a small T will be somewhat deteriorated, the convergence time required for learning will be short.

Therefore, in the gate pulse control circuit 22,
Based on the output result of the address phase comparison circuit 21, when the phase difference between the write timing and the read timing is near ½ of the buffer length of the buffer memory 37, the gate pulse period T is on the order of s (seconds). When the length is made longer and there is almost no phase difference between the write address and the read address and slip is likely to occur, the gate pulse period T is adaptively changed to the ms (millisecond) order. As a result, even if the buffer length of the buffer memory 37 is short, it is possible to configure a destuff circuit that can prevent the occurrence of memory slip and can suppress output jitter.

As described above, the phase comparison clock used in the phase comparator 38 uses the relaxed tooth missing control signal which is the output of the frequency analyzer 46 to suppress the jitter generation amount due to the destuffing process in byte units. Further, the continuous destuffing process request can be dealt with by controlling the dispersed tooth missing density. In addition, the registers 24 _{1 to} 24
By smoothing the destuffing period by using _n-1 , it is possible to suppress the amount of jitter generated by the fluctuation of the stuffing period caused by wander or the like.

[0030]

As described above, according to the present invention,
It is possible to provide a destuffing circuit that can suppress the amount of jitter generated by destuffing processing in byte units with a simple circuit configuration.

Further, the gate time for counting and averaging the number of times of stuffing per time is adaptively controlled based on the phase difference between the write address and the read address of the buffer memory, so that the system can be started up or transmitted. Even if the clock frequency on the side suddenly changes and the frequency of the received data signal also suddenly changes as a result, it is possible to quickly pull in the frequency, so that the buffer memory amount used for destuffing can be designed to be small.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of an apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram of a frequency analyzer.

FIG. 3 is a diagram showing received data and output data.

FIG. 4 is a block diagram of a conventional device.

[Explanation of symbols]

21 address phase comparison circuit 22 gate pulse control circuit 23 stuff counter 24 _{1 to} 24 _n-1 register 25 averaging circuit 31 received data line 32 received clock line 33 destuffed control line 34 write address generation circuit 35 voltage controlled oscillator 36 read Address generation circuit 37 Buffer memory 38 Phase comparator 39 Low-pass filter 40 Output data line 46 Frequency analyzer 50 Read controller

Claims (3)

[Claims] 1. A buffer memory for temporarily storing received data, a write address generation circuit for generating a write timing to the buffer memory according to destuff information inserted in the received data, and the write timing as inputs. In the destuffing circuit including a read address generating means for generating a read timing of the data in the buffer memory, the read address generating means receives the destuff information as a unit of the number of stuffs inserted in the received data. It comprises means for calculating an average value for each cycle, means for controlling the read timing according to the calculation result of this means, and means for changing the length of the unit cycle according to the stuff rate of the received data. Destuff circuit characterized by that. 2. The changing means includes means (21) for detecting a phase difference between the write timing and the read timing, and means for controlling the unit cycle according to the detection result of the detecting means. The destuff circuit according to claim 1. 3. The destuff circuit according to claim 2, wherein the means for controlling the unit period includes means for changing the unit period in the range of s (second) order to ms (millisecond) order.