KR960007673B1 - Clock recovery unit - Google Patents

Abstract

The clock restoration device in an ATM (Asynchronous Transfer Mode) network includes: a buffering means 1 for asynchronously writing by a write clock WCLK and receiving a read clock RCLK as the result to read out user's information in succession; a buffer controlling means 24 for continuously monitoring a state of the buffering means 1 and adjusting a count value such that a received service clock be kept between the upper and lower thresholds; a clock generating means 21; a first counting and comparing means 22 for inputting the output of the clock generating means 21 to generate a predetermined value; a second counting and comparing means 25 for inputting the output of the buffer controlling means 24 to generate a variable virtual time stamp TS at the transmitter; a triggering means 23 for triggering the clock output of the clock generating means 21 and outputting a service reference clock; and a DPLL means 3 for fixing the phase of the service reference clock output from the triggering means 23 and feeding it back to use it as a read clock of the buffering means 1.

Description

Clock recovery unit

1A and 1B are conceptual views of the present invention.

2 is a block diagram of the present invention applied to a narrowband integrated information network (ISDN) S interface.

3 is a block diagram of the present invention.

4 is a service reference clock timing diagram restored on the receiving side.

* Explanation of symbols for main parts of the drawings

1: Receive buffer 2: Clock recovery unit

3: DPLL section 4: R connection section

21: clock generator 22, 25: counter and comparator

23: trigger circuit 24: buffer control unit

The present invention relates to a clock recovery apparatus for recovering a clock error between a transmitter and a receiver at a receiving side in order to support a fixed rate service in an asynchronous transfer mode (ATM) network using an asynchronous transfer scheme.

Conventionally proposed clock recovery methods include the following methods.

Synchronous Frequency Encoding Technique (SFET) is a method of coating the frequency difference between the network and the service clock and transmitting it in the header information. However, there is a disadvantage in that the network clock with respect to the source clock frequency must be similar.

In addition, the time stamp (TS) method has a disadvantage in that the overhead is large because the frequency of the network clock corresponding to the service clock is transmitted within the overhead using a 16-bit TS.

Synchronous Residual Time Stamp (SRTS) is a method that combines the advantages of SFET and TS and converts the service clock into the frequency of the reference clock on the network side. That's the way it is. The receiving side can extract the TS value from this received information and add the TS value corresponding to the remaining part received in the common frequency common part known in advance to obtain the same service clock as the service clock of the transmitting side. However, such a method according to the prior art cannot use the above method because the clock side cannot know the deviation of the clock when the reference clock of the network side is not provided in common, and the clock due to the loss of the cell accompanying the TS cannot be used. An error will occur.

Therefore, the present invention devised to solve the above-mentioned problems, a method of reproducing a virtual TS of the transmitting side for clock recovery at the receiving side using the state of the queue at the receiving side without using a clock synchronized between the transmission and reception. In this case, the clock error due to the loss of the cell accompanying the TS information in the prior art does not occur, and the clock is recovered only by the receiving side, so that no additional transmitting circuit is required, and the clock of the network is not synchronized. It is an object of the present invention to provide a clock recovery apparatus which enables a receiver to recover a clock by regenerating a TS according to a buffer level by using a clock having the same jitter characteristic as that of a transmitter even in the case of failure.

In order to achieve the above object, the present invention provides a clock recovery apparatus in an Asynchronous Transfer Mode (ATM) network using an asynchronous transfer method, which is written asynchronously by a write clock (WCLK) from an ATM layer. Receiving buffering means for continuously reading user information by receiving feedback of a read clock (RCLK) obtained as a final result; Buffer control means for continuously monitoring a state of the reception buffering means and adjusting a coefficient value such that a reception service clock is maintained between an upper limit level and a lower limit level; Clock generation means for generating a clock; A first coefficient and comparing means for receiving a output of the clock generating means and generating a constant value; Second coefficient and comparison means for receiving the output of the buffer control means and generating a virtual time stamp (TS) of a transmitting side which is a variable value; Triggering means for triggering a clock output of the clock generating means and outputting it as a service reference clock according to the input conditions of the first and second coefficients and the comparing means; And a DPLL means for phase-locking the service reference clock, which is the output of the triggering means, and feedbacking the phase-locked output clock to the receive buffering means for use as a read clock of the receive buffering means. Characterized in that.

Hereinafter, with reference to the accompanying drawings will be described an embodiment according to the present invention;

1A and 1B are conceptual views of the present invention.

When sending and receiving information through an ATM network, jitter occurs for cell information due to asynchronous characteristics. In addition, the synchronization with respect to the service information may be lost due to the deviation between the transmitting service clock and the receiving service clock.

In the present invention, in order to minimize the error due to the deviation between the service clock of the transmission and the service clock of the receiving side, the receiving side continuously monitors the receiving buffer to adaptively recover the clock. The implementation method uses a method of maintaining the level of the buffer between the upper limit level and the lower limit level as shown in FIG. 1B by using a phase looked loop (PLL) that compensates for the clock deviation between the clock of the transmitter and the clock of the receiver.

2 is a configuration diagram of the present invention applied to a narrowband integrated information network (ISDN) S interface, where 1 is a reception buffer, 2 is a clock recovery unit, 3 is a DPLL unit, and 4 is an R connection unit.

The reception buffer 1 is composed of FIFOs (First In First Out) to be written at the rate of the sender service clock, and is constantly read at the clock rate recovered from the receive service clock.

The clock recovery unit 2 generates a reference clock having a displacement within a certain clock error range by using the difference information of the reception buffer 1, and at this time, as the PLL operating in a range where the input frequency is extremely small is used Use high-frequency oscillators, so use fast response gates. For example, it may be configured as an emitter coupled logic (ECL) gate.

The DPLL unit 3 uses a commercially available VLSI chip MT8940 (Mitel), and the MT8940 outputs a phase locked 8KHz output to the input when the input clock varies within a range of 1.04 Hz or less. And outputs a 2.048 MHz or 1.544 MHz system clock for the R connection 4.

Therefore, the system clock uses 8KHz obtained by dividing (N = 8000) by using an oscillator (approximately 64 MHz) with a sufficiently high clock frequency so that the input clock varies within a range of 1.04 Hz. By dividing N + 1 (8001) or N-1 (7999) accordingly, the input frequency is changed every 8KHz so that the buffer level is maintained at a constant level.

The R connection unit 4 is composed of a chip that handles the S interface of the NISDN, and the basic speed service is composed of ISAC-S (Siemens, Inc.), which is a commercially large scale integrated circuit (VLSI). In the case of primary group speed services, IPAT and ACFA (Siemens).

When configured as described in the present invention, a frame clock of 8 KHz and a data clock of 2.048 MHz are locked within the error range set out in the International Telegraph and Telephone Advisory Committee (CCITT) G.702 (or G.703). The R connection unit 4 which restores and processes the S interface maintains synchronization with the terminal side by using the restored clock as a master clock for the terminal side.

3 is a block diagram of a clock recovery apparatus of a receiver, 24 is a buffer controller, 21 is a clock generator, 22 is a counter and a comparator A, 25 is a counter and a comparator B, and 23 is a trigger circuit.

The receive buffer 1 is composed of a commercial FIFO buffer and is written asynchronously by a write clock (WCLK) from the ATM layer, and the user is read by the resulting read (receive) clock (RCLK). The information is read continuously. In addition, the status of the buffer must be continuously monitored while having the upper and lower level of the buffer.

This upper and lower level of the buffer is important information for recovering the receiving clock. That is, the receiving side adjusts the receiving service clock so that the level of the buffer can be maintained between the upper limit and the lower limit. The portion that performs this function is the buffer control unit 24, which adjusts the counter value so that the clock speed is increased when the buffer is at the upper limit level and the clock speed is reduced when the buffer level is at the lower limit level. Thus, the buffer controller 24 may be composed of a counter and a comparator.

The portion that actually generates the reference clock from the buffer level is the gate circuit, and the circuit that generates the service reference clock.

The gate circuit consists of two counters and comparators 22 and 25 and a trigger circuit 23. The two counters and comparators 22 and 25 and the trigger circuit 23 are clock generators 21. Use clock as input.

The counter and comparator A 22 keeps the counter value constant, and the counter and comparator B 25 is a circuit having a variable value by the buffer controller 24, that is, generating a virtual TS on the transmitting side. By design, a set of trigger circuits 23 and a clear input are respectively obtained.

At this time, the trigger circuit 23 is configured as a flip-flop circuit to serve to trigger by the input clock according to the two input conditions. This gate circuit is high whenever the comparison between counter and comparator B 25 is the same, that is, when the comparison between counter A and comparator A is the same, and low when the comparison between counter B and comparator B is the same. Toggle the output to a state to generate the next one clock by using it as the input reference clock of the PLL and using the output from it as an input to reset counter and comparator A 22 and counter and comparator B 25, respectively. . At this time, the clock of the transmitting side can be restored by feedbacking the output clock which is phase locked to the input and using it as a read clock of the reception buffer 1.

In FIG. 4, the input clock of the PLL produced by the buffer level which produces the virtual TS by the service clock is shown.

As shown in the figure, reference numeral 31 denotes a clock source having an error within a certain error range on the transmission and reception side, and reference numeral 32 denotes a clock divided by N fx of the clock source 31. Reference numeral 33 denotes an f _{N + 1} clock obtained by dividing fx by N + 1, and reference numeral 34 denotes an f _N-1 clock obtained by dividing fx by N + 1. Similarly, depending on the buffer level, it can be finely divided into various levels. However, since the service clock between the transmission and reception may have some deviations, the level of these deviations should not exceed the range in which the PLL can be locked. In this way, by adjusting the input of the PLL to vary the input clock within the tolerance, an output locked to the input can be obtained through the PLL.

Therefore, the present invention constructed and operated as described above does not have a large clock error due to the loss of the cell with TS information in the conventional scheme, and the clock is recovered only by the receiving side. Since it is not necessary, the configuration is simplified, and even when the clock of the network is not supplied, the clock can be restored according to the buffer level by using the clock having the same phase as the transmitting side at the receiving side.

Claims (1)

In a clock recovery apparatus in an Asynchronous Transfer Mode (ATM) network using an asynchronous transfer method, a read clock (RCLK: read) that is asynchronously written by a write clock (WCLK) from an ATM layer and is obtained as a final result. reception buffering means (1) for receiving a feedback) and reading user information continuously; Buffer control means (24) for continuously monitoring the state of said reception buffering means (1) and adjusting a coefficient value such that a received service clock is maintained between an upper limit level and a lower limit level; Generating means 21 for generating a clock; A first coefficient and comparing means (22) for receiving a output of the clock generating means (21) and generating a constant value; Second coefficient and comparison means (25) for receiving the output of the buffer control means (24) and generating a virtual time stamp (TS) of a transmitting side which is a variable value; Triggering means (23) for triggering the clock output of the clock generating means (21) according to the input conditions of the first and second coefficients and the comparison means (22, 25) and outputting it as a service reference clock; And phase-lock the service reference clock, which is the output of the triggering means 23, and feed back the output-locked phase-locked clock to the reception buffering means 1 to read the reception buffering means 1. And a DPLL means (3) for use as a clock.