JP2630058B2 - Destuff circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[Industrial applications]

The present invention relates to a digital communication system, and more particularly, to a destuff circuit for decoding a received signal stuffed on a receiving side into an original signal.

[Prior art]

In a conventional destuff circuit, the input data signal is converted into an original signal in the order of the input data signal. FIG. 3 shows a conventional destuff circuit. The input data signal 1 is supplied to the memory circuit 6. It is assumed that the memory capacity of the memory circuit 6 is N bits. The missing clock 2 indicating only the position of the information bit is supplied to the N frequency dividing circuit 7. N
The frequency dividing circuit 7 divides the frequency of the missing clock 2 by N to generate a clock divided by N. The read clock of the memory circuit 6 is generated by an N frequency dividing circuit 8 that divides the output clock 4 generated by the voltage controlled oscillator 10 by N. A phase comparator 9 compares the phase of the N-divided clock output from the N divider 7 with the N-divided clock output from the N divider 8, and outputs a control signal to the voltage-controlled oscillator 10. , The output clock 4 is synchronized with the missing clock 2. Here, the N frequency dividing circuits 7 and 8, the phase comparing circuit 9, and the voltage controlled oscillator 10 constitute a phase locked loop (PLL) circuit. Referring to FIG. 2 (a), an input data signal 1 is a signal in which one frame is composed of 720 bits, and 3 bits in one frame.
A part and a surplus bit (OH bit) are inserted.

[Problems to be solved by the invention]

If only the information bits are extracted in this state, the amount of the OH bits is too large, and the phase comparison circuit 9 cannot sufficiently suppress the fluctuation. Therefore, output jitter appears in the output data signal. In addition, in order to suppress the amount of jitter, a voltage-controlled oscillator 10
If a sufficiently low-pass filter is inserted before the above, there is a disadvantage that the frequency pull-in range becomes narrow. An object of the present invention is to provide a destuff circuit that reduces output jitter and has a wide pull-in frequency range.

[Means for Solving the Problems]

A destuffing circuit according to the present invention receives an N-bit (N ≧ M) input data signal obtained by adding M extra bits to one frame, temporarily stores the input data signal in a memory circuit, A destuffer circuit for reading an output data signal from the memory circuit in response to an output clock generated from the memory circuit and obtaining an output data signal extracted from the surplus bits from the input data signal, wherein the surplus bit is 1 A missing clock generating circuit for generating a missing clock signal that is equal to a frame, supplying the missing clock signal to the phase locked loop circuit, and destuffing using only one of the memory circuits. Is performed.

【Example】

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a destuff circuit according to one embodiment of the present invention. The input data signal 1 is supplied to the memory circuit 6. The write clock signal used at this time is generated by the N frequency dividing circuit 7 to which the input missing clock 2 is supplied.
Here, the missing input clock 2 is a clock in which the OH bit is omitted from one frame (720 bits) shown in FIG. 2A. Reading of the output data signal 3 from the memory circuit 6
This is performed by the output clock 4 generated by the voltage controlled oscillator 10 and the N-divided clock generated by the N-divider circuit 8. The control of the voltage controlled oscillator 10 is performed as follows. The clock signal 5 is supplied to the missing clock generation circuit 11. The toothless clock generation circuit 11 generates a toothless clock signal generated so that the toothless position becomes uniform.
Here, the missing clock signal is a signal in which the dispersed OH bits are missing, as shown in FIG. 2 (b). The missing clock signal is supplied to the N frequency dividing circuit 12,
The frequency dividing circuit 12 frequency-divides the missing clock signal by N and outputs a signal obtained by dividing the frequency by N. The phase-comparison circuit 9 is supplied with the N-divided signal from the N-divider circuit 12 and the N-divided signal from the N-divider circuit 8. The phase comparison circuit 9 compares these N-divided signals and supplies a control signal to the voltage controlled oscillator 10. That is, the missing clock signal generated separately from the input missing clock 2 by equalizing the OH bits from the clock signal 5 is used. As the input data signal 1, a signal as shown in FIG. At this time, since there is a missing portion of a maximum of 51 bits, if the phase comparison is performed by the phase comparing circuit 9 using the missing input clock 2, the control of the voltage controlled oscillator 10 becomes uneven, so that a jitter occurs in the output. In the present embodiment, as shown in FIG. 2B, by equalizing the OH bits, the control of the voltage controlled oscillator 10 becomes constant, and the output jitter can be reduced. Further, since it is not necessary to insert a sufficiently low-pass filter in front of the voltage controlled oscillator 10, the frequency pull-in range is wide.

【The invention's effect】

As described above, the present invention generates a missing clock signal in which surplus bits are evenly leveled separately from the input missing clock supplied to the memory circuit, and supplies the missing clock signal to the PLL circuit. Therefore, the output jitter can be reduced and the frequency pull-in range is wide. Further, in order to perform destuffing on an N-bit (N ≧ M) input data signal in which M bits are added to one frame, destuffing is performed in one stage using only one memory circuit. Since the process is performed, there is an advantage that the processing speed is high and the circuit configuration is simple.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a destuff circuit according to one embodiment of the present invention, FIG.
FIG. 3 is a block diagram showing a conventional destuff circuit. 1 ... input data signal, 2 ... input missing clock, 3
... output data signal, 4 ... output clock, 5 ... clock signal, 6 ... memory circuit, 7 ... N frequency dividing circuit, 8 ...
... N frequency divider circuit, 9 phase comparison circuit, 10 voltage controlled oscillator, 11 missing clock generation circuit, 12 frequency divider circuit.

Claims (1)

(57) [Claims] 1. An N-bit (N.gtoreq.M) input data signal obtained by adding an M-bit surplus bit to one frame, temporarily storing the input data signal in a memory circuit, and generating the input data signal from a phase locked loop circuit. An output data signal is read from the memory circuit in response to the output clock, and the destuff circuit obtains an output data signal obtained by extracting the surplus bits from the input data signal. Having a missing clock generating circuit for generating a missing clock signal such that the missing clock signal is supplied to the phase locked loop circuit, and destuffing is performed using only one of the memory circuits. A destuff circuit.