JPH0345958B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a sampling clock regeneration method for an image encoding device, and in particular, when receiving a digital television signal, the sampling clock on the transmitting side is This invention relates to a method that enables faithful reproduction even when jitter is present.

[Prior art and its problems]

When transmitting TV images, they are transmitted according to the transmission line clock. At this time, when the TV image is digitized and transmitted, this TV signal is sampled using a sampling clock and then transmitted, but it is also necessary to sample this digital signal on the receiving side using exactly the same sampling clock. Therefore, when transmitting this digitized signal, sampling clock data is multiplexed with this encoded data and transmitted. The receiving side reproduces the sampling clock based on the transmitted sampling clock data.

Here, the sampling clock data indicates the number of transmission clocks in one frame period.

In other words, the transmission line clock of 32.064MHz is N=
The frequency is divided by N by 3583152 to make one frame, and the number of 8.949MHz sampling clocks during this period is sent out as data. The reason why the number of sampling clocks is transmitted in this way is that the sampling clock created by a crystal oscillator also has a slight amount of jitter. This is to match the In this case, the number of sampling clock counters in one frame period is expressed by the following equation if there is no jitter.

3583152×1/32.064×10 ⁴ ×8.949×10 ⁶ ≒ 1000050 … This “1000050” is expressed in hexadecimal as “F4272”
However, since the upper bits hardly change, only the lower 8 bits "72" are multiplexed with the encoded data and transmitted for transmission efficiency.
And if there is jitter in the sampling clock,
Since it can be covered by the lower 8 bits, the sampling clock can be regenerated by controlling the VCXO (voltage controlled oscillator) on the receiving side based on this count value.

However, when the oscillation frequency of the VCXO changes significantly and the counted number of clocks on the transmission path overflows or underflows 8 bits, such as when the power is turned on, a frequency other than the specified one may occur.
The drawback is that the VCXO locks up. In other words, as shown in Figure 1, when the counter on the receiving side is locked with "F4272", the counter on the receiving side is locked with "F4272".
The VCXO also oscillates at a predetermined frequency of ₀ = 8.949MHz, but when the operation is unstable, such as when the power is turned on or when there is a large transmission line error, the VCXO is locked with the upper value set to "F43" or "F41". In these cases, it is the same as if the counter on the receiving side was locked with "F4372" or "F4172", and as a result, the VCXO oscillation frequency becomes ₁ greater than ₀ or ₂ smaller.
The reproduced sampling clock will be different from the sampling clock on the transmitting side, and as a result, there is a problem that the image cannot be received accurately.

[Purpose of the invention]

As mentioned above, the purpose of the present invention is to
In order to improve the problem that the VCXO may be locked at a frequency other than the specified frequency, the VCXO It is an object of the present invention to provide a sampling clock recovery method that prevents the oscillation frequency of a clock from being locked in an undesired oscillation state.

[Structure of the invention]

To achieve this objective, the sampling clock regeneration method of the present invention encodes and transmits image data, and when receiving and reproducing it, data of the lower multiple bits of the number of sampling clocks for one frame is encoded and transmitted. In a circuit that regenerates a sampling clock by controlling a voltage-controlled oscillator based on the transmission, a voltage-controlled oscillator 10 that regenerates the sampling clock and a clock regenerated by the voltage-controlled oscillator 10 within one frame are used. Counter 11 that counts the number of clocks
and a difference detection means 30 for detecting the difference between corresponding digits between the lower bits of the received sampling clock number and the clock number counted by the counter 11, and an output of the difference detection means 30. A level detecting means 8 is provided for detecting the level, and the output level of the difference detecting means 30 falls within a range that generates a difference of at least the same number of bits as the lower plurality of bits of the number of sampling clocks transmitted by the counter 11. When
The present invention is characterized in that the output from the level detecting means 8 is fixed at a predetermined value and the voltage controlled oscillator 10 is controlled so as to obtain the center frequency of the sampling clock.

[Embodiments of the invention]

An embodiment of the present invention will be described based on FIGS. 2 to 4.

FIG. 2 is a schematic block diagram of the present invention, FIG. 3 is an explanatory diagram of the operation of the present invention, and FIG. 4 is an example of a specific block diagram of the present invention.

1 is a frequency divider circuit that divides the 32.064 MHz transmission line clock by N=3583152; 2 is a counter that counts the number of sampling clocks and outputs the lower 8 bits; 3 is a flip-flop (hereinafter referred to as FF), and 4 is a multiplex circuit, which is reset by the 8-bit output of FF3 indicating the number of sampling clocks and TV.
It multiplexes and outputs encoded image data to a transmission path. 5 is a separation circuit which outputs decoded data from the transmission signal to the image signal, a transmission line clock, and data ΔS regarding the number of 8-bit sampling clocks; 6 is a subtracter; 7 is an integration circuit;
30 is a difference detection section consisting of a subtracter 6 and an integrating circuit 7; 8 is a level detection circuit; 9 is a D/A converter; 10 is a VCXO; 11 is a counter; and 12 is a frequency dividing circuit.

As mentioned above, the frequency dividing circuit 1 divides the frequency of the 32.064 MHz transmission line clock by 1/N and outputs a signal for each video frame, and N=3583152 is selected.

Counter 2 counts the 8.949MHz sampling clock and is reset by the signal transmitted from frequency divider circuit 1 for each video frame, so counter 2 ultimately counts the sampling clock between 1 video frame. It is something to do. In this case, if there is no jitter in the sampling clock, 1000050 times, ie, "F4272" in hexadecimal notation, will be counted between the video frame signals output from the frequency dividing circuit 1 as shown in the above formula. And among these, the lower 8 bits “72” are FF3
However, the above 1 is output from frequency divider circuit 1 to FF3.
A signal for each video frame is transmitted, and the 8-bit output of counter 2 is thereby set to FF3. The lower 8-bit signal .DELTA.S of the sampling clock number thus set in FF3 is transmitted to the multiplexing circuit 4, multiplexed with the image encoded data, and transmitted to the transmission line.

The receiving side receives this transmitted signal and separates the transmission line clock, decoded data, and lower 8-bit signal ΔS of the number of sampling clocks by a separation circuit 5. Of these, the transmission line clock is transmitted to the 1/N frequency dividing circuit 12 to output a video frame signal in the same way as on the transmitting side, and the above ΔS is transmitted to the difference detecting section 30.
The frequency difference between the transmitting clock and the receiving clock is calculated and cumulatively added by the integrating circuit 7.

The level detection circuit 8 outputs data that causes the output value of the difference detection unit 30 to oscillate at a frequency that does not cause the counter 11 to overflow or underflow.
When the value is within the range given to the A converter 9, a corresponding digital value is output, but the counter 11
When becomes a large value that overflows or underflows, all 0s are set.
The output voltage of the D/A converter 9 is set to zero, and the oscillation frequency of the VCXO 10 is set to 8.949MHz, which is the same as the sampling clock, so that the count value of the counter 11 during one video frame becomes "F4272". This is for forcibly controlling the VCXO10.

Therefore, when the oscillation frequency of the VCXO 10 is almost the same as the sampling clock, when there is jitter in the sampling clock on the transmitting side, the lower 8-bit output ΔS of the counter 2 on the transmitting side is extracted by the separation circuit 5. This ΔS is transmitted to the subtracter 6, and the difference between it and the output value of the counter 11 is output to the integrating circuit 7. When the output of the integrating circuit 7 is detected by the level detecting circuit 8 and has a value that does not cause the counter 11 to overflow or underflow, the output of the integrating circuit 7 is directly input to the D/A. It is output to the converter and converted into an analog value to control the oscillation frequency of the VCXO10. As a result, the output of the counter 11 changes and when the next video frame is received, if ΔS is the same as before, the output value of the subtracter 6 decreases, and the output of the D/A converter also decreases.
Controls VCXO10. By repeating this process, the VCXO 10 outputs the same oscillation frequency as the sampling clock with jitter on the transmitting side.

However, when the operation is unstable, such as when the power is turned on or when a transmission line abnormality occurs, the output of the subtracter 6 of the difference between the output value of the counter 11 that counts the oscillation frequency of the VCXO 10 and the output ΔS of the separation circuit 5 becomes extremely large. The output value of the integrating circuit 7 becomes such a large value that the counter 11 overflows or underflows. Therefore, the level detection circuit 8 detects this state and outputs all "0" to the D/A converter 9. Based on this, the output of the D/A converter 9 forces the VCXO 10 to oscillate at a frequency at which the count value becomes "F4272" during the video frame period, that is, 8.949MHz.

That is, in the present invention, when the output of the integrating circuit 7 reaches a value that causes the counter 11 to overflow or underflow, in other words, when the output of the integrating circuit 7 reaches a value that is greater than or equal to _C2 or less than or equal to _C1 in FIG. The VCXO 10 is forcibly controlled so that its oscillation frequency counts "F4272" during one video frame. Therefore, as in the conventional system shown in Figure 1, when the operation is unstable, the receiving side
There is no drawback that the VCXO is locked to ₁ or ₂ ; in such a case, the VCXO oscillation frequency will be forced to ₀ .

The receiving side PLO (Phase Lock Oscillator) in Fig. 2 is, for example, FF2 as shown in Fig. 4.
1 and 22, and an adder 20 is used as the integrating circuit 7. The FF 21 is set according to the output of the adder 20, and its state is monitored by the level detection circuit 8. When the FF 21 reaches a state where the counter 11 overflows or underflows, the level detection circuit 8 sets the FF 2.
1 is cleared and the D/A converter 9 is made to send out all "0". As a result, the D/A converter 9 controls the oscillation frequency of the VCXO 10 to be forcibly shifted to the center frequency, and the PLO
will be locked to this center frequency in a short time.

However, during normal operation, the output of FF21 is
Since it is between C ₁ and _{C 2} in the figure, the VCXO 10 operates near the center frequency, so the counter 11 will not overflow or underflow.

In the above explanation, an example was explained in which the counter outputs the lower 8 bits, but the present invention is of course not limited to this.

〔Effect of the invention〕

In the present invention, since the oscillation frequency of the VCXO is controlled to be shifted to the center frequency during unstable operation, the counter will not overflow or underflow, so the VCXO will not malfunction and cause an undesired oscillation state. There's no way you'll get locked out.

[Brief explanation of drawings]

FIG. 1 is a diagram illustrating problems in the conventional technology, FIG. 2 is a schematic diagram of the configuration of the present invention, FIG. 3 is a diagram illustrating the operation of the present invention, and FIG. 4 is an example of a specific example of the present invention. In the figure, 1 is a frequency dividing circuit, 2 is a counter, 3 is an FF,
4 is a multiplex circuit, 5 is a separation circuit, 6 is a subtracter, 7 is an integration circuit, 30 is a difference detection section, 8 is a level detection circuit, 9 is a D/A converter, 10 is a VCXO, 1
1 is a counter, and 12 is a frequency dividing circuit.

Claims (1)

[Claims] 1. When image data is encoded and transmitted, received and reproduced, the data of the lower multiple bits of the number of sampling clocks for one frame is transmitted, and the voltage controlled oscillator is controlled based on this data. In the circuit for regenerating the sampling clock, a voltage controlled oscillator 10 for regenerating the sampling clock.
, a counter 11 that counts the number of clocks within one frame from the clock regenerated by the voltage controlled oscillator 10, and a plurality of lower bits of the received sampling clock number and the number of clocks counted by the counter 11. A difference detection means 30 for detecting the difference between corresponding digits and a level detection means 8 for detecting the output level of the difference detection means 30 are provided, and the output level of the difference detection means 30 is transmitted by the counter 11. When the difference is greater than the same number of bits as the lower plurality of bits of the number of sampling clocks that have been sampled, the output from the level detection means 8 is fixed at a predetermined value, and the voltage controlled oscillator is 1. A sampling clock regeneration method characterized in that the sampling clock is controlled such that the center frequency of the sampling clock is obtained.