JP3508049B2 - Transmission line clock recovery circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission path clock recovery circuit, and more particularly to a method of recovering a transmission path clock on the receiving side of a data transmission device in an asynchronous network.

[0002]

2. Description of the Related Art Conventionally, in a television encoding / transmission apparatus for sampling and encoding and transmitting a television signal, it is necessary to reproduce a sampling clock in order to reproduce an image signal on the receiving side. The method of reproducing the sampling clock is to synchronize the transmission path clock with the sampling clock, or to transmit the relative frequency information between the transmission path clock and the sampling clock,
There is a method of reproducing on the basis of this on the receiving side.

When the transmission path clock is synchronized with the sampling clock, the transmission path clock FL and the sampling clock F
When synchronized with the proportional relationship with S [FL = N / M × FS], a phase comparison is made between the signal obtained by dividing the transmission path clock FL by N and the signal obtained by dividing the sampling clock FS by M on the receiving side. ,
A VCXO (voltage-con
trolled crystal oscilato
r: voltage controlled oscillator) to control [FS = N / M × F
L] to recover the sampling clock.

When transmitting the relative frequency information Ns,
JP-A-54-51305 and JP-A-63-2344
As disclosed in Japanese Patent Laid-Open No. 54-54, the frequency ratio of the frequency counts of the sampling clock FS and the transmission path clock FL is obtained as the relative frequency information Ns and transmitted to the receiving side at regular intervals.

For example, the clock count number of the sampling clock FS for each cycle of 1 / N of the transmission path clock FL is sent as relative frequency information Ns. Also on the receiving side, as relative frequency information between the reproduction sampling clock and the transmission path clock FL,
The count number of the reproduction sampling clock is obtained as the relative frequency information Nr on the receiving side every 1 / N cycle of the transmission path clock FL.

Difference signal Δ = Ns of these relative frequency information
The value of -Nr is obtained, and the transmission frequency of the VCXO for the regenerated sampling clock on the receiving side is controlled by this value. Difference signal Δ
Is D / A (digital / analog) converted through a digital filter and VC is used as an analog control voltage signal.
The oscillation frequency is controlled by being applied to the XO, and the relative frequency information Nr on the receiving side changes accordingly, and by this series of feedback control, the differential signal will eventually converge to a point where it becomes 0. Then, the frequencies of the sampling clock on the transmitting side and the regenerated sampling clock match.

Here, 150M (155.52Mbp)
The signal coded in s) is NN at an asynchronous frequency on the way.
In the case of being multiplexed and sent to a 600M network transmission line of I (network / network interface), separated from 600M to 150M before the receiving side and transmitted, and supplied to a decoding device to decode an image signal,
It will be processed by each circuit shown in FIGS.

FIG. 8 shows the configuration of an apparatus for encoding and transmitting an image signal at 150 M. The apparatus is an A / D (analog / digital) converter 71 and a multiplexing circuit 72.
The sampling clock generating circuit (FS) 73, the counter 74, the 1 / N frequency dividing circuit 75, and the transmission path clock generating circuit (FLs) 76.

FIG. 9 shows a 600M network transmission structure in which 150M is asynchronously multiplexed and transmitted on a 600M network transmission line, separated on the receiving side and returned to 150M. The network transmission device is an NNI network. A transmission multiplexer (600M-T) 81,
NNI network transmission / separation device (600M-R) 82, and NNI
And a network transmission line clock generation circuit (FLn) 83.

FIG. 10 shows the configuration of an image receiving apparatus, in which the transmission side transmission path clock is reproduced from the network transmission path clock. In the figure, this receiving apparatus comprises a stuff separation circuit 91, a buffer memory 92, a network transmission line clock recovery circuit (FLn reproduction) 93, and a transmission line clock recovery circuit (FLs reproduction) 94.

FIG. 11 shows the structure of a decoding device which reproduces the image signal by reproducing the sampling clock by obtaining the frequency information. The decoding device is a separation circuit 101 and a D / A.
It is composed of a (digital / analog) converter 102 and a sampling clock (FS) regenerating circuit 110. Here, the sampling clock (FS) reproduction circuit 110 includes a subtractor 103, a digital filter 104, a D / A conversion circuit 105, and a transmission path clock distribution circuit (FLs) 106.
, 1 / N frequency dividing circuit 107, counter 108, VC
XO109 and.

When a transmission signal of 150 M is transferred to an NNI transmission line clock at an asynchronous frequency in the middle of the transmission line network by the NNI network transmission multiplexer 81 shown in FIG. 9, the clock frequency of the transmission side 150 M is changed. 8K because the clock frequency of 150M on the NNI and the transmission line of NNI is different.
Since the number of data for each frame does not match and gradually shifts, excess and shortage data is adjusted by stuff multiplexing.

The 8K frame is composed of a control area (overhead: OH) and a data area, and an area for handling stuff multiplex is provided in the control area (overhead area).

Since the receiving side can extract valid data by looking at the staff information, the data on the transmitting side is correctly sent to the receiving side. However, when transmission is performed with the asynchronous 150 M transmission line clock FLs, the transmission line clock via NNI is DC.
Since the transmission line clock FLn is synchronized with the network reference frequency such as S (Digital Clock Supply), the transmission line clock reproduced by the decoding device on the receiving side also becomes the transmission line clock FLn, and the transmission line clock FLs on the transmitting side. Have different frequencies. Therefore, the sampling clock of the image cannot be reproduced as it is by using the method of the relative frequency information described above.

Therefore, it is necessary for the receiving side to regenerate the transmission line clock FLs having the same frequency as the transmitting side. In this case, since it can be seen that the data is added or subtracted by the stuff information, the transmission side transmission line clock is regenerated using the stuff information.

When the image signal is encoded and transmitted at 155.52 M, the encoded data is transmitted by multiplexing the data in an 8 K transmission frame. 270x9 for 8K frame
The control signal part (overhead: OH) is 9 × 9, and the data part (payload) is 261 × 9, which is composed of blocks (2430). 29/30 (about 97%) will be used for data transmission.

In other words, one data corresponds to 30/29 clocks of the transmission line clock. When the transmission-side transmission line clock and the transmission-line network clock are asynchronous, the number of data will be excessive or insufficient depending on the frequency shift during NNI multiplexing. Staff multiplexing is performed by writing in the information area and the staff data area.

The NNI multiplexing stuff section has a buffer memory on the input side in order to adjust data fluctuations.
The stuffing is not performed periodically according to the frequency shift, but is performed according to the storage amount of the buffer memory.

Therefore, the relative position of the overhead of both the input side (transmission side) 8K frame and the multiplexing side (reception side) 8K frame is determined by the transmission path clock FLs of the transmitter.
And the NNI 150M transmission line clock FLn shifts at a speed corresponding to the magnitude of the difference in frequency.

Since the stuffing process cannot be performed when the network side of the NNI corresponds to the overhead, the accumulated amount in the buffer memory changes greatly before and after this, and the fluctuation period of the stuff amount depends on the relative shift period of the overhead. Will have a large jitter.

On the receiving side, VCX is performed according to the stuffing.
The frequency of O is controlled to regenerate the transmission path clock on the transmission side. When there is no stuffing, it matches the transmission line clock on the receiving side. If there is a positive stuff of +1 data, extra data is sent, so the VCXO is controlled so that the frequency of the reproduction transmission line clock increases by 30/29 clocks in a cycle of 8K. When there is a negative stuff of −1 data, the VCXO is controlled so that the frequency of the reproduction transmission line clock is lowered by 30/29 clocks in the cycle of 8K.

In actual NNI stuffing multiplexing, 3 words, that is, 24 bits are stuffed once, so one correction in 8K cycles can be controlled by VCXO by the number of ± 24 × 30/29 clocks. Will be needed. When it corresponds to the overhead portion, stuffing cannot be performed for a period of 9 words, so a total of 12 words appear as the amount of change in stuff jitter.

In the receiving side block shown in FIG. 10, the transmission line clock FLn is regenerated from the received optical transmission line signal.
The stuff separation circuit 91 separates the stuff information and the stuff data, and the stuff data is combined with the transmission data as write data and sent to the buffer memory 92 together with the write clock. The transmission path clock recovery circuit 94 reproduces a stable transmission path clock FLs on the transmission side from the stuff information sent from the stuff separation circuit 91 and the transmission path clock FLn of the network transmission path clock recovery circuit 93. Data is read from the buffer memory 92 by the reproduced transmission line clock FLs. The transmission path clock recovery circuit 94 has the same configuration as the sampling clock recovery circuit 110 of the reception block shown in FIG.

When configuring a VCXO, 155.54M
Has a high frequency, so a divided value, for example, 1/8 of 1
9.44M is generated as a word clock. The variation of the stuff information in the case of the word clock appears as a variation of 12 words in the number of clocks in each cycle, that is, as jitter, so this large jitter absorption is fully taken into consideration, and the pull-in time, stability, and temperature dependence The PLL (Phase Locked)
It is necessary to determine the time constant of Loop.

[0025]

In the above-mentioned conventional method for recovering the transmission path clock, the VCX is made by using the stuff information.
When controlling O, the VCXO is controlled by using the stuff information instead of the sampling frequency information by the sampling clock reproduction method using the above-mentioned relative frequency information, and the transmission path clock having the same frequency as the transmission side is reproduced. It is composed.

In this case, since the stuff information is not generated at equal intervals, the control amount generated by one stuff is large, and the stuff jitter has a long period, the control proportional to the stuff information is performed. If done, the reproduced frequency will have stuff jitter.

Therefore, since the sampling clock reproduced based on this transmission line clock also has stuff jitter, jitter appears in the reproduced image signal,
There is a problem that the quality of the reproduced image is greatly deteriorated.

With respect to the jitter period, if the shift of the frequency of the transmission path clock is 1 ppm, a long period jitter of 10 seconds or more appears, and if it is 0.1 ppm, it becomes about 10 times longer period jitter.

The amount of change in the jitter of the stuff information occurs when the data area jumps by 9 words at the overhead, and the worst is 3 words × (3+).
1) = estimated to be 12 words in size. That is, the control amount of the stuff information is normally 1 to 3 words with respect to the clock of the frequency of 19.44M, but the control value of 12 words should be generated in the short term by accumulating the stuff information in the overhead section. There is.

On the other hand, in order to reproduce the data stuffed on the receiving side and read it out with the clock, a buffer memory is required for smoothing once. The capacity of this buffer memory depends on the delay time and delay of the data. It cannot be made too large due to the time variation limitation.

In order to reproduce a highly stable transmission line clock that satisfies these restrictions, it is necessary to construct a circuit that reproduces a highly stable clock after pull-in and pull-in in a short time.

However, in the conventional clock generating circuit, the transfer characteristic of the control loop of the VCXO has a control voltage vs. oscillation frequency characteristic of the VCXO, deviation of circuit elements, temperature change and secular change, and moreover, it takes a long response time. However, the system becomes unstable even if the shortest transfer characteristic for high-speed pull-in is attempted, and therefore it is necessary to set the parameter in view of the margin, and there is a problem that the pull-in time cannot be shortened.

Further, in order to make the buffer memory small, it is necessary for the VCXO to accurately follow the control signal, but since the transfer characteristics of the control loop of the VCXO have variations, accurate control cannot be performed and variations occur. It is necessary to increase the buffer memory in consideration of the above.

Further, the frequency control requires control about once every 0.1 seconds in order to shorten the pull-in time. In this case, the error of one clock is 1 / (19.44M
X0.1) = 0.5 ppm, therefore, when the gain of the system is 1, the accuracy of frequency control of the VCXO by the differential signal of the clock becomes 0.5 ppm, and the accuracy of control becomes coarse, and Since it is unstable, it must be sufficiently smaller than 1.

If the gain is set to 1/100 in order to stabilize the system and control with high accuracy, the accuracy of 0.5 ppm / 100 = 0.005 ppm can be controlled with a difference of 1 clock. Since the correction of the error of 1 clock is corrected only 1/100 to the residual error,
Even if the precision below the decimal point is calculated correctly, 100
The number of times (10 seconds) asymptotically converges to about 0.366, and the number of times 300 converges to 0.05 asymptotically.

When there is quantization, there is a dead zone of calculation, which may make it difficult to converge. When the gain is controlled to be small, the frequency is not linearly corrected but is asymptotically corrected, which causes a problem of convergence time. Further, since it takes a long time to pull in, there is a problem that unless the buffer memory is enlarged, overflow occurs and data is lost.

Further, the VCXO has temperature dependence in the control voltage-oscillation frequency characteristic, and even if the oscillation frequency is the same,
The control voltage varies depending on the ambient temperature. Therefore, when there is a temperature change, it is necessary to make the control voltage follow the change in order to transmit a constant frequency until the temperature stabilizes.
There is a problem that the phase of the clock shifts in order to generate the control signal for the correction of this change tracking.

Therefore, the object of the present invention is to solve the above-mentioned problems, to perform the pull-in at high speed and accurately without generating the reproduction frequency and the clock phase shift due to the temperature change, and to be influenced by the noise. It is an object of the present invention to provide a transmission path clock regenerating circuit that can regenerate a transmission path clock with high accuracy and high stability.

[0039]

A transmission line clock regenerating circuit according to the present invention is a transmission line clock regenerating circuit for regenerating the same transmission line clock as a transmitting side on a receiving side of an apparatus for asynchronously transmitting a signal through a network transmission line. And a means for obtaining the number of transmission side transmission path clocks in one frame period from the information subjected to the stuff multiplex processing at the transmitting side;
Means for obtaining the number of reproduction transmission path clocks in a frame cycle, means for obtaining a difference between the number of transmission side transmission path clocks and the number of reproduction transmission path clocks, and for each transmission path clock in each basic clock cycle according to the difference. Means for correcting the value of the angular velocity, means for obtaining the phase angle by integrating the corrected angular velocity for each of the basic clock cycles, means for reproducing the transmission path clock from the phase angle, and means for generating the basic clock. Is equipped with.

That is, the transmission line clock regenerating circuit of the present invention has means for obtaining frequency information NLs of the transmission side transmission line clock from the stuff information, and 1 / N of the NNI transmission line clock.
A means for obtaining the frequency information NLr of the regenerated clock by counting the regenerated transmission path clock in the cycle T of N, a means for obtaining the difference signal Δ between the frequency information NLs on the transmission side and the frequency information NLr on the reception side, and a basic cycle from the difference signal. Means for obtaining the angular velocity of the transmission path clock for each, a means for adding the angular velocity of the transmission path clock for each basic clock period to obtain a phase angle, a means for reproducing the transmission side clock from the phase angle, and a transmission side transmission Means for obtaining frequency information NLr on the receiving side from the line clock FLs and the NNI transmission line clock FLn.

In order to increase the accuracy, the magnitude of the angular velocity is adaptively controlled by checking the staff information of NNI.
Stabilize the reproduction clock by averaging the staff information and making the response sensitivity less sensitive to fluctuations (jitter) in the staff information, or making it hardly follow, and changing the average value of the staff information. On the other hand, control is performed to quickly respond to shorten the pull-in time.

In the transmission path clock regenerating circuit having the above-mentioned configuration, the frequency information NLs of the transmission side transmission path clock is obtained based on the stuff information. The reproduced transmission path clock is counted in a constant period (T) obtained by dividing (1 / N) the NNI transmission path clock, and reproduced clock frequency information NLr is obtained.

A signal Δ = NLs-NLr of the difference between the two.
Is obtained. Originally, the value of NLs should be counted in the count cycle T, but when the difference signal Δ is increased, the frequency of the reproduction sampling clock is Δ / NL.
Since it is lower by s, the frequency is increased based on this value, and thus the angular velocity value is increased by Δω.

The phase angle generator generates a high frequency as the angular velocity increases, and in the next counting cycle, a frequency higher by the angular velocity correction value Δω is generated as the count value of the frequency information on the receiving side, and the error Δ Angular velocity correction value Δ
Adaptively change the ratio of ω.

At the time of high-speed pull-in, the gain is corrected by almost 1. The gain is very small in the steady state. When the gain is set to 1 at the time of pulling in, the error signal is corrected to be 0 after 1 count period, and the frequency is pulled in to the frequency matching the transmitting side, and the pull-in time becomes very short.

That is, since the sample clock is obtained from the digital phase angle without using the VCXO, the frequency is accurately corrected from the error signal, and the corrected frequency is transmitted according to the corrected angular velocity for each count cycle. The road clock is regenerated.

Since the present invention is digital processing, if the stuff information is averaged and controlled with high accuracy, the reproduction frequency is correctly corrected according to the control signal value, and the generated frequency has a constant angular velocity value. Then, it is kept constant without depending on the temperature fluctuation.

That is, in the configuration of the present invention, the frequency can be accurately corrected for each control cycle. Therefore, if the gain of the feedback loop is set to 1, sampling of the frequency that is correctly corrected in the next control cycle is performed. A clock can be obtained and high-speed pull-in is possible.

Further, since the present invention is digital processing, there is no temperature dependence, there is no influence on the control system due to noise, and the control correction by the error signal can be accurately and accurately performed, and the regenerative transmission due to temperature dependence is performed. There is no phase shift of the road clock.

[0050]

BEST MODE FOR CARRYING OUT THE INVENTION Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a transmission path clock recovery circuit according to an embodiment of the present invention. In the figure, the transmission line clock recovery circuit 4 is a subtractor 4
1, an angular velocity correction circuit 42, a phase angle generation circuit 43,
It is composed of a transmission line clock generator 44, an NNI network transmission line clock generation circuit (FLn) 45, a 1 / N frequency dividing circuit 46, a counter 47, and a basic clock generator 48.

A signal transmitted by light of 155.52 Mbps is converted into an electric signal by an O / E (optical / electrical) converter 1 and a transmission line clock FL of 155.54 M is generated.
Is reproduced, the electric signal is supplied to the stuff separation circuit 2, and the transmission line clock FL is supplied to the NNI network transmission line clock generation circuit 45 and the basic clock generator 48.

In the NNI network transmission line clock generation circuit 45, the transmission line clock FL is divided into 1/8 to generate a word clock of 19.44M, and the word clock is stuffed into the stuff separation circuit 2 and the 1 / N division circuit. Supply to 46.

The 1 / N frequency dividing circuit 46 divides the word clock into 1/2430 to obtain a frame period T of 8K. In the basic clock generator 48, 155.52M is 1 /
The frequency is divided into two to generate a 77.76M basic clock, and the basic clock is supplied to the phase angle generating circuit 43.

The stuff separation circuit 2 obtains transmission side transmission line clock frequency information NLs from the stuff information in the period T and sends it to the subtractor 41. The subtracter 41 subtracts the transmission side frequency information NLs and the reproduction transmission path clock frequency information NLr at the cycle T obtained from the counter 47 to obtain an error signal Δ and supplies it to the angular velocity correction circuit 42.

The angular velocity correction circuit 42 corrects the angular velocity of the reproduction transmission path clock in the cycle of the basic clock based on the error signal Δ, and the corrected angular velocity is generated by the phase angle generation circuit 43.
Supply to. Since the basic clock is 77.76M and the transmission side transmission line clock is about 19.44M, the angular velocity is 9
The correction will be added to 0 degree. The correction of the angular velocity is performed so that the angular velocity is increased when the error signal Δ is positive and the angular velocity is decreased when the error signal Δ is negative.

The phase angle generation circuit 43 integrates the phase angle for each basic clock to obtain the phase angle of the regenerated transmission line clock signal. The transmission line clock generator 44 is a high-order 10 phase angle signal.
Bit to 10-bit PCM (Pulse Cod)
e Modulation) sine wave is obtained, 10 bits are D / A (digital / analog) converted to obtain an analog sine wave, and the waveform is shaped to obtain a rectangular wave transmission line clock.

The precision of the number of bits of the angular velocity correction circuit 42 depends on the precision of the control of the frequency of the generated clock. A precision of 0.001 ppm requires a precision of 30 bits. Unlike the case of using the VCXO, it is not affected by the noise in the surroundings. Therefore, if the accuracy is high, the control can be performed with such accuracy.

Since the transmission path clock generator 44 only needs to have the upper 10 bits of the phase angle, the phase angle generating circuit 4
In the case of 3, it is not necessary to integrate the phase angle with 30 bits, and LSB (Least Significant) of the upper 10 bits is used.
It is possible to simplify processing such as addition processing only when there is a carry in ant Bit).

As another configuration, the phase angle generation circuit 43 integrates the angular velocity ω for each reference clock to obtain the phase angle θ and outputs it. In that case, the integration is performed with an accuracy of 30 bits.
At this time, the value overflowed to the upper 30 bits is 36.
Since the value exceeds 0 degrees, it will be discarded.

The reference clock has a clock cycle of 77.76M, and a high-speed element is required to perform 30-bit integration, but it is developed into 8 phases and integration is performed with a 9.72M clock, and each integration is performed. If the value is selected at 77.76M and is switched, the integration can be configured by a normal element. Even if the minimum accuracy of correction is 0.001 ppm,
When a correction of 1 is added to the LSB of the angular velocity every 8K cycle, a frequency variation of 8 ppm occurs after 1 second.

When the accuracy of the frequency information NLs is not high, if the correction value of the angular velocity is increased in the configuration of the present invention to improve the followability, the effect of the stuff jitter is directly received, and the reproduction transmission line clock has a jitter. Occurs as it is. As a method of improving this, there is a method of increasing the accuracy of frequency information by averaging it.

FIG. 2 is a block diagram showing a configuration example of the transmission path clock generator 44 of FIG. In the figure, the transmission line clock generator 44 comprises a sine wave table 44a, a D / A converter 44b, and a rectangular wave circuit 44c.

The sine wave table 44a is a ROM (read-only memory) that generates a PCM sine wave for a 10-bit phase angle, and outputs a 10-bit sine wave signal for a 10-bit phase angle.

The D / A circuit 44b converts the PCM value into an analog sine wave signal, and the rectangular wave circuit 44c converts the sine wave signal into a rectangular wave signal to reproduce and output the transmission path clock on the transmitting side. The obtained reproduction transmission path clock is supplied to the buffer memory 3 and the circuit of the next stage.

FIG. 3 is a block diagram showing another configuration example of the transmission path clock generator 44 of FIG. In the figure, in another configuration example of the transmission path clock generator 44, a clock waveform generator 44d, a D / A converter 44b, and a tank circuit 44 are shown.
e and a rectangular wave circuit 44c.

The other configuration example described above is a method for simplifying the circuit of the transmission path clock generator 44.
4a and the number of bits of the D / A converter 44b are reduced, and the obtained sampling clock signal of rough accuracy is supplied to the tank circuit 44e or BPF (Band-Pass Fil) having a high Q.
ter) to obtain a highly accurate clock.

FIG. 4 is a block diagram showing the configuration of the clock waveform generator 44d shown in FIG. In the figure, a clock waveform generator 44d is a circuit used in place of the sine wave table 44a shown in FIG. 4, and includes a determination circuit 11 and N / 4-i.
It is composed of an arithmetic circuit 12, an N-i arithmetic circuit 13, and a switcher 14.

The accuracy of the phase angle used for the sampling clock is 3
~ 4 bits, ROM sine wave table 44a
And the clock waveform generator 44d is used. In this case, instead of finding the PCM sine wave from the phase angle,
A triangular wave of PCM value is obtained by calculation.

The n-bit signal has a signal value i of 0 to N-1.
(N = 2 to the nth power). The output signal Y of the triangular wave is determined by the decision circuit 51 from the signal value i of the upper n bits of the phase angle signal.
And output as it is depending on the range of i, N / 4-
Either the output of the i arithmetic circuit 12 or the output of the i-N arithmetic circuit 13 is selected by the switch 14 and output.

The judgment of the judgment circuit 11 is   Output of switch 14: Judgment condition of judgment circuit 11     Y = i: When i <N / 4, switching circuit input A selection     Y = N / 4-i: In the case of N / 4 <i <3N / 4,                                             Switching circuit input B selection     Y = i−N: When 3N / 4 <i <N,                                             Switching circuit input C selection Becomes

For example, in the case of n = 3, when changing from i = 0 to 7, the value of Y is 0, 1, 2, 1, 0, -1, -2,
Take a PCM value of -1,0. This triangular waveform signal can be used instead of the sine wave approximately. If it is a 3-bit signal, D / A conversion can be easily performed.

Next, the operation of the counter 47 shown in FIG. 1 will be described. Regenerated transmission line clock FL in cycle T
The number of r is counted from the phase angle, the counter 47 is free-counted, and the frequency information of the reproduced clock is obtained from the difference value for each cycle.

The upper 3 bits of the phase angle change between 000 and 111, but when it changes from 111 to 000, that is, when 360 degrees, in other words, when it exceeds 0 degrees, the counter 47 is incremented by 1 and counting is performed. .

The integer count value and the signal value of the phase angle of 3 bits after the decimal point are sampled every period T, the difference from the previous time is calculated to obtain the count value at the period T, and the frequency information of the reproduction clock is obtained. It is supplied to the subtractor 41 as NLr.

The 1 / N frequency dividing circuit 46 is a transmission line clock FL.
(155.52M) is divided by 8 × 2430 to obtain a cycle of 8K. However, since the transmission line clock does not vary much from the beginning, the cycle can be made a little longer to improve the accuracy of the control signal. Divide by 512 to about 0.064.
It is also possible to obtain a cycle T of seconds (15.6 Hz) and perform angular velocity correction control in this cycle. At this time, the frequency information needs to be a count value obtained by integrating the period.

FIG. 5 is a timing chart showing the operation of the clock recovery circuit 4 of FIG. In the figure, (a) shows the basic clock signal generated from the basic clock generator 48, (b) shows the cycle counted by the counter 47, and the cycle is the (n + 1) th, then (n + 1) th cycle.

(C) shows a correction value in the angular velocity correction circuit 42. At the switching point, the difference value Δ between the count value (reception side frequency information) in the nth cycle and the count value (transmission side frequency information) sent from the transmission side is calculated, and the calculated value is the angular velocity correction circuit 42. And the correction value Δω of the angular velocity ω is added. That is, if it is "0" in the nth counting cycle, it is "Δω" in the n + 1th counting cycle.

(D) shows the angular velocity output value of the angular velocity correction circuit 42. If the angular velocity value for each basic clock is the angular velocity ω in the nth cycle, the angular velocity is ω in the n + 1th cycle.
It becomes + Δω.

(E) shows the phase angle θ of the phase angle generating circuit 43. The phase angle generation circuit 43 integrates the angular velocity ω to calculate the phase angle θ. The phase angle θ has a triangular waveform that monotonically repeats at an angular velocity ω in each basic clock cycle from 0 degree to 360 degrees.

(F) shows the PCM value of the sine wave of the transmission line clock obtained from the phase angle θ in each sine wave table 44a of the transmission line clock generator 44 for each basic clock period.

(G) is a D / A converter 44b for the PCM signal.
Shows a sine wave signal having a transmission line clock frequency obtained by converting into an analog signal. (H) shows a transmission path clock obtained by converting a sine wave signal into a rectangular wave clock by the rectangular wave circuit 44c.

(I) indicates a clock number. The i-th clock is a clock cycle whose angular velocity is determined by ω,
The angular velocity is determined by ω + Δω in the (i + 1) th clock period in which the count period is the (n + 1) th clock period. That is, in one embodiment of the present invention, by controlling the angular velocity, the cycle of the clock, that is, the frequency can be accurately obtained immediately after the change.

FIG. 6 is a block diagram showing the structure of a transmission path clock recovery circuit according to another embodiment of the present invention. In the figure, a transmission line clock recovery circuit 5 according to another embodiment of the present invention is the same as the transmission line clock recovery circuit 4 according to an embodiment of the present invention except that an averaging circuit 51 for averaging transmission side frequency information is added. The same components are designated by the same reference numerals. The operation of the same component is the same as that of the embodiment of the present invention.

The averaging circuit 51 averages the values of the frequency information NLs over a period in which the period of jitter can be reduced, and outputs the averaged value as frequency information. If the frequency information is averaged, the frequency tracking is delayed when the transmission side frequency really changes. In that case, the value of the frequency information NLs is output as it is without performing the averaging.

When the frequency information varies depending on the staff, the variation value has periodicity and the frequency information varies. For example, +3, -1, -1, -1, or +12,
It changes like -3, -3, -3, -3 (or -1 is 12 times).

On the other hand, when the frequency on the transmission side really changes, the frequency information is continuously biased to one side. Since the transmission line clock is stable, there is no sign change,
When the fluctuation occurs in one direction, the frequency of the transmission-side transmission path clock fluctuates, so that averaging is not performed and correction is performed using the frequency information as it is.

FIG. 7 is a block diagram showing the structure of a transmission path clock recovery circuit according to another embodiment of the present invention. In the figure, a transmission line clock recovery circuit 6 according to another embodiment of the present invention has the same configuration as the transmission line clock recovery circuit 5 according to another embodiment of the present invention, except that a control circuit 61 is added, and is the same. The same reference numerals are given to the components. The operation of the same constituents is the same as that of the other embodiments of the present invention.

In the control circuit 61, the frequency of the transmission side transmission line clock is changed by the frequency information being continuously increased or decreased, the stuff cycle being changed, or the average value of the frequency information being increased or decreased. The angular velocity correction circuit 4 so that high-speed pull-in can be performed when it is determined that there is fluctuation
1 is controlled. That is, as the correction value of the angular velocity, the gain of the feedback correction by the error signal is set to 1 or the gain is set sufficiently large so that the high-speed pull-in is performed.

On the other hand, since the variation of the stuff is repeated, the gain of the correction is controlled so that it is sufficiently smaller than 1 based on this variation. Or, when the average value is almost constant, it is determined that the stuffing is being performed steadily, and the clock frequency does not change following the stuffing jitter.
The gain of the correction is controlled to be sufficiently smaller than 1 using the average value of the frequency information.

Further, in controlling the fluctuation of the transmission line clock, a rapid change does not usually occur in the stable state. Therefore, when the error signal Δ is large to some extent, the angular velocity is corrected not by the loop gain becoming 1, but by the change amount. Is corrected to be a constant ratio. As a result, smooth frequency fluctuation can be performed.

By these controls, it is possible to regenerate a stable transmission path clock with high accuracy while making the pull-in high speed and not being influenced by the stuff jitter.

In this way, the frequency information NLs of the transmission side transmission line clock is obtained from the stuff information, the reproduction transmission line clock is counted at a cycle T of 1 / N of the NNI transmission line clock, and the reproduction clock frequency information NLr is obtained. Then, the difference signal Δ between the transmission side frequency information NLs and the reception side frequency information NLr is obtained, and the angular velocity of the transmission path clock for each basic cycle is obtained from the difference signal Δ, and the transmission path clock for each basic clock cycle is obtained. The angular velocities are added to obtain the phase angle, the transmission side transmission path clock is regenerated from the phase angle, and the transmission side transmission path clock FLs and the NNI transmission path clock FL
By obtaining the frequency information NLr on the receiving side from n and n, the sample clock can be obtained from the digital phase angle. As a result, the frequency is accurately corrected from the error signal, and the transmission path clock having the frequency corrected according to the angular velocity corrected for each count cycle can be regenerated.

Since the above processing is digital processing,
If the staff information is averaged and controlled with high accuracy, the reproduction frequency is corrected correctly according to the control signal value, and if the angular velocity value is constant, the generated frequency is kept constant regardless of temperature fluctuations. Be drunk

In other words, since the frequency can be corrected accurately for each control cycle, if the gain of the feedback loop is set to 1, the sampling clock with the correct frequency can be obtained in the next control cycle. It enables high-speed pull-in.

Further, since the above-mentioned processing is digital processing, there is no temperature dependence, there is no influence on the control system due to noise, control correction by an error signal can be accurately and accurately performed, and reproduction depending on temperature dependence is performed. No phase shift of the transmission line clock occurs.

In order to improve the accuracy of the above processing, the magnitude of the angular velocity is adaptively controlled by checking the staff information of NNI. Stabilize the reproduction clock by averaging the staff information and making the response sensitivity less sensitive to fluctuations (jitter) in the staff information, or making it hardly follow, and changing the average value of the staff information. On the other hand, control is performed to quickly respond to shorten the pull-in time.

The phase angle generator 43 generates a high frequency as the angular velocity increases, and in the next count cycle, a frequency higher by the angular velocity correction value Δω is generated as the count value of the frequency information on the receiving side, and the error Δ The ratio of the angular velocity correction value Δω with respect to is adaptively changed.

At the time of high-speed pull-in, the gain is corrected by almost 1. The gain is very small in the steady state. When the gain is set to 1 at the time of pulling in, the error signal is corrected to 1 after one count cycle, and the frequency is pulled to a frequency that matches the transmitting side, and the pull-in time becomes extremely short.

[0099]

As described above, according to the present invention, a transmission line clock regenerating circuit for regenerating the same transmission line clock as the transmitting side at the receiving side of an apparatus for asynchronously transmitting a signal through a network transmission line In addition, the number of transmission side transmission path clocks in one frame period is obtained from the information subjected to the stuff multiplex processing in step 1, and the number of reproduction transmission path clocks in one frame period is obtained, and the difference between the number of transmission side transmission path clocks and the number of reproduction transmission path clocks is obtained. , The angular velocity value for each transmission path clock in each basic clock cycle is corrected according to the difference, the corrected angular velocity is integrated for each basic clock cycle to obtain the phase angle, and the transmission path clock is reproduced from the phase angle. By doing so, the pull-in can be performed quickly and accurately without generating the reproduction frequency and the clock phase shift due to the temperature change. It can be, there is an effect that it is possible to reproduce high stability line clock with high precision without being affected by noise.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a transmission path clock recovery circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration example of the transmission path clock generator of FIG.

FIG. 3 is a block diagram showing another configuration example of the transmission path clock generator of FIG.

FIG. 4 is a block diagram showing a configuration of the clock waveform generator of FIG.

5 is a timing chart showing the operation of the clock recovery circuit of FIG.

FIG. 6 is a block diagram showing a configuration of a transmission path clock recovery circuit according to another embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of a transmission path clock recovery circuit according to another embodiment of the present invention.

FIG. 8 is a diagram showing a configuration of a device that encodes an image signal at 150M and transmits the encoded image signal.

FIG. 9: 600M asynchronously multiplexed and transmitted 150M on a 600M network transmission line, separated at the receiving side and returned to 150M 600M
FIG. 3 is a diagram showing a configuration of network transmission of the above.

FIG. 10 is a diagram showing a configuration of an image receiving device.

FIG. 11 is a diagram showing a configuration of a decoding device which reproduces a sampling clock by obtaining frequency information and reproduces an image signal.

[Explanation of symbols]

1 O / E converter 2 staff separation circuit 3 buffer memory 4, 5, 6 Transmission line clock recovery circuit 41 Subtractor 42 Angular velocity correction circuit 43 Phase angle generation circuit 44 Transmission line clock generator 45 NNI network transmission line clock generation circuit 46 1 / N frequency divider 47 counter 48 basic clock generator 51 Averaging circuit 61 Control circuit

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04L 7/027 H04J 3/00 H04J 3/07 H04L 7/033 H03L 7/06

Claims (5)

(57) [Claims] 1. A transmission line clock regenerating circuit for regenerating the same transmission line clock as a transmitting side at a receiving side of a device for asynchronously transmitting a signal through a network transmission line, the information being subjected to stuff multiplex processing at the transmitting side. Means for obtaining the number of transmission side transmission line clocks in one frame period, means for obtaining the number of reproduction transmission line clocks in the one frame period, and means for obtaining a difference between the number of transmission side transmission line clocks and the number of reproduction transmission line clocks , Means for correcting the value of the angular velocity for each transmission path clock in each basic clock cycle according to the difference, means for integrating the corrected angular velocity for each basic clock cycle to obtain a phase angle, and from the phase angle A transmission line clock regenerating circuit having means for regenerating a transmission path clock and means for generating the basic clock. 2. A means for averaging the transmission-side transmission path clock, and a means for adaptively switching between the averaged value and the value of the transmission-side transmission path clock. The described transmission line clock recovery circuit. 3. A means for averaging the transmission side transmission path clock, and a means for adaptively varying the correction value of the angular velocity according to a change in the value of the transmission side transmission path clock. The transmission line clock recovery circuit according to claim 1. 4. The means for regenerating the transmission line clock from the phase angle generates a triangular waveform with a predetermined bit set in advance for the signal of the phase angle, and the frequency component of the transmission line clock from the triangular waveform. 4. The transmission path clock recovery circuit according to claim 1, further comprising a tank circuit for extracting. 5. The transmission path clock regenerating circuit according to claim 1, wherein the basic clock is a clock obtained by dividing the transmission side transmission path clock.