KR20040009795A - PLL having prescaler - Google Patents

Abstract

PURPOSE: A PLL(Phase Locked Loop) including a prescaler is provided to divide an output value of a voltage controlled oscillator in all bands of frequencies by using a general purpose prescaler. CONSTITUTION: A PLL including a prescaler includes a prescaler(34), a programmable counter(35), a swallow counter(36), and a controller(37). The prescaler(34) is used for dividing a frequency of an output clock signal of a voltage controlled oscillator. The programmable counter(35) is used for receiving an output signal of the prescaler(34). The swallow counter(36) is used for receiving the output signal of the prescaler(34) and controlling a division ratio of the prescaler(34). The controller(37) is used for outputting a mode control signal for controlling the prescaler(34) by using the outputs of the programmable counter(35) and the swallow counter(36).

Description

Phase Control Loop Circuit with Prescaler {PLL having prescaler}

The present invention relates to a phase locked loop (PLL) comprising a prescaler, and more particularly to the value of a voltage controlled oscillator (VCO) in all frequency bands using a general purpose prescaler. A phase control loop circuit PLL comprising a prescaler capable of dividing.

1 is a block diagram illustrating a general phase control loop circuit using a prescaler.

The phase control loop circuit PLL includes a phase comparator 11 for comparing the phase of the external clock signal ECLK and the phase of the program clock signal PCLK, and a low band filter (LPF) 12 for filtering the output signal of the phase comparator 11. And the output frequency fvco of the internal clock signal ICLK output from the voltage controlled oscillator 13 and the voltage controlled oscillator 13 which generate a signal having a frequency proportional to the DC signal of the low band filter 12. A prescaler 14 for dividing by M, and a program counter 24 for dividing the frequency of the output clock signal divided by the prescaler 14 at 1 / N to output the program clock signal PCLK.

The output frequency fvco of the internal clock signal ICLK of the voltage controlled oscillator 13 is first divided by 1 / M in the prescaler 25, and then divided by 1 / N by the program counter 24, so as to compare the frequency of the program clock signal PCLK. Negative feedback as fp is input to the phase comparator 11.

Here, the comparison frequency fp of the program clock signal PCLK is defined as shown in [Equation 4].

[Equation 4]

Therefore, the output frequency fvco of the internal clock signal ICLK is defined as shown in [Equation 5]. Where fp = fr.

[Equation 5]

When the division ratio N of the program counter 24 is changed in Equation 5, the output frequency fvco changes in steps of M x fr. Therefore, the channel separation, which is the frequency interval of the channel, becomes M × fr, and the reference frequency fr of the external clock signal ECLK in the synthesizer becomes 1 / M of the channel separation.

FIG. 2 is a block diagram illustrating a phase control loop circuit PLL using a swallow method in which channel separation is set to a reference frequency fr of the external clock signal ECLK according to the related art.

The phase control loop circuit PLL includes a phase comparator 21 for comparing the phase of the external clock signal ECLK and the phase of the program clock signal PCLK, a low band filter LPF 22, a voltage controlled oscillator 23, and 1 / M. And a swallow counter for controlling the division ratio of the pre-scaler 24, a dual modulus prescaler 24 having a 1 / (M + 1) division ratio, a programmable counter 25 having a 1 / N division ratio, and a prescaler 24 26, a control unit 27 for outputting a mode control signal MC for controlling the prescaler 24 using the output of the swallow counter 26 and the output PCLK of the program counter 24, and an external clock signal ECLK. SBI which is enabled in the enable signal LE in synchronization with the control signal and sets the set value M of the prescaler 24, the set value N of the programmable counter 25 and the set value A of the swallow counter 26 using data DATA. (Serial Bit Interface).

The output frequency fvco of the voltage controlled oscillator 23 is divided by the dual modulus prescaler 24 having 1 / M and 1 / (M + 1) division ratios and input to the program counter 25 and the swallow counter 26. do.

The swallow counter 26 is used for the division ratio control of the prescaler 25, and the division ratio of the prescaler 24 is set to 1 / (M + 1) while the swallow counter 26 is in operation.

When the swallow counter 26 counters A pulses, the division ratio of the prescaler 24 is set to 1 / M. That is, the time of A / N is a division of 1 / [(M + 1) × N], and the time of (N-A) / N is a division of 1 / M × N.

At this time, the comparison frequency fp is defined by Equation 6.

[Equation 6]

Therefore, the output frequency fvco is defined by [Equation 7]. Where fp = fr.

[Equation 7]

In Equation (7), N has a coefficient relationship with M, but since there is no coefficient relationship with A, changing the value of A changes only the reference frequency fr. Thus, the prescaler 24 can be used and the channel separation can be set to the reference frequency fr. In particular, in the frequency synthesizer of a high frequency, the frequency division ratio of the prescaler 24 is set to be large, and the pulse swirl method is used.

In general, the output frequency fvco of the pulse swirl method is set according to [Equation 8].

[Equation 8]

Here, M is the division ratio of the prescaler 24, N is the setting value of the program counter 25, and A is the setting value of the swallow counter 26, and has A <N relationship. In addition, fosc represents a reference oscillation frequency and R represents a setting value of a reference counter.

3 is a detailed circuit diagram of the prescaler 24 of the general phase control loop circuit PLL shown in FIG.

The prescaler 24 includes two D flip-flops FF1 and FF2 connected in series in which the internal clock signal ICLK of the voltage controlled oscillator 23 is applied to the clock input terminal CLK, and the output Q of the front stage is applied to the input D of the rear stage. NOR gate NOR1 negatively sums the output signals D8, D16, D32, D64, D128 and the mode control signal MC of the prescaler 24, and the inverted output signal Qb of the D flip-flop FF2 and the output signal MCO of the NOR gate NOR1 are negated. D flip-flop FF3 and D flip-flops to which the NAND gate ND1 to be logically multiplied, the internal clock signal ICLK of the voltage controlled oscillator 23 is applied to the clock input terminal, and the output signal of the NAND gate ND1 is applied to the data input terminal D. And a NAND gate ND2 for negatively multiplying the output signals of FF2 and FF3 to the data input terminal of the D flip-flop FF1, and a divider 29 for dividing the frequency of the inverted output signal of the D flip-flop FF1.

Here, the divider 29 has a plurality of D flip-flops FF4, FF5, and FF6 connected in series in which the inverted output signal Qb of the front stage is applied to the clock input terminal CLK of the rear stage and its output signal Q is applied to the input terminal D. , FF7, FF8. Here, an example will be described in which frequency is divided into 1/8, 1/16, 1/32, 1/64, and 1/128 times using five flip-flops FF4, FF5, FF6, FF7, and FF8). .

However, the prescaler 24 is predesigned according to the frequency used, and when used in a general low band, it is designed using a general D flip-flop, and at a high frequency of 100 MHz or more, a True Single Phase Clock (TSPC) structure or a CML (Current). Since the design must be performed using a D flip-flop using a Mode Logic) structure, the prescaler has to be designed differently according to the frequency used.

An object of the present invention for solving such a problem is to provide a general-purpose phase control loop circuit using a prescaler that can be used at both low and high frequencies.

1 is a block diagram illustrating a general phase control loop circuit PLL.

FIG. 2 is a detailed circuit diagram of a prescaler of the general phase control loop circuit PLL shown in FIG.

3 is a block diagram illustrating a phase control loop circuit PLL using the pulse swirl method in accordance with the present invention.

4 is a detailed block diagram illustrating a prescaler of the phase control loop circuit PLL using the pulse swirl method according to the present invention shown in FIG.

The phase control loop circuit of the present invention for achieving the above object,

A prescaler for dividing the frequency of the output clock signal of the voltage controlled oscillator;

A programmable counter to which an output of the prescaler is applied; And

It includes a swallow counter for receiving the output of the prescaler to control the division ratio of the prescaler,

The prescaler is,

And selectively driving a structure corresponding to a frequency of an external clock signal input according to the output signal of the swallow counter.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a block diagram illustrating a phase control loop circuit using the pulse swallow method according to the present invention.

The phase control loop circuit PLL includes a phase comparator 31 for comparing the phase of the external clock signal ECLK inputted from the outside with the phase of the programmable clock signal PCLK, a low pass filter (LPF) 32, and a voltage. The control oscillator VCO 33, the prescaler 34 which divides the frequency of the internal clock signal ICLK of the voltage controlled oscillator 33 into 1 / M or 1 / (M + 1), and the output of the prescaler 34 are applied. A programmable counter 35, a swallow counter 36 for controlling the division ratio of the prescaler 34 by receiving the output of the prescaler 34, and output signals of the programmable counter 35 and the swallow counter 36. The control unit 37 for outputting the mode control signal MC for controlling the prescaler 34 by means of the prescaler 34 and the enable signal LE in synchronization with the external clock signal ECLK, and setting the prescaler 34 using data DATA. Value M, programmable count Setting the set value A of the counter 36 as a set value N and a swallow of 35, and by using the N input count value and a SBI (38) for controlling a prescaler (34). It is assumed here that the program counter 35 is an N bit counter and the swallow counter 16 is an A bit counter. A <N.

Therefore, in the phase control loop circuit of the swirl method using the channel frequency as the fundamental frequency fr of the external clock signal ECLK inputted, the frequency of the internal clock signal ICLK of the voltage controlled oscillator 33 is the dual modulus prescaler 34. Is divided by the division ratio of 1 / M and input to the programmable counter 35 and the swallow counter 36. Here, the division ratio of the prescaler 34 becomes 1 / (M + 1) while the swallow counter 36 is in operation.

When the swallow counter 36 counts A pulses, the division ratio of the prescaler 34 is 1 / M.

In this case, the comparison frequency fp of the programmable clock signal PCLK of the program counter 35 may be represented by Equation 1 below.

[Equation 1]

Here, the output frequency fvco is the frequency of the internal clock signal ICLK of the voltage controlled oscillator 13, M is the division ratio of the prescaler 14, N is the set value of the programmable counter 15 of the phase control loop circuit, and A Is the set value of the swallow counter 16.

Here, N is a coefficient relationship with respect to M, but since it is not related with A, changing the value of A changes the frequency fr. In this way, the prescaler can be used, and the channel separation can be set to the reference frequency fr. In particular, in a high frequency frequency synthesizer, a pulse swirl method is used because the division ratio of the prescaler 34 is set large.

In general, the output frequency fvco of the internal clock signal ICLK representing the function of the phase control loop circuit using the pulse swirl method is defined by the following [Equation 2].

[Formula 2]

Here, the output frequency fvco is the frequency of the internal clock signal ICLK of the voltage controlled oscillator 33, M is the division ratio of the prescaler 34, N is the set value of the programmable counter 35 of the phase control loop circuit, A Denotes a setting value of the swallow counter 36 of the phase control loop circuit, A <N, and fosc denotes a reference oscillation frequency, and R denotes a reference counter.

FIG. 5 is a detailed block diagram illustrating a prescaler of the phase control loop circuit PLL using the pulse swirl method according to the present invention shown in FIG. 4.

The prescaler 34 includes two D flip-flops FF11 and FF12 connected in series in which the internal clock signal ICLK of the voltage controlled oscillator 33 is applied to the clock input terminal CLK, and the output Q of the front stage is applied to the input D of the rear stage, The internal clock signal ICLK of the voltage controlled oscillator 33 is applied to the clock input terminal CLK, and two D flip-flops FF13 and FF14 connected in series, with the output Q at the front end to the input D at the rear end, and the swallow counter 36 Noa gate NOR11 for logically combining the upper bits of the count signal NCNT of the N1), inverter INV11 for inverting the output signal of the NOR gate NOR11, and Noah gate NOR12 for logically combining the inverted output signals of the D flip-flops FF12 and FF14, NOR gate NOR13, which negatively sums the output signals D8, D16, D32, D64, D128 and the mode control signal MC of the prescaler 34, and output signal MCO of NOR gate NOR13 and output signal MCO of NOR gate NOR13. D flip-flop FF15 and D flip-flops to which the NAND gate ND11 to be logically multiplied, the internal clock signal ICLK of the voltage controlled oscillator 33 is applied to the clock input terminal, and the output signal of the NAND gate ND11 is applied to the data input terminal D. NAND gate ND12 for applying one of the output signals of FF12 and FF14 and the output signal of D flip-flop FF15 to the data input terminal of D flip-flops FF11 and FF13, and the inverted output signal of D flip-flops FF11 and FF13. And a divider 39 for dividing the frequency of one of the Qbs. Here, only a portion corresponding to the upper bits of the count signal NCNT is applied to the NOR gate NOR11.

The output signal of the NOR gate NOR11 is applied to and controlled by the reset terminals of the D flip-flops FF11 and FF12, and the output signal of the inverter INV11 is applied to and controlled by the reset terminals of the D flip-flops FF13 and FF14.

Therefore, when the external clock signal ECLK of low frequency is applied, the output signal of the NOR gate NOR11 is enabled, resets and disables the D flip-flops FF11 and FF12, and enables the D flip-flops FF13 and FF14 to operate at a low frequency. When the same operation as the prescaler is performed and the high frequency external clock signal ECLK is applied, the output signal of the inverter INV11 is enabled to reset and disable the D flip-flops FF13 and FF14, and the D flip of the TSPC and ECL structures. Flops FF11 and FF12 are enabled to operate as prescalers operating at high frequencies.

Here, the divider 39 has a plurality of D flip-flops FF16, FF17, and FF18 connected in series to which the inverted output signal Qb at the front end is applied to the clock input terminal CLK at the rear end and its output signal Q is applied to the input terminal D. , FF19, FF20. Here, an example will be described in which frequency is divided into 1/8, 1/16, 1/32, 1/64, and 1/128 times using five flip-flops FF16, FF17, FF18, FF19, and FF20. Therefore, the number and configuration of flip-flops can be changed according to the configuration of the system.

As such, the prescaler 34 of the phase control loop circuit according to the present invention operates by enabling a general D flip-flop used in a general low band when an external clock signal having a low frequency is applied according to a frequency used, At the high frequency of 100MHz or higher, the D flip-flop using the TSPC structure and the CML structure is enabled to operate, and thus the prescaler driving method may be modified according to the used frequency, and thus it may be used universally.

As described above, the prescaler of the phase control loop circuit according to the present invention connects the D flip-flops having different structures in parallel, and selectively uses the D flip-flops according to the input frequency, thereby making it universally available at low and high frequencies. There is an effect that can be used.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (5)

A prescaler for dividing the frequency of the output clock signal of the voltage controlled oscillator; A programmable counter to which an output of the prescaler is applied; A swallow counter configured to receive an output of the prescaler and control a division ratio of the prescaler; And Control means for outputting a mode control signal for controlling the prescaler using the output of the programmable counter and the swallow counter, The prescaler is, And a prescaler for selectively driving a structure corresponding to a frequency of an external clock signal using a setting value of the programmable counter. The method of claim 1, The prescaler is, A plurality of first flip-flops operating in response to a clock signal of a low frequency; A plurality of second flip-flops that operate in response to a high frequency clock signal; And And a control means for selectively driving the first flip-flop or the second flip-flop in accordance with the frequency of the external clock signal. The method of claim 2, And said control means comprises a prescaler comprising logic means for combining only the upper bits of a set value of said programmable counter. The method of claim 2, The second flip-flop, A phase control loop circuit comprising a prescaler, characterized in that it comprises a flip-flop of a TSPC (True Single Phase Clock) structure. The method of claim 2, The second flip-flop, A phase control loop circuit comprising a prescaler, characterized in that it comprises a flip-flop of a current mode logic (CML) structure.