JP2000138580A - Prescaler - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a prescaler which can prevent malfunctions by generating the optimum select signal. SOLUTION: A prescaler 8 is provided with a selection circuit 13, a 1/N frequency divider 14, a selection control circuit 15, and a synchronous circuit 16. The selection circuit 13 selects either one of a complementary signal composed of a positive-phase signal (a) or a complementary signal composed of an anti-phase signal (b) in accordance with a select signal S and outputs the selected signal (c). The frequency divider 14 divides the frequency of the selected signal (c) by N. The control circuit 15 outputs the signal (g) obtained by dividing the frequency of the output signal XPout of the frequency divider 14. The synchronous circuit 16 outputs the output signal (g) of the control circuit 15 as the select signal S synchronously to the complementary signals (a) and (b).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL which operates to match an output signal frequency to a set frequency.
The present invention relates to a prescaler of a comparison frequency divider used for a frequency synthesizer.

Recently, PLL frequency synthesizers (hereinafter simply referred to as “PL”) have been used in mobile communication devices such as mobile phones and mobile phones.
L circuit). This PLL circuit,
The pulse swallow method is mainly employed, and it is necessary to prevent a malfunction of a prescaler provided in the comparison frequency divider.

[0003]

2. Description of the Related Art FIG. 8 shows an example of a conventional prescaler. The prescaler is provided, for example, in a comparison frequency divider of a PLL circuit employing a pulse swallow method. This prescaler divides an input signal by 2N or (2N +
1) Perform a 2-modulus operation for frequency division.

More specifically, the prescaler includes a 1/2 frequency divider 51, a selection circuit 52, a 1 / N frequency divider 53, and a selection control circuit 54. The frequency signal fv is input to the 分 frequency divider 51 from the outside (an output terminal of a PLL circuit not shown) via a buffer circuit 55. 1/2 frequency divider 5
1 divides the frequency signal fv by 2 and outputs the divided signal a and the inverted signal b complementary to the divided signal a to the selection circuit 52.

The signals a and b and the select signal S are input to a selection circuit 52. The selection circuit 52 converts the frequency-divided signal a or the inverted signal b into the selection signal c according to the selection signal S.
Is output to the 1 / N divider 53. More specifically, the selection circuit 52 selects the frequency-divided signal a in response to the H-level select signal S, and selects the inverted signal b in response to the L-level select signal S. Then, the selection circuit 52 outputs the selected frequency-divided signal a or the inverted signal b as the selection signal c.

The 1 / N frequency divider 53 frequency-divides the selection signal c input from the selection circuit 52 by N, and outputs the frequency-divided signal Pout externally (a main counter and a swallow counter of a comparison frequency divider (not shown)). And to the selection control circuit 54.
The 1 / N frequency divider 53 performs a frequency division operation by counting the rise of the selection signal c.

[0007] The selection control circuit 54 has the divided signal Pou
t and a module control signal (hereinafter referred to as a module signal) MD are input. The selection control circuit 54 outputs a signal based on the frequency-divided signal Pout as the selection signal S to the selection circuit 52 according to the module signal MD. More specifically, the selection control circuit 54 outputs a signal based on the frequency-divided signal Pout as the select signal S in response to the H-level module signal MD, and outputs the frequency-divided signal Pout in response to the L-level module signal MD. Regardless, it holds the select signal S. Note that the module signal MD is a signal for controlling switching of the modulus operation of the prescaler, and is generated based on the count operation of the main counter and the swallow counter of the comparison frequency divider (not shown).

In the prescaler configured as described above,
The frequency signal fv is frequency-divided by a 1/2 frequency divider 51,
A divided signal a and its inverted signal b are used. Selection control circuit 5
When the L-level module signal MD is input to No. 4, the select signal S is not inverted. Therefore, the selection circuit 5
2 is fixed to one of the divided signal a and the inverted signal b. Then, the selection signal c is
The signal is frequency-divided by N in a 1 / N frequency divider 53 and output to the outside as a frequency-divided signal Pout. Therefore, the frequency signal fv is a frequency-divided signal Pout obtained by dividing the frequency by 2N by the prescaler.

When an H-level module signal MD is input to the selection control circuit 54, the selection signal S
Is a signal that repeatedly rises and falls every cycle of the divided signal Pout. Therefore, the selection signal c output from the selection circuit 52 is a signal in which the frequency-divided signal a and the inverted signal b are alternately selected for each cycle of the frequency-divided signal Pout. Then, for example, when the selected divided signal a rises and the inverted signal b is selected, the rising of the selection signal c thereafter becomes 以後 cycle of the divided signal a (frequency signal fv
(One cycle). Also, for example, when the frequency-divided signal a is selected when the selected inverted signal b rises, the rise of the selection signal c thereafter becomes 周期 cycle of the frequency-divided signal a (the frequency signal fv (One cycle).

The selection signal c is frequency-divided by N in a 1 / N frequency divider 53 and output to the outside as a frequency-divided signal Pout. Here, the rising of the selection signal c is delayed by one cycle of the frequency signal fv for each cycle of the divided signal Pout, and the 1 / N divider 53 counts the rising of the selection signal c to perform the dividing operation. Is performed, the frequency signal fv becomes a frequency-divided signal Pout frequency-divided by (2N + 1) by the prescaler. Thus, the divided signal Pout is
This is a signal obtained by dividing the frequency signal fv by 2N or (2N + 1).

[0011]

The divided signal P
out delays the rising or falling timing of the frequency-divided signal a and the inverted signal b due to variations in the characteristics of the transistors constituting the 1 / N divider 53, temperature, power supply, and the like. , Its delay time is not constant. From this, the module signal MD and the divided signal P
out is a divided signal a
The rising or falling timing of the inverted signal b is delayed, and the delay time is not constant.

Accordingly, a spike may occur in the selection signal c. More specifically, for example, immediately after the divided signal a selected as the selection signal c rises, the select signal S goes to the L level, and when the inverted signal b is selected, the short period of the divided signal a H level component becomes a spike. Then, the 1 / N divider 53 that counts the rise of the selection signal c may count the spikes. At that time, the divided signal Pout is obtained by dividing the frequency signal fv by (2N-1). It becomes a signal. Therefore, in the prescaler, the module signal M
There is a problem that a malfunction occurs in accordance with the rising or falling timing of D or the divided signal Pout.

An object of the present invention is to provide a prescaler capable of generating an optimal select signal and preventing a malfunction.

[0014]

According to the first aspect of the present invention, the selection circuit selects one of a complementary signal consisting of a positive-phase signal and a negative-phase signal according to the select signal, The selection signal is output. In the frequency divider, the selection signal is frequency-divided. The selection control circuit outputs a signal obtained by dividing the output signal of the frequency divider or a signal of a predetermined level based on the module control signal. In the synchronization circuit, an output signal of the selection control circuit is synchronized with the complementary signal, and the signal is output as a select signal. Therefore, when the selection signal is switched from one of the normal phase signal and the negative phase signal to the other in response to the selection signal, no spike occurs in the selection signal.

According to a second aspect of the present invention, in the D flip-flop circuit, an output signal of the selection control circuit is input as a data signal and a signal synchronized with the complementary signal is input as a clock signal. It is composed.

According to the third aspect of the present invention, in the 1/2 frequency divider, the input signal is frequency-divided by 2 to be the complementary signal. The input signal is input to the D flip-flop circuit as a clock signal, and the select signal is synchronized with the complementary signal based on the input signal.

The selection control circuit may include a latch circuit for latching the output signal of the frequency divider based on the module control signal, and counting the output signal of the latch circuit. And a T flip-flop circuit for outputting the signal.

In the synchronous circuit, the output signal of the selection control circuit is input as a data signal and the input signal is input as a clock signal.
The flip-flop circuit includes a latch circuit that latches an output signal of the D flip-flop circuit and outputs the latched signal as the select signal.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment in which the present invention is embodied in a PLL circuit of a pulse swallow system will be described below with reference to FIGS.
It will be described according to. As shown in FIG. 2, the PLL circuit
An oscillator 1, a reference frequency divider 2, a phase comparator 3, a charge pump 4, a low-pass filter (hereinafter, referred to as LPF) 5, a voltage-controlled oscillator (hereinafter, referred to as VCO) 6, and a comparative frequency divider 7 are provided.

The oscillator 1 outputs a reference clock signal CK having a natural frequency based on the oscillation of the crystal oscillator to the reference frequency divider 2. The reference frequency divider 2 is configured by a counter circuit, and based on a preset frequency division ratio, the reference clock signal CK
, And outputs the reference signal fr to the phase comparator 3.

The phase comparator 3 receives the reference signal fr,
The comparison signal fp from the comparison frequency divider 7 is input. Then, the phase comparator 3 outputs to the charge pump 4 pulse signals ΦR and ΦP corresponding to the frequency difference and the phase difference between the reference signal fr and the comparison signal fp.

The charge pump 4 outputs an output signal SCP to the LPF 7 based on the pulse signals ΦR and ΦP output from the phase comparator 3. This output signal SCP
Is a DC component including a pulse component, and the DC component rises and falls with the frequency fluctuation of the pulse signals ΦR and ΦP, and the pulse component changes based on the phase difference between the pulse signals ΦR and ΦP. .

The LPF 5 smoothes the output signal SCP of the charge pump 4 and removes the high-frequency component from the output signal SCP.
The LPF is output to the VCO 6. The VCO 6 is connected to the L
An output signal fv having a frequency corresponding to the voltage value of the output signal SLPF of the PF5 is output to an external circuit (not shown).
Output to the comparison frequency divider 7.

The comparison frequency divider 7 includes a prescaler 8 and
It comprises a main counter 9, a swallow counter 10, and a control circuit 11. The prescaler 8 includes the V
The output signal fv of CO6 is input and its prescaler 8
Divides the frequency of the input signal fv by 2N or 2N + 1 and outputs it to the main counter 9 and the swallow counter 10 as an output signal Pout.

The swallow counter 10 frequency-divides the output signal Pout of the prescaler 8 by A and outputs the frequency-divided signal to the control circuit 11. The control circuit 11 sends a module control signal (hereinafter referred to as a module signal) M to the prescaler 8 based on the frequency-divided signal of the swallow counter 10.
D is output. More specifically, while the swallow counter 10 is counting A pulses, the control circuit 11
An H-level module signal MD is output. When the H-level module signal MD is input, the prescaler 8 divides the input signal fv by 2N + 1. Further, after the swallow counter 10 counts A pulses, the control circuit 11 continues to operate until the preset signal is input.
A level module signal MD is output. When the L-level module signal MD is input, the prescaler 8 divides the input signal fv by 2N.

The main counter 9 includes a prescaler 8
Is divided by M (M> A), and the divided signal is output to the control circuit 11 and to the phase comparator 3 as a comparison signal fp. Control circuit 11
Means that every time the frequency-divided signal from the main counter 9 rises,
That is, every time the main counter 9 divides the input signal Pout by M, it outputs a preset signal to the swallow counter 11. The swallow counter 10 is preset based on the preset signal, and starts counting the A pulses as described above.

Therefore, the prescaler 8 converts the input signal fv to 2N + based on the module signal MD at the H level.
After performing the operation of dividing by 1 A times, the operation of dividing the input signal fv by 2N based on the module signal MD of L level is performed (M−A) times. As a result, the comparison signal fp output from the main counter 9 changes the input signal fv from ｛(2N
+1) A + 2N (MA)｝ (= 2NM + A).

Next, a specific configuration of the prescaler 8 is shown in FIG.
And FIG. As shown in FIG. 1, the prescaler 8 includes a 1/2 frequency divider 12, a selection circuit 13, and a 1 / N
It includes a frequency divider 14, a selection control circuit 15, and a synchronization circuit 16.

As shown in FIG. 3, the 1/2 frequency divider 12
It is composed of a T flip-flop circuit (hereinafter, referred to as a TFF circuit). The frequency signal fv is input from the VCO 6 to the 分 frequency divider 12 via the buffer circuit 17 as a clock signal. The 1/2 frequency divider 12 outputs the frequency signal f
An output signal that is inverted at each rising edge of v, ie, a frequency signal f
A divided signal a as a positive-phase signal obtained by dividing v by 2 and an inverted signal b as a reverse-phase signal complementary to the divided signal a are output to the selection circuit 13.

The selection circuit 13 receives the signals a and b and the select signal S. The selection circuit 13 outputs one of the frequency-divided signal a and the inverted signal b to the 1 / N frequency divider 14 as the selection signal c in accordance with the select signal S. More specifically, the selection circuit 13 selects the frequency-divided signal a in response to the H-level select signal S, selects the inverted signal b in response to the L-level select signal S, and outputs it as the selection signal c. .

As shown in FIG. 3, the 1 / N frequency divider 14
It is composed of a counter circuit composed of three stages of TFF circuits. That is, in the present embodiment, N is 8, and the prescaler 8 divides the input signal fv by 16 or 17. The selection signal c is input as a clock signal from the selection circuit 13 to the first stage TFF circuit of the 1 / N frequency divider 14. The first-stage TFF circuit outputs to the second-stage TFF circuit an output signal that is inverted each time the selection signal c rises, that is, a signal d obtained by dividing the selection signal c by two. The signal d is input as a clock signal to the second stage TFF circuit. The second-stage TFF circuit converts the output signal, which is inverted every time the signal d rises, that is, the signal e obtained by dividing the selection signal c by 4 into the third-stage TFF circuit
Output to FF circuit. The signal e is input to the third-stage TFF circuit as a clock signal. Third stage TFF
The circuit outputs an output signal that is inverted every time the signal e rises, that is, a signal obtained by dividing the selection signal c by 8 to the outside (the main counter 9 and the swallow counter 10) via the buffer circuit 18 as a divided signal Pout. At the same time, a signal XPout which is a complementary signal of the frequency-divided signal Pout is output to the selection control circuit 15.

The selection control circuit 15, as shown in FIG.
It comprises a latch circuit 15a and a TFF circuit 15b. The signal XPout is input as a data signal to the latch circuit 15a of the selection control circuit 15, and the module signal MD is input as a gate signal. The latch circuit 15a outputs the signal XPout as an output signal f to the TFF circuit 15b in response to the module signal MD at the H level. Further, the latch circuit 15a holds the output signal f at the current level regardless of the signal XPout in response to the module signal MD at the L level. TFF circuit 15b
, The output signal f of the latch circuit 15a is input as a clock signal. The TFF circuit 15b includes the latch circuit 15
A signal which is inverted each time the output signal f of a rises is output to the synchronization circuit 16 as an output signal g of the selection control circuit 15. As a result, the selection control circuit 15 outputs a signal obtained by dividing the signal XPout by 2 in response to the H-level module signal MD as an output signal g, and responds to the L-level module signal MD regardless of the signal XPout. , Control signal g
At the current level.

The synchronizing circuit 16 comprises a D flip-flop circuit 16a as shown in FIG. Synchronous circuit 1
6, the output signal g of the selection control circuit 15 is input as a data signal, and the frequency signal fv is input as a clock signal via a buffer circuit 17. Synchronous circuit 16
Stores the output signal g of the selection control circuit 15 every time the frequency signal fv rises, and outputs the output signal g to the selection circuit 13 as the selection signal S.

Next, the operation of the prescaler 8 configured as described above will be described with reference to FIG. In this embodiment, the frequency division ratio (count number) A of the swallow counter 10 is set to "1".

The frequency signal fv is frequency-divided by the に て frequency divider 12 into a frequency-divided signal a and its inverted signal b. H
When the level module signal MD is input to the selection control circuit 15, the output signal f of the latch circuit 15a becomes a complementary signal XPout of the frequency-divided signal Pout. Then, the output signal g of the selection control circuit 15 becomes the signal f (signal XPout).
(In FIG. 4, it falls). When the frequency division ratio (count value) A of the swallow counter 10 is set to “2” or more and the H-level module signal MD is continuously input to the selection control circuit 15, the signal g becomes the frequency of the frequency-divided signal Pout. The signal repeats rising and falling every cycle.

Here, the signal XPout is expressed by a 1 / N frequency divider 1
4, the rising or falling of the frequency-divided signal a and the inverted signal b due to variations in the characteristics of each transistor included in the 1 / N divider 14, variations in temperature, power supply, and the like. Timing is delayed.
The output signal g of the selection control circuit 15 is
5 when generated by the TFF circuit 15b, variation in characteristics of each transistor included in the TFF circuit, temperature,
The rise or fall timing t1 of the signal XPout is delayed due to power supply variation or the like. Therefore, the output signal g of the selection control circuit 15 is not synchronized with the frequency-divided signal a and the inverted signal b.

However, when the frequency signal fv subsequently rises after the output signal g of the selection control circuit 15 falls, the L-level output signal g is temporarily stored in the synchronization circuit 16 and output from the synchronization circuit 16. The selected select signal S becomes L level.

Then, the selection signal c output from the selection circuit 13 is obtained by converting the frequency-divided signal a into the inverted signal b or the inverted signal b.
From the divided signal a. Since the select signal S is inverted when the frequency signal fv rises, the edges of the select signal S are synchronized with the edges of the divided signal a and the inverted signal b. Therefore, for example, as shown in FIG. 4, at the timing t2 when the selection signal c is switched from the frequency-divided signal a to the inverted signal b, the frequency-divided signal a falls, that is, the inverted signal b rises. Thus, no spike occurs in the selection signal c.

Thereafter, the falling and the rising of the selection signal c are delayed by a half cycle of the frequency-divided signal a (one cycle of the frequency signal fv). Then, the selection signal c is
It is frequency-divided by the 1 / N frequency divider 14 and output to the outside as a frequency-divided signal Pout. Here, the rising of the selection signal c is delayed by one cycle of the frequency signal fv every one cycle of the divided signal Pout, and the 1 / N divider 14 counts the rising of the selection signal c to perform the dividing operation. Is performed, the frequency signal fv is converted into (2N + 1) by the prescaler.
=) It is a frequency-divided signal Pout obtained by dividing the frequency by 17.

When the L level module signal MD is input to the selection control circuit 15, the latch circuit 15a
, The output signal g of the selection control circuit 15, and the select signal S are not inverted. Therefore, the selection signal c output from the selection circuit 13 is fixed to one of the frequency-divided signal a and the inverted signal b. Then, the selection signal c becomes 1 / N
The signal is frequency-divided by the frequency divider 53 and output to the outside as a frequency-divided signal Pout. Therefore, the frequency signal fv is a frequency-divided signal Pout obtained by dividing the frequency by (2N =) 16 by the prescaler. As described above, the frequency-divided signal Pout is a signal obtained by dividing the frequency signal fv by 16 or 17.

Next, the operation and effect of the prescaler 8 configured as described above will be described. (1) The synchronization circuit 16 synchronizes the select signal S with the frequency-divided signal a and the inverted signal b, that is, the frequency signal fv. Therefore, at the timing t2 when the selection signal c changes from the frequency-divided signal a to the inverted signal b, the frequency-divided signal a falls, that is, the inverted signal b rises. As a result, generation of a spike in the selection signal c is prevented. As a result, the prescaler 8 is prevented from malfunctioning even when the rising or falling timing of the module signal MD or the frequency-divided signal Pout is undefined.

The above embodiment may be modified and implemented as follows. The selection control circuit 15 and the synchronization circuit 16 of the above embodiment
May be changed to the selection control circuit 21 and the synchronization circuit 16 shown in FIG. More specifically, the selection control circuit 21 includes two TFF circuits 21a and 21b and a selection circuit 21c.

The TFF circuit 21a includes a 1 / N frequency divider 14
Is input as a clock signal. T
The FF circuit 21a outputs to the selection circuit 21c a signal inverted every time the signal XPout rises, that is, a signal h obtained by dividing the signal XPout by two and an inverted signal i which is a complementary signal of the signal h.

The module signal M is supplied to the TFF circuit 21b.
An inverted signal XMD which is a complementary signal of D is input as a clock signal. The TFF circuit 21b outputs to the selection circuit 21c a control signal j that is inverted every time the signal XMD rises, that is, every time the module signal MD falls.

The signals h and i, the control signal j and the control signal NA are input to the selection circuit 21c. The control signal NA corresponds to the main counter 9 and the swallow counter 1
A signal based on the first bit data of 0, which is L level when the value (MA) obtained by subtracting the numerical value of A from the set numerical value of M is L level, and is H level when it is odd number. Signal. When the L-level control signal NA is input, the selection circuit 21c is deactivated and the control signal j
Regardless of the above, the signal h is used as the output signal k to
Output to 2. The selection circuit 21c is activated when the H-level control signal NA is input. The activated selection circuit 21c selects one of the signal h and the signal i according to the signal j, and outputs the selected signal to the synchronization circuit 22 as an output signal k. That is, the activated selection circuit 21c switches between the signal h and the signal i and outputs it as the output signal k every time the module signal MD falls.

The synchronization circuit 22 includes a D flip-flop circuit (hereinafter, referred to as a DFF circuit) 22a and a latch circuit 22b.
And The DFF circuit 22a includes a selection control circuit 21
Is output as a data signal, and the frequency signal fv is input as a clock signal via the buffer circuit 17. The DFF circuit 22a stores the output signal k of the selection control circuit 21 every time the frequency signal fv rises, and outputs the signal k to the latch circuit 22b as the output signal 1 of the DFF circuit 22a.

The latch circuit 22b includes a DFF circuit 22a
Is input as a data signal, and the module signal MD is input as a gate signal. When the H-level module signal MD is input, the latch circuit 22b outputs the signal 1 to the selection circuit 13 as the select signal S. Further, when the L-level module signal MD is input, the latch circuit 22b holds the select signal S at the current level regardless of the signal l.

Next, the operation of the prescaler configured as described above will be described with reference to FIG. The description of the same parts as those in the above embodiment will be partially omitted. The division ratio (count value) A of the swallow counter 10 is set to "2".

When the signal XPout is generated by the 1 / N divider 14, the divided signal a is generated due to variations in characteristics of each transistor included in the 1 / N divider 14, temperature, power supply, and the like. The rising or falling timing of the inverted signal b is delayed. Also, when the output signal k of the selection control circuit 21 is generated by the selection control circuit 21, the output signal k of the selection control circuit 21 is different from the signal XPout due to variations in characteristics of each transistor included in the TFF circuit 21a, variations in temperature and power supply, and the like. , The rising or falling timing t1 is delayed. Therefore, the output signal k of the selection control circuit 21 is not synchronized with the frequency-divided signal a and the inverted signal b.

When the frequency signal fv rises after the output signal k of the selection control circuit 21 is inverted, the output signal 1 of the DFF circuit 22a of the synchronization circuit 22 is inverted. The signal 1 is output to the selection circuit 13 as the select signal S when the H-level module signal MD is input to the latch circuit 22b. When the L-level module signal MD is input to the latch circuit 22b, the select signal S is held at the current level.

When the select signal S is inverted, the select signal c output from the select circuit 13 becomes the inverted signal b from the frequency-divided signal a or the frequency-divided signal a from the inverted signal b. Here, the timing t at which the select signal S (signal 1) is inverted
2 is when the frequency signal fv rises, so that the select signal S is synchronized with the frequency-divided signal a and the inverted signal b. Therefore, for example, as shown in FIG. 6, the timing t2 at which the selection signal c changes from the frequency-divided signal a to the inverted signal b or from the inverted signal b to the frequency-divided signal a is determined when the frequency-divided signal a falls or when the frequency is inverted. It is when the signal b rises. This prevents spikes from occurring in the selection signal c. As a result, similarly to the above-described embodiment, this prescaler prevents malfunction even if the rising or falling timing of the module signal MD or the divided signal Pout is undefined.

When the value (MA) is an even number, for example, as shown in FIG. 7A, when the value M is "8" and the value A is "2", the selection control circuit 21 Is inactivated, and the output signal k of the selection control circuit 21 becomes the signal X
The signal h is obtained by dividing Pout by two.

When the value (MA) is an odd number, for example, as shown in FIG. 7B, when the value M is "8" and the value A is "1", the selection control circuit 21 Is activated, and the output signal k of the selection control circuit 21 becomes a signal that switches between the signal h and the signal i every time the module signal MD falls. As a result, the function of the signal k with respect to the module signal MD is adjusted, and the select signal S output when the H-level module signal MD is input to the latch circuit 22b is changed to the signal XPou.
The signal can be inverted based on the rise of t.

In the above embodiment, the synchronization circuit 16 is
Although the flip-flop circuit is used, the selection control circuit 1
5 may be constituted by another circuit as long as the output signal g can be synchronized with the signals a and b.

The prescaler 8 according to the above embodiment has the following features.
Although the configuration provided with the 、 frequency divider 12 is adopted, the frequency-divided signal fv is set as the signal a, and the inverted signal of the frequency-divided signal fv is set as the signal b.
A configuration without the 1/2 frequency divider 12 may be adopted. In this case, the signal “a” is output from the D flip-flop circuit 1 of the synchronization circuit 16.
6a. In this way, the frequency-divided signal fv (signal a) is frequency-divided by N or (N + ／) by the prescaler.

[0056]

As described in detail above, according to the present invention,
It is possible to provide a prescaler capable of generating an optimal select signal and preventing a malfunction.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram showing a prescaler according to an embodiment;

FIG. 2 is a block circuit diagram illustrating a PLL circuit according to one embodiment;

FIG. 3 is a circuit diagram showing a prescaler according to one embodiment;

FIG. 4 is a timing waveform chart showing an operation of the prescaler according to the embodiment;

FIG. 5 is a circuit diagram showing another example of a prescaler.

FIG. 6 is a timing waveform chart showing an operation of another example prescaler.

FIG. 7A is a timing waveform chart showing an operation of another prescaler. (B) A timing waveform chart showing an operation of another example prescaler.

FIG. 8 is a block circuit diagram showing a conventional prescaler.

[Explanation of symbols]

12 1/2 frequency divider 13 selection circuit 14 1 / N frequency divider (frequency divider) 15, 21 selection control circuit 16, 22 synchronization circuit a, b frequency-divided signal, inverted signal (positive-phase signal, negative-phase signal) (Complementary signal) c Select signal S Select signal MD Module control signal fv Frequency signal (input signal)

Claims (5)

[Claims] 1. A selection circuit for selecting one of a complementary signal consisting of a positive-phase signal and a negative-phase signal according to a select signal and outputting the select signal, and a frequency divider for dividing the select signal A selection control circuit that outputs a signal obtained by dividing the output signal of the frequency divider or a signal of a predetermined level based on a module control signal; and synchronizes the output signal of the selection control circuit with the complementary signal. And a synchronizing circuit for outputting the signal as the select signal. 2. The prescaler according to claim 1, wherein an output signal of the selection control circuit is input as a data signal, and a signal synchronized with the complementary signal is input as a clock signal. A prescaler comprising a circuit. 3. The prescaler according to claim 2, further comprising a 分 frequency divider that divides an input signal by two to generate the complementary signal, and a signal input as a clock signal to the D flip-flop circuit. Is the input signal. 4. The prescaler according to claim 1, wherein said selection control circuit latches an output signal of said frequency divider based on said module control signal, and said latch. A T flip-flop circuit for counting an output signal of the circuit and outputting the signal. 5. The prescaler according to claim 1, wherein the synchronization circuit includes: a D flip-flop circuit to which an output signal of the selection control circuit is input as a data signal and the input signal is input as a clock signal; A latch circuit for latching an output signal of the D flip-flop circuit and outputting the latch signal as the select signal.