JPH037189B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a synchronization system for driving various digital video equipment by generating a clock signal that is phase-synchronized with a synchronization signal of an input television signal when synchronously combining television signals such as so-called genlock. The present invention relates to a clock signal generator, and in particular, is capable of extremely quickly phase-synchronizing a clock signal generated from an original oscillator with an input synchronizing signal without any time delay.

Conventionally, when combining synchronization signals such as so-called genlock of television signals, a voltage controlled oscillator (VCO) is used as the source oscillator built into the synchronization signal generator, and the input synchronization signal and the output of the synchronization signal generator are It was common to use a so-called phase lock loop (PLL) device, which controls the voltage controlled oscillator of the original oscillator by feeding back phase error information obtained by comparing the phase with a synchronizing signal.
However, such a PLL device has serious drawbacks: (1) Since it uses a voltage controlled oscillator as the source oscillator, its control information is susceptible to fluctuations due to external noise mixed in or power supply voltage fluctuations.

(2) Since a phase lock loop is used, the rise of the phase locking effect on the input synchronizing signal is slow;
It takes time to obtain almost perfect phase synchronization, and quick response characteristics cannot be obtained.

It has two properties.

On the other hand, digital video equipment, which has recently been widely used for broadcasting, has a sampling clock that samples input analog video signals and digitizes them, or resamples input digital video signals to match the in-house standard synchronous disc. Such a sampling clock signal generally needs to be phase-locked to the input synchronization signal, and in particular to the horizontal synchronization signal.

In addition, in a normal television video signal transmission system, such a sampling clock signal is not necessarily transmitted together with a synchronization signal, so a sampling clock signal whose phase is synchronized with the input synchronization signal as described above is required. In this case, the required sampling clock signal is formed from the oscillation output signal of the original oscillator with a built-in synchronous signal generator that has been subjected to synchronous coupling such as Genlock as described above, or by the completely similar signal processing, It has been common practice to construct an oscillator whose phase can be synchronized to an input synchronizing signal according to a phase lock loop method, and to form a required sampling clock signal from its oscillation output signal.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional problems and eliminate their drawbacks, and to create a sampling clock signal that is stably and quickly phase-locked to an input synchronization signal without using a conventional phase lock loop or synchronous coupling. An object of the present invention is to provide a synchronous clock signal generating device which can easily generate a synchronous clock signal from an original oscillator with a built-in synchronous signal generator or from the output of a dedicated oscillator.

Another object of the present invention is to provide a synchronous clock signal generator that does not require expanding the dynamic range of phase control even if there is a large phase difference between the clock signal formed from the oscillator output and the input synchronous signal. It is about providing.

That is, the synchronous clock signal generator of the present invention includes a fixed frequency oscillator that oscillates at a frequency corresponding to a predetermined clock period, and an input synchronous signal by counting and frequency-downgrading the oscillation output signal of the fixed frequency oscillator. a counter that forms output synchronization signals of equal frequency; a phase comparator that compares the phases of the output synchronization signal and the input synchronization signal to detect a phase difference; an averager that calculates an average value over the period using the predetermined clock cycle as a measure; and a variable phase shifter for forming an output clock signal with a clock period of .

The present invention will be described in detail below with reference to the drawings.

First, FIG. 1 shows the basic configuration of an embodiment of the synchronous clock signal generator of the present invention. In the basic configuration shown in the figure, all the constituent elements are constructed with digital circuits, and the phase comparator 1
Therefore, the position of the input horizontal synchronization signal HD and the output horizontal synchronization signal formed by, for example, counting down the oscillation output clock pulse signal having the standard clock period of the crystal-controlled oscillator 3 using the counter 2 and lowering the frequency is determined. phase difference, i.e.
For example, the time difference representing the difference in timing of the same phase point, such as the rising edge of a horizontal synchronization signal, is determined using the period of the oscillation output clock pulse signal as a measure, and the count value representing the time difference is calculated over an appropriate period (for example, 100m).
sec to several seconds) and is supplied to the averager 4 so as to integrate the signal over several seconds. The oscillator 3 is crystal-controlled as described above to obtain good oscillation frequency stability, and its nominal oscillation frequency is selected to be an integral multiple of the frequency of the horizontal synchronizing signal.

Therefore, the above-mentioned count value representing the phase difference, that is, the time difference, between the input and output horizontal synchronizing signals obtained from the phase comparator 1 is calculated by the averager 4, as described above, from the minute frequency fluctuations of the crystal oscillator 3 in a short period of time. For example, calculate the average value by integrating over an appropriate period that removes the effects of Select a representative value, apply the representative value of the phase difference to the phase shifter 5, and shift the phase of the oscillation output clock pulse signal supplied from the oscillator 3 to the phase shifter 5 by an amount corresponding to the phase difference. , input horizontal sync signal
Extract as synchronous clock signal CK whose phase is synchronized with HD. Therefore, the synchronized clock signal CK obtained from the phase shifter 5 is different from the input horizontal synchronizing signal HD even though the crystal oscillator 3, which operates independently of the phase of the input horizontal synchronizing signal HD, is the primary oscillator.
A state that is phase-synchronized with the HD can be obtained,
Moreover, the phase synchronization effect by the phase shifter 5 is
There is no appreciable possibility of significant time delays such as those caused by conventional phase lock loops.

In fact, since the input horizontal synchronization signal HD is also generated from an original oscillator with oscillation frequency stability equal to or higher than that of the crystal controlled oscillator, the input and output horizontal synchronization signals that should be compared by the phase comparator 1 are The phase difference between the signals is not that large,
Normally, the phase difference in the oscillation output frequency of the oscillator 3 is within the range of about ±90 degrees, but even if a large phase difference exceeding ±90 degrees occurs, the above-mentioned principle structure will allow the input In order to obtain the synchronized clock signal CK that is phase-synchronized with the horizontal synchronization signal HD, it is necessary to make the dynamic range of the phase comparator 1 and the phase shifter 5 sufficiently wide. It is also recognized as difficult.

However, in the synchronous clock signal generator of the present invention, even when such a significantly large phase difference occurs, the same effect as described above with reference to FIG. 1 can be achieved without requiring the expansion of the dynamic range described above. In order to make this possible, the synchronous clock signal generator can be configured as shown in FIG. 2 by making some changes to the basic configuration shown in FIG.

That is, in the configuration example shown in the second figure, the first
A slip signal generating circuit 6 is added to the basic configuration shown and connected between the averager 4 and the counter 2, and the circuit operation is as follows.

In the configuration example shown in the second figure, similarly to the configuration shown in the first figure, the count value representing the phase difference, that is, the time difference, between the input and output horizontal synchronizing signals detected by the phase comparator 1 is averaged over an appropriate period. 4, and the time difference is an integral multiple of the clock period corresponding to the integer part of the value obtained by dividing the average value of the time difference obtained by the integration by the period of the oscillation output clock pulse signal of the oscillator 3, that is, the clock pulse signal. A value corresponding to the time difference of the integer part measured using the period as a measure is supplied to the slip signal generation circuit 6, and the clock period corresponding to the decimal part of the value obtained by dividing the average value by the period of the oscillation output clock pulse signal is also supplied. A value corresponding to a fractional time difference measured using the clock period as a measure is applied to the phase shifter 5 to shift the phase of the oscillation output clock pulse signal by that value. Therefore, regardless of the magnitude of the value obtained by integrating the phase difference (time difference) between the input and output horizontal synchronizing signals by the averager 4, the phase shifter 5 always adjusts the shift within ±180 degrees. You will only have to do the phase.

On the other hand, the slip signal generating circuit 6 does not operate unless the absolute value of the average value, which is the output signal of the averager 4, exceeds a predetermined set value, and the slip signal generating circuit 6 does not operate unless the absolute value of the average value, which is the output signal of the averager 4, exceeds a predetermined set value. (For example, when it exceeds the positive (+) side, the input horizontal sync signal HD
(assuming that the phase of the output horizontal synchronization signal is ahead of the output horizontal synchronization signal)
, temporarily stops counting for frequency step-down of the oscillation output clock pulse signal, waits for the elapse of the time corresponding to the time difference of an integral multiple of the clock cycle, restarts counting, and synchronizes the input/output clock pulse signal. Counter 2 is caused to slip until there is a slight time difference, less than a clock period, between the signals. Incidentally, at the same time as the counting slip of the counter 2 is performed, the slip signal is also applied to the averager 4, and its output signal is an average value (the output signal here refers to the average value of the averager 4 as shown in the first figure). By subtracting a count value corresponding to a time difference that is an integer multiple of the clock cycle from the average value corresponding to the reduction in the phase comparison output time difference due to the counting slip of the counter 2, the average value is immediately corrected. Note that the absolute value of the average value, which is the output signal of the averager 4, is minus (-) the predetermined set value.
When it is assumed that the phase of the output horizontal synchronization signal is delayed with respect to the input horizontal synchronization signal HD, in order to perform time difference correction of the opposite polarity to the above-mentioned plus (+) side time difference correction, counter 2
The counting operation is performed by adding a count value corresponding to a negative time difference that is an integer multiple of the clock period,
A count value corresponding to a time difference that is an integer multiple of the clock period is added to the average value that is the output signal of .

Note that since both the transmitting and receiving sides use an oscillator, such as a crystal controlled oscillator, that has an oscillation frequency stability that can be used as the primary oscillator for synchronizing signal generation, the counting slip of counter 2 as described above is used. To correct a large time difference, it is sufficient to make a correction of about one clock period per horizontal scanning period (1H), so the median of the counting operation period for frequency downshifting in counter 2 is set as (1H-1). ) If you set it to the clock period,
During normal operation when the phase difference between the input and output horizontal synchronizing signals is less than a clock period, the average value of the time difference mentioned above shifts to the plus (+) side by approximately one clock period, so the slip signal for one clock period is The signal is applied to the counter 2 and the averager 4, and when the phase difference between the input and output horizontal synchronizing signals is greater than or equal to ±1 clock cycle, two clock pulses are applied to the counter 2 and the averager 4. A slip signal for a period from 0 clock period to 0 clock period is applied to the counter 2 and averager 4 (when it is 0 clock period, no slip signal is actually generated), so that the input/output horizontal A large time difference between synchronization signals can be corrected by simply suspending the counting operation of counter 2 for a time corresponding to the large time difference, and subtracting the slip signal from the average value of the time difference. This can be achieved by circuit operation, and the circuit configuration for time difference correction is significantly simplified.

In the synchronous clock signal generator according to the present embodiment shown in FIG. 2, when the phase difference between the input and output horizontal synchronous signals exceeds one clock period, for example, 1.3
If an averaging time difference of one clock period occurs, the time difference of one clock period is corrected by the slip of the counting operation in the counter 2, and the time difference of 0.3 clock periods is corrected by the oscillation output clock pulse signal of the phase shifter 5. Corrected by a phase shift of . Therefore, the phase of the oscillation output clock pulse signal itself can always be corrected within a clock cycle, and even if there is a large time difference that is an integer multiple of the clock cycle, the counter 2 is immediately corrected when a shift of one clock cycle occurs. Since this can be corrected by the slip operation of the phase comparator 1, there is no need to significantly expand the dynamic range of the phase comparator 1. As described above, the reason why the slip signal is added (subtracted) to the averager 4 is to correct the average value corresponding to the reduction in the phase comparison output time difference due to the counting slip of the counter 2.

As is clear from the above description, according to the present invention, the following remarkable effects can be obtained when driving digital video equipment by generating a clock signal phase-synchronized with an input synchronizing signal. .

(1) Since a source oscillator with good oscillation frequency stability, such as a crystal controlled oscillator, can be used for clock signal generation, it is easy to maintain extremely good stability of the entire clock signal generation system.

(2) The integration time constant of the averager that calculates the average value of the time difference between input and output synchronization signals can be set to any value by configuring it with a digital circuit, and can be changed arbitrarily, making it possible to Lock-in characteristics can be arbitrarily and appropriately adjusted depending on the situation of the entire signal transmission system.

(3) It is easy to digitize the entire clock signal generation system, making it easier to stabilize the entire video signal transmission system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the basic configuration of an embodiment of the synchronous clock signal generator of the present invention.
FIG. 2 is a block diagram showing the configuration of another example. 1... Phase comparator, 2... Counter, 3... Oscillator, 4... Averager, 5... Phase shifter, 6... Slip signal generation circuit.

Claims (1)

[Claims] 1. A fixed frequency oscillator that oscillates at a frequency corresponding to a predetermined clock cycle, and an output with a frequency equal to the input synchronizing signal by counting and frequency-downgrading the oscillation output signal of the fixed frequency oscillator. a counter that forms a synchronization signal; a phase comparator that compares the phases of the output synchronization signal and the input synchronization signal to detect a phase difference; and an average value over a predetermined period of time difference corresponding to the phase difference. an averager that obtains the predetermined clock period as a measure; and an averager that obtains the predetermined clock period using the predetermined clock period as a measure; A synchronous clock signal generator comprising: a variable phase shifter that forms an output clock signal. 2 Forming a slip signal corresponding to a time difference corresponding to an integral multiple of the predetermined clock period among the average values of the time differences, and adding amounts and values corresponding to the corresponding time differences, respectively, according to the slip signal. or a slip signal generation circuit that slips the phase shift amount of the variable phase shifter and the count initial value of the counter by subtracting, respectively, the predetermined value obtained by subtracting the time difference corresponding to the slip signal from the average value of the time difference. 2. The synchronous clock signal generating device according to claim 1, wherein the amount of phase shift of said variable phase shifter is controlled in accordance with a time difference that is less than a clock period of said clock signal. 3. Synchronous clock signal generation according to claim 2, characterized in that the counting period of the oscillation output signal in the counter is set shorter than the period of the output synchronizing signal by a time equal to the predetermined clock period. Device.