JPS5673995A - Phase shift circuit - Google Patents

Phase shift circuit

Info

Publication number
JPS5673995A
JPS5673995A JP15105279A JP15105279A JPS5673995A JP S5673995 A JPS5673995 A JP S5673995A JP 15105279 A JP15105279 A JP 15105279A JP 15105279 A JP15105279 A JP 15105279A JP S5673995 A JPS5673995 A JP S5673995A
Authority
JP
Japan
Prior art keywords
frequency
signals
input signal
phase shift
gates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15105279A
Other languages
Japanese (ja)
Inventor
Mitsuo Chiba
Norio Meki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP15105279A priority Critical patent/JPS5673995A/en
Publication of JPS5673995A publication Critical patent/JPS5673995A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To lower the frequency of input signal and to reduce the power consumption, by outputting 4 signals every different 90 deg. in the phase in time sharing at phase shift circuit and performing a 90 deg. phase shift with a sum frequency output made by adding either one of the said signals. CONSTITUTION:An input signal 1 is frequency-divided into 4 at flip flops FF1, FF2, the 4 signals different in the phase by 90 deg. respectively are fed to four gates S1-S4 respectively, the gates S1-S4 are sequentially scanned with the ring counter 4, and the said four signals are added to a flip flop FF3 in time sharing. By multiplying the output of FF3 with either one of the said 4 frequency-division signals, the frequency 2 times the 4 frequency-divided signal, that is, a half the input signal frequency, can give the output signal 6 in 90 deg. phase shift at the switching of the gates S1-S4. Accordingly, in comparison with 1/4 frequency of input signal for the output signal conventionally, the input signal frequency is lowered and the power consumption is reduced.
JP15105279A 1979-11-20 1979-11-20 Phase shift circuit Pending JPS5673995A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15105279A JPS5673995A (en) 1979-11-20 1979-11-20 Phase shift circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15105279A JPS5673995A (en) 1979-11-20 1979-11-20 Phase shift circuit

Publications (1)

Publication Number Publication Date
JPS5673995A true JPS5673995A (en) 1981-06-19

Family

ID=15510240

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15105279A Pending JPS5673995A (en) 1979-11-20 1979-11-20 Phase shift circuit

Country Status (1)

Country Link
JP (1) JPS5673995A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0313117A (en) * 1989-06-12 1991-01-22 Nec Corp 90× phase difference generating integrated circuit device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0313117A (en) * 1989-06-12 1991-01-22 Nec Corp 90× phase difference generating integrated circuit device

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