JPH04162292A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To eliminate simultaneous selection of a word line, a bit line, etc., by processing a circuit so that two output signals of the same phase, reverse phase are not simultaneously output as H levels. CONSTITUTION:Inverters 1-3, P-channel MOSFETs 4, 5 and N-channel MOSFETs 6, 7 are provided corresponding to an input terminal 51, a same phase output terminal 52 and a reverse phase output terminal 53. If an input signal 101 is varied from an L level to an H level, a reverse phase output signal 106 is varied to the L level to be output previously at a predetermined time from when a same phase output signal 105 is varied to the H level. If the signal 101 is varied from the H level to the L level, the signal 106 is varied to the H level to be output by delaying by a predetermined time from when the signal 105 is varied to the L level. Thus, selection of a plurality of lines simultaneously is avoided in word lines and bit lines.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor memory device, and in particular to an address that receives one input signal and outputs two signals, one in phase and the other in phase with respect to the input signal. -Relates to a semiconductor memory device that functions as a buffer.

[Conventional technology]

Conventionally, this type of semiconductor memory device has an address buffer circuit including inverters 8 to 9, as shown in FIG. Correspondingly, from the output terminals 55 and 56, in-phase output signals 111 are respectively given a phase delay of four stages of inverters with respect to the input signal 107.
Then, an anti-phase output signal 112 with a phase delay of three stages of inverters is output. The timing charts of each signal in FIG. 2 are shown in FIGS. 4(a), (b), (
As shown in c), (d), (e) and (f).

[Problem to be solved by the invention]

In the semiconductor memory device described above that functions as a conventional address buffer circuit, the circuit configuration includes four stages of inverters in the case of the in-phase output signal 111, and the circuit configuration includes four stages of inverters in the case of the in-phase output signal 112. The circuit configuration includes three stages of inverters. For this reason, FIGS. 4(a), (b), (c), and (d).

(As is clear from the timing charts of each signal shown in e> and (f), when the input signal 107 changes from H level to L level, the reverse phase output signal 112 reaches H level slightly earlier. Then, since the in-phase output signal 111 becomes L level, the in-phase output signal Il
There is a time period (see time period * in FIGS. 4(e) and 4(f)) in which the output signal 112 and the negative phase output signal 112 are at the H level at the same time. Therefore, word lines and bit lines have a drawback in that a plurality of lines are selected simultaneously, causing data corruption in memory cells or access delays.

[Means to solve the problem]

The semiconductor memory device of the present invention receives one input signal, and
In a semiconductor memory device that outputs an in-phase output signal and an anti-phase output signal corresponding to the input signal in parallel, when the input signal changes from the L (LOW) level to the H (HIG) level, the The common mode output signal is L (LO
A predetermined time period Δt1 precedes the time when the W) level changes to the H (old G)f) level, and the reverse phase output signal changes from the H([Gl() level to the tOW>level and is output. , when the input signal changes from H (l(rG)I) level to L (L, 011) level, the in-phase output signal changes from H (old GH) level to L (LOW
) level, the negative phase output signal changes from L (LOIl) level to H level with a delay of a predetermined time Δt.
The device is configured to include a circuit that operates to change the level to (HIGH) and output it.

〔Example〕

Next, the present invention will be explained with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 3(a), (
b), (c), (d), (e) and (f) are timing charts of signals in this embodiment. As shown in FIG. 1, in this embodiment, inverters 1 to 3, P-channel MOSFETs 4 and 5,
N-channel MOSFETs 6 and 7.

In FIG. 1, when the input signal 101 input from the input terminal 51 is at the L level, FIG. 3(a),
As is clear from the timing charts of each signal shown in (b), (c), (d), (e), and (f), the signal 103 output from inverter 2 is at L level, and the signal 103 output from inverter 3 is at L level. Since the output signal 104 is at H level, N-channel MOSFET 7 is in the OFF state, and N-channel MOSFET 5 is in the ON state.
The situation is as follows. Therefore, P-channel MOSFET
The in-phase output signal 105 output through the P-channel MOSFET 6 is output at L level, and the negative phase output signal 106 output through P-channel MOSFET 6 is output at H level. Note that the in-phase output signal 1θ5 and the anti-phase output signal 106 are input to the gates of P-channel MOSFETs 6 and 4, respectively, and therefore, P-channel MOSFETs 4 and 6 are turned OFF and ON, respectively.
The situation is as follows.

Next, when the input signal 101 changes from the L level to the H level, the signal 103 output from the inverter 2 changes from the L level to the H level after a delay time of two inverter stages has elapsed.
The signal 10 that changes to the level and is output from the inverter 3
4, after the delay time of one inverter stage has elapsed, H
Changes from level to L level.

In response to the level changes of signals 103 and 104, N channel 40SFE 77 is turned on and N channel 1110sFET 5 is turned off. In this case, the current capacity of N channel gutter 03FET7 is changed to P channel M
By setting the current capacity to be larger than the current capacity of the OSFET 6, the negative phase output signal 106 is output as an L level signal. Also, N-channel MOSFET 5 is OF
Corresponding to the F state, when the L level negative phase output signal 106 is input to the gate of the P channel MOSFET 4, the in-phase output signal 105 changes from the L level to the H level and is output. That is, Tsunoda power signals 105 and 1
06 are never output as H level signals at the same time.

When the input signal 101 inputted from the input terminal 51 changes from the H level state to the L level state, FIGS. 3(a), (b), (c), (d), (e) and (f)
As shown in , since the signal 103 output from inverter 2 is initially at H level and the signal 104 output from inverter 3 is at L level, the N-channel MOSFET
7 is in the ON state, and the N-channel MOSFET
5 is in the OFF state. Therefore, as described above, the in-phase output signal 105 outputted via the P-channel 40SFE 74 is output at H level, and the anti-phase output signal 106 outputted via the P-channel 140sFET 6 is outputted at L level. is output.

Next, when the input signal 101 changes from the H level to the L level, the signal 103 output from the inverter 2 changes from the H level to the L level after a delay time of two inverter stages has elapsed, and is output from the inverter 3. signal 1
04, after the delay time of one stage of inverter has elapsed,
Changes from L level to H level.

Corresponding to the level changes of these signals 103 and 104, N-channel MOSFET 7 is turned off and N-channel MOSFET 5 is turned on. Even if the N-channel MOSFET 7 is in the OFF state, an H-level signal is output as the negative-phase output signal 106 until the in-phase output signal 105 input to the gate of the P-channel MOSFET 6 changes to L-level. There isn't.

On the other hand, since the N-channel 140sFET 5 is in the ON state, by setting the current capacity of the N-channel MOSFET 5 to be larger than the current capacity of the P-channel MOSFET 4, the common-mode output signal 105 is output as an L-level signal. Ru. As the common mode output signal 105 changes from H level to L level, the P channel MOS whose gate is inputted with this L level common mode output signal 105
The FET 6 is turned on, and the negative phase output signal 106 changes from L level to H level and is output. That is, the negative phase output signal 106 is not output as an H level until the in-phase output signal 105 is output as an L level signal, and the Okayama force signals 105 and 106 are
They are not simultaneously output as H level signals.

Therefore, the problem of multiple lines being selected at the same time, such as word lines and bit lines, is avoided.

〔Effect of the invention〕

As described above in detail, the present invention provides a semiconductor memory device including a circuit that outputs two signals of in-phase and anti-phase in response to one input signal. By performing circuit processing so that signals are not output as H level at the same time, it is possible to eliminate the problem of selecting word lines and bit lines at the same time, and to eliminate problems such as data corruption in memory cells and access delays. There is an effect.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of an embodiment of the present invention, Figure 2 is a circuit diagram of a conventional example, and Figures 3 (a), (b), (c), (d
), (e) and (f), and Fig. 4 (a), (b),
(c), (d), (e) and (f) are timing charts of each signal in the above embodiment and the conventional example, respectively. In the figure, 1 to 3.8 to 12...inverter, 4.5...P channel MOSFET, 6.7
...N-channel MOSFET.

Claims (1)

[Scope of Claims] A semiconductor memory device that receives one input signal and outputs in parallel an in-phase output signal and an anti-phase output signal corresponding to the input signal, wherein the input signal changes from an L (LOW) level to an H level. (HIGH)
When the in-phase output signal changes to L (L
A predetermined time period Δt_1 precedes the time point at which the level changes from OW) level to H (HIGH) level, the negative phase output signal changes from H (HIGH) level to L (LOW) level and is output, and the input signal changes from the H (HIGH) level to the L (LOW) level, the in-phase output signal changes from the H (HIGH) level to the L (LOW) level by a predetermined time Δt_2; The reverse phase output signal changes from L (LOW) level to H (HI) level.
What is claimed is: 1. A semiconductor memory device characterized by comprising a circuit that operates to change the output level to GH).