JPS62172595A - Storage device for semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To quicken the continuity read of memory information by providing a delay between the rising and falling of an X decoder output and forming a NOR gate circuit to apply preceding discharge of a bit line to a GND level. CONSTITUTION:An output of an X decoder circuit 11 to a word line 12 is connected to each gate electrode of a transistor (Tr) 13 and a memory Tr 6. A prescribed delay is provided between the rising and falling of the output of the circuit 11 and the NOR gate input circuit inputting an output of the circuit 11 is formed. Every time an output N of the NOR gate circuit generates a one-shot pulse at each address switching, the Tr 16 is discharged to the GND level when the pulse is in a high level. Since the Tr 16 is connected in parallel with the Tr 6, the bit line 7 is discharged to the GND level preceding by the pulse period. Thus, the read access time of the memory information continuity is quickened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit memory device.

[Conventional technology]

FIG. 3 is a block diagram showing an example of the configuration of a conventional semiconductor integrated circuit storage device.

When an arbitrary address is selected by the signal A o "-An input from the address input terminal 1 to the address input circuit 2, a predetermined memory transistor 6 is selected by the X decoder circuit 3 and the Y decoder circuit 4, and the memory transistor 6 is output from the output terminal 10 via the sense amplifier circuit 8 and the output circuit 9. Here, the memory information specifically refers to whether the selected memory transistor 6 becomes "conductive" or not. In terms of whether it is "non-conductive", "conductive" and "non-conductive" correspond to memory information '1' and '''0'', respectively.

That is, the output X from the X decoder circuit 3 is connected to the gate electrode of the memory transistor 6, and this output line forms the word line 5. The memory transistor 6 has its source side grounded to the GND terminal, and its drain side connected to the Y decoder circuit 4 through the bit line 7.

The time from when an input is set to address input terminal 1 to when an output is output from output terminal 10 is the address access time, but in general, the access time for memory information "conduction" is the access time for "non-conduction°". This is because the transistor width of the memory transistor 6 is quite narrow in order to reduce the overall chip size.
Release of bit line to GND level due to “conduction”
t, takes a long time due to the time constant of the bit line resistance and parasitic capacitance, whereas the detection of memory information "non-continuity" does not require discharging to the GND level and is relatively fast within the sense amplifier circuit 8. This is because it is fast because it takes only charging time.

Note that a general semiconductor integrated circuit has a control terminal and a control circuit, and this control circuit is configured to control the entire integrated circuit, but since it is not particularly necessary for explaining the present invention, it is omitted. be.

[Problem that the invention seeks to solve]

In conventional semiconductor integrated circuit storage devices, as described above, the read access time when memory information is "conductive" is determined by the time constant of the bit line wiring resistance and bit line capacitance when the bit line is connected to GND through the narrow transistor width of the memory transistor. Since the terminal is discharged, there is a drawback that the read access time is slower than the "non-conducting" read access time, which does not require this.

This invention was made in order to improve the above-mentioned problems, and aims to obtain a semiconductor integrated circuit storage device with improved total access time by speeding up the access time for reading "conduction" of memory information. purpose.

[Means for solving problems]

The semiconductor integrated circuit storage device according to the present invention provides a certain delay between the falling and rising edges of the X-decoder output output to the word line, and forms a NOR gate input circuit that receives the X-decoder output as an input. The output terminal is connected to the gate of a transistor connected in parallel with the bit line.

[Effect]

Due to the action of the X decoder, a one-shot pulse is outputted by the 9 NOR circuit only at the time of address switching, and the bit line is pre-discharged to the GND level by this pulse, thereby speeding up the "conduction" read.

〔Example〕

An embodiment of this invention will be described below. In Figure 1,
The address signal received from the address input terminal 1 is passed through the address input circuit 2 to the X decoder circuit 11 or
It enters the Y decoder circuit 4.

Output X from X decoder circuit 11 to word line 12
s to Xm are connected to each gate electrode of m transistors 13 and to each gate electrode of m memory transistors 6. Each source side of the m transistors 13 is connected to GN
The drains are connected to the D terminal to form a common drain, and a NOR circuit with m inputs is formed using the depletion Y-type transistor 14 as a load transistor. 15 is a VCCt source terminal of the NOR circuit. This N
The output N of the OR circuit is connected to the gate electrode of the transistor 16, the source side of the transistor 16 is connected to the GND terminal, and the drain flltl is connected to the m memory cells 2.
The Y decoder circuit 4, sense amplifier circuit 8, output circuit 9, and output terminal 10 connected to the bit line 7 are connected to the third
This is similar to that shown for the conventional example in the figure.

Next, the operation will be explained. The X decoder circuit 11 has a special circuit design for the present invention. In other words, the fall of the X decoder output is a sudden fall at 9, as shown in the timing shown in FIG. It is designed.

m input NOs that receive m outputs from the X decoder with the above characteristics
The output N of the R circuit changes to the second output every time the address input changes.
The drain of the transistor 16, which generates a one-shot pulse as shown in FIG. 3(e) and has the pulse as its gate input, is discharged to the GND level only during the "H" level of the pulse. Since the drain of this transistor 16 is connected in parallel with the bit line of the memory transistor 6, the bit line is eventually discharged every time the address input is switched, so the address access time for reading memory information "conduction" is reduced. It will be faster.

In the embodiment described above, the one-shot pulse m
Although a depletion type transistor is used as the load of the input NOR circuit, a resistive load, an engineering type transistor, or a P-channel type transistor can have the same effect as long as the NOR circuit is formed.

In addition, in the above-described embodiment, the bit line is discharged to the GND level in advance only during the one-shot pulse, but the level at which the bit line is discharged only during the one-shot pulse is GN.
It is not limited to the D level, but may be any other suitable level that facilitates speeding up the Y decoder circuit 4 and sense amplifier circuit 8.

〔Effect of the invention〕

As described above, according to the present invention, a delay is provided between the fall and rise of the output of the X decoder, a NOR gate circuit is created using the delayed word line output as an input gate, and Since the circuit is configured to discharge the bit line of the output memory transistor to the GND level or another appropriate level in advance when reading, the read access time for memory information conduction can be increased. Moreover, according to this circuit configuration, the increase in chip area can be extremely small, and furthermore, according to this configuration, N
Due to the positional relationship between the OR gate transistor and the memory transistor, there is an advantage that the speed of the slowest memory transistor can be preferentially increased due to the 1M resistance and capacitance of the word line.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a timing chart for explaining its operation. FIG. 3 is a block diagram showing a conventional example. 4...Y decoder circuit, 6...memory transistor, 7...bit line, 11...X decoder circuit, 12...word line, 13...e/NO
Driver transistor of R circuit.

Claims (1)

[Claims] In a semiconductor integrated circuit memory device in which a memory element is arranged at the intersection of a word line and a bit line, a certain delay is provided between the fall and rise of the X decoder output output to the word line, and A semiconductor integrated circuit memory device comprising a NOR gate input circuit which receives a decoder output as an input, and an output terminal of the NOR gate circuit connected to a gate of a transistor connected in parallel with the bit line.