JPS6050795A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the variation width of an output signal and shorten the delay time of the signal, and reduce a through current which is flowed through an output circuit by approximating the level of the output node of a push-pull type output stage to a potential between a source voltage at a high impedance state and the ground and generating a proper output control signal. CONSTITUTION:When address signals Axi and Ayi vary and that is detected to vary an output control signal to a high level, the outputs of NOR gate circuits G1 and G2 are fixed at a low level regardless of readout signals (a) and (a'). The node n1 enters a high impedance state. When the output control signal Cp varies from the high level to the low level right before the next readout signals (a) and (a') are inputted to the output circuit 6, the output stage 6a has transition from a state wherein the node n1 is set at an intermediate level to a lowimpedance output state, and the readout signals (a) and (a') are inputted. Consequently, this output circuit 6 increases the variation speed of the output signal and shorten the delay time of the signal to improve the time of access to a memory.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to semiconductor integrated circuit technology, and, for example, to a technology that is effective when used in the configuration of an output circuit in a semiconductor integrated circuit.

[Background technology]

As shown in FIG. 1, the output circuit in a semiconductor memory device is a tri-type circuit consisting of two insulated gate field effect transistors (hereinafter referred to as MO8FET) Q, Q, connected in series between the power supply voltage VCC and the ground. We considered a push-pull type circuit that can obtain the state at any time. That is, in this output circuit, when the signal a is high level and the signal a is low level, MO8FETQs is on + Qt is off, and the output is high level (from power supply voltage VCC to MO8FE
Threshold voltage of TQ1 ■Level after subtracting th VCC
Vth), and when signal a is low level and signal a is high level, MO8FETQ is off, and Q! is turned on and the output becomes low level (0■).

Furthermore, when both signals a and b are set to low level, M
OS FET Q* and Q! is turned off and the output is placed in high impedance. In this output circuit, when the output is changed due to changes in the signals a and b, the output signal ■. As shown in FIG. 2, ut is changed from a high level to a low level, and from a leakage level to a high level level. Therefore, if the switching speed of MO8FETQ*-Qt is sufficiently fast, the signal delay time is so small that it does not become a problem.

In a memory with a 1-bit output, only one output circuit is required, so the MOS F that makes up this
The switching speed can be increased by increasing the constants of E T Qr and Qt. However, when the above output circuit is applied to a multi-bit type memory configured to output read signals of multiple pits in parallel,
Since a plurality of output circuits are required, the constants of the MOSFETs constituting each output circuit cannot be increased due to current consumption limitations. Therefore, the switching speed of each MO8FET becomes slow, and the rise and fall of the output signal becomes slow, resulting in a long signal propagation delay time in the output circuit, which causes a delay in access time in the memory. That's what I found out.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor integrated circuit technology that provides remarkable effects not seen in the past.

Another object of the present invention is to shorten the time required for an output signal to change, thereby reducing delay time, when applied to an output circuit of a semiconductor integrated circuit, for example.

Still another object of the present invention is to reduce the through current in the output circuit, thereby reducing the generation of noise on the power supply voltage.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the present invention provides means for bringing the level of the output node of the push-pull output stage close to the potential between the power supply voltage and ground in a zero impedance state, and also forms an appropriate output control signal. By using this output control signal to fix the output node to a potential between the low level and the low level immediately before output,
The present invention achieves the above-mentioned objects of reducing the change width of the output signal, thereby shortening the signal delay time, and also reducing the through current flowing through the output circuit.

The present invention will be specifically explained below using the drawings.

〔Example〕

FIG. 3 shows an embodiment in which the present invention is applied to an output circuit of a semiconductor memory device such as a static RAM (random access memory).

In the figure, 1 is a memory array in which a plurality of memory cells are arranged in an IJ sock shape, and 2 is a memory array in which a plurality of memory cells are arranged in an IJ sock shape, and 2 is a
This is an X decoder that sets one corresponding word line in memory array 1 to a selection level.

3 is a Y-type address signal person also supplied from the outside,
. ~A, 1, one set of column switches provided on one side of the memory array 1 for connecting internal complementary data line pairs to common data lines CD, CD is turned on to generate address signals A, 1. ~ A, a pair of complementary data lines corresponding to i are common data lines CD.

This is an X decoder connected to a CD.

Although not particularly limited, in this embodiment, eight pairs of the common data lines CD and CD are provided, and when the selection signal output from the X decoder 3 is supplied to the column switch circuit 4, the corresponding When the column switches of the set are turned on, the eight pairs of complementary data lines in the memory array 1 are connected to the eight pairs of common data lines CD, CD.

Each of the common data lines CD and CD is connected to a sense amplifier 5, and the sense amplifier 5 amplifies the level difference between the common data lines CD and CD to read data. There is.

Then, the output signal of this sense amplifier 5 (read? Jj L
Signals a and T are supplied to the output circuit 6, and output signals at an appropriate level are output from the output terminal 7. ut is output to the outside.

The output circuit 6 includes, for example, a pair of NOR circuits in which read signals a, a from the sense amplifier 5 are supplied to one input terminal, and an appropriate output control signal CP is supplied to the other input terminal. The gate circuits G+ and Gt are connected in series between the power supply voltage VCC and the ground.
R gate circuit G.

Two MOSs that are turned on and off by the output of Gt
A push-pull type output stage 6a consisting of FETQ+ and Qt, and this switch MO8I;'ETQ.

And Q! voltage setting circuit 6b connected to the connection node n of
It is composed of. The voltage setting circuit 6b connects the power supply voltage VCC and the node n of the output stage 6a.

MOS F B T Qs connected in series between
Q4, and MO8FBTQw and Qs connected in series between node n1 and ground. The gates and drains of the MOS PET Qs and Qs are connected to each other and act as a kind of giode. Furthermore, the above output control signal CP is applied to the gate terminals of MOS FET Q4 and Qs,
It is turned on and off by an output control signal CP. Although not shown, a write circuit is connected to each of the common data lines CD and CD, and data is written into a memory cell selected by an externally supplied data X and Y decoder.

Further, in this embodiment, the output control signal CP supplied to the output circuit 6 is an address signal A supplied from the outside.
It is formed in a signal forming circuit 9 based on a detection signal from an address change detecting circuit 8 that detects changes in xi, A, and i.

In this signal forming circuit 9, in addition to the output control signal CP, a timing signal for operating the X decoder 2 and the φ8. φ, or a precharge signal φ to a precharge circuit 10 that precharges a data line immediately before turning on a column switch provided on one side of the memory array 1.
. Alternatively, an equalization signal or the like is generated to bring each data line pair or common data line pair in the memory array 1 to the same potential at appropriate timing to increase the read speed.

The potential of the output control signal CP is as shown in FIG.
It rises to a high level approximately in synchronization with a change in the address signal AxiIA, i, and falls to a low level immediately before a change in the read signals a, a.

In this case, the output control signal CP rises by detecting the change in the address signal Axi t Ayi as described above. On the other hand, the fall of the output control signal CP may be synchronized with the changes in the read signals a and a by providing a circuit that detects changes in the levels of the common data lines CD and CD. In the formation circuit 9, the reference clock signal or the like may be frequency-divided so that the signal falls after an appropriate period of time has elapsed after rising. Or signal forming circuit 9
In this case, if an appropriate timing signal for operating the sense amplifier 5 is generated, the output control signal CP may fall in synchronization with the timing signal.

Next, the operation of the output circuit 60 controlled by the output control signal CP as described above will be explained. In the table, although not particularly limited, the above MO8FETQ+-Qa
will be explained below assuming that it is formed into an N-channel type.

When the output control signal CP is set to low level, N
The OR gate circuits G+ and Gt act as inverters, and when the read signal a is at a high level, MO8FETQ is turned off, MO8FETQ is turned on, and the node n1 is brought to a low level. Conversely, when read signal a is low level, MO8F
ETQ is turned on, Q is turned off, and the node n of the output stage 6a
, is set to high level. Also, at this time, MO8FBTQ4 and Q are controlled by the low level output control signal CP.

Because it is cut off! The pressure setting circuit 6b has no effect on the node nl, and the output terminal 7 receives an output signal having a phase opposite to that of the readout signal 8. ut is output.

When the address signals AxI and Ayi are changed and this is detected and the output control signal CP is changed to high level, the output of the NOR gate circuit G+-Gy becomes low level regardless of the read signals a and a. Fixed. Therefore, both MO8FETs Q+ and Qt of the output stage 6a are turned off, and the node n is placed in a high impedance state. However, when the output control signal CP becomes high level,
Switches MO8FFiTQ and Q in the voltage setting circuit 6b
Since node s is turned on, node n is charged up or down and connected to power supply voltage VCC and ground (
0■), and is fixed at a level approximately midway between the two.

Therefore, when the output control signal CP is changed from high level to low level immediately before the next read signals a and a enter the output circuit 6, the output stage 6a changes from the state where the node n is set to the intermediate level. It shifts to a low impedance output state, and then read signals a and a start to come in. Therefore, the output signal is ut is always changed from an intermediate level between the output high level and low level to high or low level. As a result, in this output circuit 6, the output signal changes quickly, the i-th delay time is shortened, and the memory access time is improved.

Moreover, since the output signal changes faster, the through current flowing through the output stage 6a (the current flowing as the load capacitance is charged and discharged) is reduced accordingly. Therefore, within the range of current consumption allowed for the output circuit, MO8FE of the output stage 6a
The switching speed can be increased by setting large constants for TQ and Q.

In the absence of the voltage setting circuit 6b, if multiple output circuits are provided to make the memory a multi-bit output, the constants of MO8FETQ+ and Q must be set small due to current consumption limitations, and therefore the signal Although the delay time increases, according to the above embodiment, even if the output is multi-bit, it is not necessary to make the constant of MO8FET Qt: Qt very small, so the signal delay can be reduced.

Further, in the above embodiment, the MOSFET Qs and Q provided in the voltage setting circuit 6b are connected to the switches MO8FETQ4 and Q by the output control signal CP.
When MO8FBTQ is turned on, it acts as a current limiter to suppress the through current flowing through the circuit, and also acts as a type of diode, so that the drain side voltage of MO8FBTQ is lower than the power supply voltage VCC and reaches the threshold of MO8FETQs. The voltage on the source side of MO8FETQ6 should be kept at the ground level (
OV) and υ should not fall below a potential that is higher by the threshold voltage of MO8FETQa. As a result, the node n of the output stage 6a in the high impedance state,
Limit the upper and lower limits of the potential of
It can be fixed at a level intermediate between cc and ground.

In other words, if MOS F B T Qs and Q6 are not present, node n is set to a potential determined by the ratio of on-resistances of MO8FETs Q4 and Q.
Depending on the variation in the constants of ETQ4 and Q, the potential of node n may be fixed to a higher or lower value, but MO8FETQs and Q.

By clamping the potential across MO8FETs Q+ and Q, the variation range of the potential at node n can be narrowed and fixed at approximately an intermediate level. However, MO8FETQ4 and QI
Depending on the constant of l and other conditions, MO8FETQ
s and Q6 can also be omitted.

The constants of the switches MO8FHTQ4 and Qll are set in advance according to the size of the load capacitance connected to the output terminal 7, but the constants of the switches MO8FHTQ4 and Qll are
There is no need to provide load driving capability like 8FETQI and Q, and it is sufficient to charge up or charge down node n1 over a relatively long period of time and fix the level to an intermediate level, so the constants of MO8FBTQa and Q are small. (For example, less than 1/10 of the constant of Q,,Q,)
Therefore, the through current passed to the voltage setting circuit 6b is considerably smaller than the through current flowing to the output stage 6a when the output changes, and even if the voltage setting circuit 6b is provided, the current consumption will not increase that much. do not have.

Further, the voltage setting circuit 6b in the above embodiment is replaced with a diode-connected MOSFET and a switch MO8FE between the node n and one of the power supply voltages VCC or the ground.
It is also possible to configure only one side with T provided, so that only the change of the output signal to the high level side or the low level side is made faster.

In other words, if for some reason the rise of the output signal is found to be much slower than the fall, the voltage at node n1 and the power supply voltage ■. MO8FBTQs diode-connected only between 0 and switch MO8F B
T Q 4 is provided to change the level of the node n immediately before the change in the output signal f) from the power supply voltage ■cc of the MO8FET.
By changing the output while keeping the potential close to a potential lower by the threshold voltage of Qs, the rise of the output signal can be made faster. Similarly, it is also possible to increase only the falling speed of the output signal.

Furthermore, instead of providing the voltage setting circuit 6b in the above embodiment, the output node n of the output stage 6a.

are directly connected to the output terminal 7, and as shown in Fig. 5, resistors R6 and R7 are externally connected between the output terminal 7 and the power supply voltage ■cc and the ground, respectively.
The output terminal 70 is set to an intermediate potential determined by the resistance ratio of 7.
The level may be fixed immediately before the output signal changes.

However, as multiple output circuits are provided to make the output multi-bit, each MO8FETQ+ of the output stage 6a,
The smaller the Qt constant is set, the higher the output signal level ■. H
Or ■. Since the load condition of the output terminal becomes severe due to the relationship with The output node of can be quickly brought closer to the intermediate level.

〔effect〕

The output node of the output stage is connected between the power supply voltage and ground in a high impedance state to an output circuit consisting of a push-pull type output stage and a gate circuit for controlling this output stage to achieve a tri-state state. In addition to providing a left-hand means to bring the potential close to the potential of As a result, the delay time of a signal whose output signal changes quickly is reduced, and the through current in the output stage is also reduced.

As a result, when applied to a multi-bit output type memory, for example, it is possible to reduce the signal delay time in each output circuit and improve the access time, that is, the data read speed, and the through-current in each output stage. This has the effect of reducing the noise generated in the power supply voltage.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

For example, it is possible to use another gate circuit of the NAND gate instead of the N0I gate circuit in the above embodiment.

[Application field]

The above explanation will mainly focus on the static RAM, which is the field of application that was the background of the invention made by the present inventor.
Although the description has been made regarding the output circuit of a semiconductor memory device, the present invention is not limited thereto, and can be applied not only to semiconductor memory devices such as dynamic RAM and ROM, but also to output circuits of microcomputers and the like.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an example of the configuration of an output circuit in a semiconductor integrated circuit, Fig. 2 is a waveform diagram showing changes in the output signal in the output circuit, and Fig. 3 is an example of the case where the present invention is applied to a static RAM. FIG. 4 is a circuit diagram showing the embodiment. FIG. 4 is a timing chart showing the timing of each signal in the embodiment. FIG. 5 is a circuit diagram showing another embodiment of the present invention. 1...Memory array, 5...Sense amplifier, 6...
- Output circuit, 6a... Output stage, 6b... Voltage setting circuit, 7... Output terminal, G5. G,...Gate circuit (
NOR gate circuit), Q, -Q, ... MOSFET,
CPo,. Output control signal.

Claims (1)

[Claims] 1. A pair of gate circuits operated by an appropriate output control signal, connected in series between a first power supply voltage and a second power supply voltage of the circuit, and an output signal of the gate circuit; and a pair of transistors each driven by a pair of transistors, and the potential of the connection node of the pair of transistors is fixed at an intermediate level of the output based on the output control signal immediately before output. Semiconductor integrated circuit. 2. The semiconductor integrated circuit according to claim 1, wherein a voltage setting circuit operated by the output control signal is connected to the connection node of the pair of transistors. 3. A semiconductor integrated circuit, wherein the output control signal is formed based on a signal from a circuit that detects a change in address in a semiconductor memory device.