JPS57114946A - Microprogram controller - Google Patents

Microprogram controller

Info

Publication number
JPS57114946A
JPS57114946A JP34381A JP34381A JPS57114946A JP S57114946 A JPS57114946 A JP S57114946A JP 34381 A JP34381 A JP 34381A JP 34381 A JP34381 A JP 34381A JP S57114946 A JPS57114946 A JP S57114946A
Authority
JP
Japan
Prior art keywords
signal
suppression
flag
register
field
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP34381A
Other languages
Japanese (ja)
Inventor
Ryoichi Takamatsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP34381A priority Critical patent/JPS57114946A/en
Publication of JPS57114946A publication Critical patent/JPS57114946A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
    • G06F9/262—Arrangements for next microinstruction selection

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To speed up the processing, by providing a combined logical circuit taking a specific field of micro-code and an external condition signal as the input signal and outputting a suppression signal once. CONSTITUTION:A micro-code read out from a control memory 2 is stored in a register 3, and fields D1, D2 are decoded 5, 6 and output a control signal 10. A flag F representing branch condition of the register 3, field CC and external condition signal m are inputted to a combined logical circuit 11. When a flag F is at 1 and the field CC represents m=1, if the signal m is at 1, a suppression signal 17 is on-state and an A register set signal 13 of the output of a suppression gate 12 is suppressed. When the flag F is at 0, operation is made so that the suppression signal is always off. Thus, even if two operations are operated by one step at the branch condition, the number of steps can be reduced without interference to the operation of other branches, allowing to speed up the processing.
JP34381A 1981-01-07 1981-01-07 Microprogram controller Pending JPS57114946A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP34381A JPS57114946A (en) 1981-01-07 1981-01-07 Microprogram controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP34381A JPS57114946A (en) 1981-01-07 1981-01-07 Microprogram controller

Publications (1)

Publication Number Publication Date
JPS57114946A true JPS57114946A (en) 1982-07-17

Family

ID=11471217

Family Applications (1)

Application Number Title Priority Date Filing Date
JP34381A Pending JPS57114946A (en) 1981-01-07 1981-01-07 Microprogram controller

Country Status (1)

Country Link
JP (1) JPS57114946A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59188745A (en) * 1983-04-08 1984-10-26 Nec Corp Exception detecting system
JPS60238932A (en) * 1984-05-11 1985-11-27 Nec Corp Data processor
KR20170135838A (en) * 2015-04-10 2017-12-08 후지 테콤 가부시키가이샤 Linking mechanism between water meter and water leak determining unit, and water leak determining unit employing said linking mechanism

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59188745A (en) * 1983-04-08 1984-10-26 Nec Corp Exception detecting system
JPH0441377B2 (en) * 1983-04-08 1992-07-08 Nippon Electric Co
JPS60238932A (en) * 1984-05-11 1985-11-27 Nec Corp Data processor
KR20170135838A (en) * 2015-04-10 2017-12-08 후지 테콤 가부시키가이샤 Linking mechanism between water meter and water leak determining unit, and water leak determining unit employing said linking mechanism

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