JPS54141975A - Sequence control unit - Google Patents

Sequence control unit

Info

Publication number
JPS54141975A
JPS54141975A JP4879578A JP4879578A JPS54141975A JP S54141975 A JPS54141975 A JP S54141975A JP 4879578 A JP4879578 A JP 4879578A JP 4879578 A JP4879578 A JP 4879578A JP S54141975 A JPS54141975 A JP S54141975A
Authority
JP
Japan
Prior art keywords
output
circuit
input
bit
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4879578A
Other languages
Japanese (ja)
Other versions
JPS6010642B2 (en
Inventor
Yutaka Aoyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP4879578A priority Critical patent/JPS6010642B2/en
Publication of JPS54141975A publication Critical patent/JPS54141975A/en
Publication of JPS6010642B2 publication Critical patent/JPS6010642B2/en
Expired legal-status Critical Current

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  • Programmable Controllers (AREA)

Abstract

PURPOSE:To execute either of conditional and sequential systems easily by providing a sequential function to the multiple-input-output and multiple-output arithmetic circuit. CONSTITUTION:When the instruction interpreter 12 interprets a step control instruction, an output is produced in the circuit i, when the output condition of arithmetic register 11 is significant, that is when the set condition of multiple-input- output holding circuit holds, the AND circuit 14 produces an outpu ''1''. When the bit location address interpreter 15 interprets the bit location address signal g of instruction, only the output of the K-th bit of interpret-output K is made ''1''. When the output j of AND circuit 14 is ''1'', the AND gates 17-1 to 17-8 are closed, data outputs of the input-output register 10 are inhibited, a data in which only the K-th bit is ''1'' and other bits are all ''0'' is taken out as the data output e through the OR gates 18-1 to 18-8.
JP4879578A 1978-04-26 1978-04-26 Sequence control device Expired JPS6010642B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4879578A JPS6010642B2 (en) 1978-04-26 1978-04-26 Sequence control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4879578A JPS6010642B2 (en) 1978-04-26 1978-04-26 Sequence control device

Publications (2)

Publication Number Publication Date
JPS54141975A true JPS54141975A (en) 1979-11-05
JPS6010642B2 JPS6010642B2 (en) 1985-03-19

Family

ID=12813158

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4879578A Expired JPS6010642B2 (en) 1978-04-26 1978-04-26 Sequence control device

Country Status (1)

Country Link
JP (1) JPS6010642B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH048905Y2 (en) * 1985-07-23 1992-03-05

Also Published As

Publication number Publication date
JPS6010642B2 (en) 1985-03-19

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