JPS5532232A - Rom check system - Google Patents

Rom check system

Info

Publication number
JPS5532232A
JPS5532232A JP10367778A JP10367778A JPS5532232A JP S5532232 A JPS5532232 A JP S5532232A JP 10367778 A JP10367778 A JP 10367778A JP 10367778 A JP10367778 A JP 10367778A JP S5532232 A JPS5532232 A JP S5532232A
Authority
JP
Japan
Prior art keywords
rom
address
check
output
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10367778A
Other languages
Japanese (ja)
Other versions
JPS6052450B2 (en
Inventor
Tomohiro Shimizu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP53103677A priority Critical patent/JPS6052450B2/en
Publication of JPS5532232A publication Critical patent/JPS5532232A/en
Publication of JPS6052450B2 publication Critical patent/JPS6052450B2/en
Expired legal-status Critical Current

Links

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Read Only Memory (AREA)

Abstract

PURPOSE: To make a ROM check easily and definitely by checking the output of ROM by continuously assigning addresses of ROM corresponding to external fixed check signals and next-address signals outputted by ROM.
CONSTITUTION: When a control signal is supplied to terminl I0 of next-address control part 10 attached to LSI1, AND gates 16 to 20 and the output-side AND gate of RAM 3 are all closed. Next, applying a fixed bit signal to terminals I1 to I5 of control part 10 stores the bit signal in register 21 via NAND gate 15 and ROM address part 5 selects line (l1) to check various outputs generated by ROM2 by the check circuit via the output-side AND gate. Simultaneously, next-address signal NA outputted by ROM 2 is applied to gates 12 to 15 together with next selective signals applied to terminals I1 to I5, so that line O2 will be selected in the same way. Addresses are continuously assigned in sequence, so that ROM will be checked easily and definitely.
COPYRIGHT: (C)1980,JPO&Japio
JP53103677A 1978-08-25 1978-08-25 ROM check method Expired JPS6052450B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53103677A JPS6052450B2 (en) 1978-08-25 1978-08-25 ROM check method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53103677A JPS6052450B2 (en) 1978-08-25 1978-08-25 ROM check method

Publications (2)

Publication Number Publication Date
JPS5532232A true JPS5532232A (en) 1980-03-06
JPS6052450B2 JPS6052450B2 (en) 1985-11-19

Family

ID=14360411

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53103677A Expired JPS6052450B2 (en) 1978-08-25 1978-08-25 ROM check method

Country Status (1)

Country Link
JP (1) JPS6052450B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7468202B2 (en) * 2002-05-30 2008-12-23 Ngk Insulators, Ltd. Honeycomb structural body

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7468202B2 (en) * 2002-05-30 2008-12-23 Ngk Insulators, Ltd. Honeycomb structural body

Also Published As

Publication number Publication date
JPS6052450B2 (en) 1985-11-19

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