JPS6052450B2 - ROM check method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an RO that checks the function of a read-only memory (ROM) built into a large-scale integrated circuit (LSI).
Regarding the M check method.

Small electronic calculators and the like are generally equipped with a ROM for storing microinstructions, and arithmetic processing is executed based on the output of this ROM.

However, when various circuits including this ROM are integrated into an LSI, most malfunctions occur in the ROM section, and it is necessary to check this ROM.
A method has been used in which predetermined arithmetic processing is executed based on the output signal of the controller, and the results are determined. However, such a checking method requires a lot of time to execute various pre-programmed operations, and
There was a flaw in the lack of sufficient accuracy checks.
In addition to the method described above, there is also a method to check the ROM, in which the address of the ROM is automatically advanced and R
Although there is a method of checking the signal output from the OM, in that case, the next address signal output from the ROM cannot be checked, and therefore it is impossible to check with sufficient accuracy. The present invention has been made in view of the above points, and
A predetermined test signal is input from outside the LSI to the next address signal output from the ROM, and the ROM address is continuously advanced according to both signals.
It is an object of the present invention to provide a ROM check method that can check all ROM outputs including the next address signal by checking the output signal of the address signal.

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, numeral 1 indicates a central processing circuit (CPU) of a small electronic computer, which is composed of one chip of LSI.

A ROM 2, a random access memory (RAM) 3, an arithmetic processing circuit (ALU) 4, and the like are provided within the CPUI. The ROM 2 stores various microinstructions in a fixed manner, and sends an address designation signal AD for addressing the RAM 3 to the ALU 4 via a line a, corresponding to an address designated by the ROM address section 5. A code signal CODE and various control signals INS are outputted via lines b and c, respectively, and a next address signal NA is outputted via line d. In this embodiment, in order to simplify the explanation, the next address signal NA will be explained as having 5 bits. RAM3 and A
LU4 is the above address designation signal ADl code signal CO
Using the DE1 control signal 1NS and the like, predetermined arithmetic processing is executed and stored, and the data is transferred to and displayed on a display section (not shown). Further, the address designation signal outputted through the line a is transmitted through the AND circuit 6 to the output terminals 01 to 012, and the code signal CODE outputted through the line b is transmitted through the AND circuit 7 to the output terminals 01 to 012.
The control signal 1NS output from line c from 3 to 016 is sent to output terminals 017 to 020 via AND circuit 8.
is output by Note that the above AND circuits 6 to 8 are controlled to open or open by a control signal inputted from the input terminal. The signals output from the output terminals 01 to 020 are input to a check circuit 9 connected to the outside and inspected. This check circuit 9 is configured to have an expected output installed in advance and automatically judge it by comparing it with the actual output, or print the transferred ROM2 output and make a judgment based on it. has been done. The next address signal NA output via line d is applied to one input terminal of exclusive OR circuits 11 to 15 in next address signal control section 10. The other input terminals of the exclusive OR circuits 11 to 15 are connected to the input terminals 11 through AND circuits 16 to 20 whose openings are controlled by the control signals. The control signals are inputted with weights of 1, 2, 4, 8, and 16. The negative outputs of the exclusive OR circuits 11 to 15 are then read into the address register 21 by ROMA in the control signal. The output of this address register 21 is input to the ROM address section 5, the corresponding address line is selected, and various signals are outputted from the ROM 2. FIG. 2 is a diagram showing the main parts of FIG. 1 in detail.

That is, the output of the address register 21 is input to the ROM address section 5 with weightings of 1, 2, 4, 8, 16, and predetermined address lines 11, 12, . . .
Select. Then, according to the selected address line, the predetermined address designation signal AD (6 bits for designating first register F, 6 bits for designating second register S, 6 bits for designating second register S, total 12 bits) and code are output from ROM 2 as described above. Signal CODE (4 bits), instruction signal INS (4 bits) and next address signal NA (
5 bits). Next, the operation of the present invention configured as described above will be explained.

When checking the output of the ROM 2, control signals are input from the input terminals to AND circuits 6 to 8 and AND circuits 16 to 20, respectively, and the respective gates are opened. And first,
In order to select the address line 11, input terminals 11~
A signal J (1, 0, 0, 0, 0) is input from 15. (Hereafter, when writing data, 1, 2, 4 from the left,
This is done with weighting of 8... ) Note that no next address signal NA is applied to the exclusive AND circuits 11 to 15 at this time. Therefore, the address register.
The star 21 receives signals input from the input terminals 11 to 15 (
1, 0, 0, 0, 0) is input and stored. Therefore, select the address line 11 in the ROM address section 5,
As a result, the address designation signal AD of RAM3 is (
A first register F designation signal of (1, 0, 1, 0, 0, 0) and a second register S designation signal of (1, 0, 0, 0, 1) are output. Furthermore, (0, 1, 0, 0) is output as the control signal 1NS. Furthermore, at this time,
The code signal CODE outputs nothing. ) Therefore, in the check circuit 9, as mentioned above, the address designation signal A
It is determined whether the Dl code signal CODEl control signal 1NS is outputting as designed. Also,
At this time, the next address signal NA is (0, 0, 0, 1, 0
) is output.

In other words, a command is given to select line 13 as shown in FIG. 3, but at the same time signals (0, 1, 0, 1, 0) are input from input terminals 11 to The outputs (A), 1, 0, 0, 0) of the exclusive OR circuits 11 to 15 are stored, and therefore line 12 is selected as the next step. Then, when line 12 is selected in the ROM address section 5, the address designation signal AD, that is, the first register F designation signal (0, 1, 0, 1
, 0, 1) and second register S designation signal (0, 1,
0, 0, 1, 0) code signal CODE (1, 0, 0, 0)
) and control signal 1NS (0, 0, 0, 1) are outputted from output terminals 01 to 022, respectively, and are checked in check circuit 9.

Also, at this time, as the next address signal NA (0, 0, 0
, 0, 1) are output, and at the same time input terminals 11 to I
, by inputting the signals (1, 1, 0, 0, 1) as shown in FIG. 3, the outputs of exclusive OR circuits 11 to 15 become (1, 1, 0, 0, 0), Therefore, line 13 is selected as the next step. Thereafter, in the same way, lines 13, 1, etc. are successively selected, and RO
The output of M2 is checked.

If, at this time, there is a defect in ROM2 and ROM address section 5, the abnormality will be detected by checking the ROM2 outputs except for the next address signal NA in the check circuit 9, and the next address signal NA will be erroneously detected. When outputting, the address lines 11, 12, etc. are not selected in the correct order, so the output of ROM2 in the next step is different from the expected output, and this abnormality is caused. It will be detected. In the above embodiment, the exclusive OR circuits 11 to 15 are used to sequentially specify addresses using the next address signal NA and the signals from the input terminals 11 to next. It may also be controlled by a matching circuit.

Further, in the above embodiment, output terminals 01 to 020 are separately provided in order to check the ROM2 output, and the terminals 01 to 020 are separately provided.
The output from ~020 is checked by the check circuit 9. Predetermined data is stored in the RAM 3, and this RAM 3 is addressed using the output of the ROM 2, and the stored contents of this RAM 3 are If the design data expected by the design of ROM2 is compared with the actual read data by reading from a terminal output to an external memory or display unit, etc., the external output terminals 01 to 020
It becomes possible to perform the check without separately installing the .

As explained in detail above, according to the present invention, the LS
A simple check circuit is created by inputting a predetermined test signal from outside the I, sequentially specifying the address of the ROM according to both signals, and simultaneously checking the ROM output to determine the quality of the ROM. This has the excellent effect that all ROM outputs including the next address signal can be easily and reliably checked simply by externally connecting the address signal.

[Brief explanation of the drawing]

l Figure 1 is a block circuit diagram of a small electronic calculator for explaining one embodiment of the present invention, Figure 2 is a detailed diagram of the main part of Figure 1, and Figure 3 is for explaining the operation of the present invention. It is a figure showing various signals of. 1...CPU12...ROM13...
...RAM14...AL, Ul5...
・ROM address section, 9...Check circuit, 1
0...Next address signal control section, 11-15...
...Exclusive OR circuit, 21...Address register.

Claims (1)

[Claims] 1. In an LSI equipped with a predetermined logic circuit that executes various arithmetic operations under the control of the output of a ROM that permanently stores various microinstructions including its own next address designation signal, Means for modifying an address by a test signal input from outside the LSI, and directly or indirectly leading out the memory contents of the address designated by the address designation signal modified by the means to the outside of the LSI. A ROM check method characterized in that a means for checking a ROM is provided.