JPH0370814B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data corruption detection device in a small electronic device equipped with an information processing function.

Some small electronic calculators use solar cells or a commercial AC power source as a power source. When using the above-mentioned solar cell or commercial AC power source, instantaneous voltage fluctuations are likely to occur, which may destroy data during calculation and display erroneous calculation results. In this case, there will be no problem if the power supply voltage drops completely and the power-on/clear function works, but if the voltage drops momentarily, the power-on/clear function may not work, which may cause miscalculations etc. as described above. arise. Furthermore, if the data changes to an impossible value, there is a risk that the arithmetic processing will enter an infinite loop, making it impossible to perform key input.

The present invention has been made in view of the above points, and is capable of reliably detecting data errors caused by instantaneous fluctuations in power supply voltage, etc., and uses the detection signal to detect errors such as all-clear processing and power-off processing. An object of the present invention is to provide a data corruption detection device that can perform processing.

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, reference numeral 1 denotes a key input section, and the key input data is sent to a RAM (random access memory) 3 via an arithmetic section 2. Also, 4
is a ROM that stores various microprograms
(read-only memory), and its storage contents are read out at timings T ₁ and φ ₂ by address designation from the ROM address section 5. That is,
From ROM4, row address UA and column address LA for RAM4, numerical code for calculation Code, various instructions INS, and own next address NA
is read out. The 2-bit row address UA read from ROM 4 is read from RAM 3, the 4-bit column address LA is stored in address counter 6, the numerical code Code is stored in calculation unit 2, and the instruction INS is read from RAM 3.
is instruction decoder 7, next address
NA is sent to the ROM address section 5. This ROM
The address section 5 further receives judgment data J regarding the calculation result from the calculation section 2 . this
The ROM address unit 5 reads the next address NA from the ROM 4 and the judgment data J from the calculation unit 2 in synchronization with the read pulse φ _R , decodes the contents, and specifies the address of the ROM 4. Further, the instruction decoder 7 decodes the instruction INS from the ROM 4 and provides a control command to the timing generation circuit 8. This timing generation circuit 8 uses the clock pulses φ ₁ and φ ₂ from the oscillation circuit 9 as references, and generates T ₁ , T ₂ , T ₃ ,
Generates various timing signals such as φ _R , φ _T1 , φ _T3 , T ₁ and φ ₂ . Further, the instruction decoder 7 is connected to the AND circuit 10 and the NOR circuit in the data destruction detection circuit 11 from the read/write control line a.
Give control command to _G1 . The control command output to this control line a becomes "0" when reading data, and becomes "1" when writing data. Further, a timing signal _T1 is input to the AND circuit 10, and its output signal is used as a read/write control command R/M.
Sent to RAM3. Further, the instruction decoder 7 sends a load instruction to the address counter 6. This address counter 6 loads the column address from the ROM 4 in response to the load instruction from the decoder 7, and outputs the 4-bit column address to the RAM 3.
Input to the above NOR circuit _G1 . Furthermore, the 2-bit row address UA output from the ROM 4 is input to this NOR circuit _G1 via inverters 12a and 12b. Therefore, the RAM 3 has various operation registers such as X,
Registers such as Y, Z, and M are configured. and,
For example, the 0th digit _M0 of the M register is used as a check data storage digit, and data "1010" is written therein. The M register is designated when the row address UA from the ROM 4 is "00", and the _M0 digit is designated when the column address LA from the counter 6 is "0000". The data read from the RAM 3 is input to the arithmetic unit 2 and also to the display unit 1.
3 and displayed. Further, sampling data is read from the RAM 3 to the key input section 1. Furthermore, the data read from the RAM 3 is processed by a NAND circuit in the data destruction detection circuit 11.
Entered into _G2 . In this case, of the 4-bit data output from the RAM 3, the first and third bits are inputted via the inverters 14a and 14b, and the second and fourth bits are directly inputted to the NAND circuit _G2 . The output of the NAND circuit _G2 is inputted to the AND circuit _G3 together with the output of the NOR circuit _G1 , and the output thereof is inputted to the flip-flop F1. This flip-flop F1 receives a clock pulse φ ₂
Reads the input in synchronization with flip-flop F2
Output to. This flip-flop F2 reads the input in synchronization with the timing signal φ _T1 , and its output becomes the detection signal RES of the data destruction detection circuit 11 and is sent to the ROM address section 5. This ROM
When the address section 5 receives the detection signal RES, it resets the held data and specifies the start address of the all-clear processing program in the ROM 4.

Next, the operation of the above embodiment will be explained. When the power switch is turned on, reference clock pulses φ ₁ and φ ₂ are outputted from the oscillation circuit 9 and sent to the timing generation circuit 8. The above clock pulses φ ₁ , φ ₂
As shown in FIG. 4, they have the same period but differ only in phase. The timing generating circuit 8 uses the clock pulses φ ₁ and φ ₂ as references and generates various timing signals as shown in FIG. 4 under control from the instruction decoder 7. Timing signals T ₁ , T ₂ , and T ₃ are sequentially outputted in synchronization with clock pulse φ ₂ , and one machine cycle is composed of T ₁ to _{T 3} . On the other hand, when the power switch is turned on, the ROM address section 5 specifies the start address of the all-clear processing program in the ROM 4, and the all-clear processing shown in step _S1 in FIG. 3 is performed.
Next, proceed to step _S2 , and write check data "1010" into the _M0 digit of the M register in RAM3. That is, the row address "11" designating the M register is output from the ROM 4, and the column address "0000" designating the M ₀ digit is output via the address counter 6.
Output. Furthermore, numerical code from ROM4
"1010" as the code is sent to the RAM 3 via the calculation unit 2.
and write it to the _M0 digit above. Thereafter, the process proceeds to key sampling processing shown in step _S3 . In this key sampling step, if the All Clear (AC) key is operated, the process returns to step _S1 , but if any other key is operated, the process returns to step _S4 .
Proceed to and check whether the content of the _M0 digit is "1010". In other words, by ROM4
Specify _M0 digit of M register in RAM3,
The contents are read out to the data destruction detection circuit 11 to check whether the data is destroyed or not. When specifying the _M0 digit of the M register above, the row address UA is "11", the column address LA is "0000", and the row address "00" is the inverter 12a,
12b, the inputs of the NOR circuit _G1 become all "0" in the read mode. Therefore, as shown in FIG. 4, the output of the NOR circuit _G1 becomes "1" for one machine cycle and is input to the AND circuit _G3 . On the other hand, the contents of _M0 digit read from RAM3 can be read directly or by inverters 14a and 14b.
When the above read data is normal, the first and third bits "0" of the 4-bit data "1010" are inverted and input to the NAND circuit _G2 by the inverters 14a and 14b. Because it is reversed to
All inputs to the NAND circuit _G2 become "1".
Therefore, the output of NAND circuit _G2 becomes "0",
The gate of AND circuit _G3 is closed to maintain the outputs of flip-flops F1 and F2 at "0". As a result, the data destruction detection signal RES is not output,
The ROM address section 5 is not reset.
Therefore, the next address of the ROM 4 is designated by the ROM address section 5, and the process proceeds from step _S4 to step _S5 in FIG. In this step _S5 , arithmetic processing is performed on the key input, and the result is sent to the RAM 3 to be stored. Next, the process advances to step _S6 , and in the same way as step _S4 , it is checked whether the content of the _M0 digit of the M register is "1010", and if there is no abnormality, it is written to RAM3 in step _S7 . The data is read out and displayed on the display section 13. Thereafter, the process returns to the key sampling step _S3 to prepare for the next key input.

However, in step _S4 or _S6 ,
When reading the contents of the _M0 digit of the M register from RAM 3, if the read data is destroyed, that is, if even 1 bit of the 4-bit data is inverted, all the inputs of the NAND circuit _G2 are As a result, a “1” signal is output from the NAND circuit G _{2 and} the AND circuit
G ₃ gate opens. Therefore, as shown in FIG. 4, the output of the AND circuit _G3 becomes "1", and the _flip -flop F
1. Furthermore, the data held in flip-flop F1 is written to flip-flop F2 by timing signal φ _T1 . The data written to this flip-flop F2 becomes the data destruction detection signal RES, and the ROM address section 5
sent to. As a result, the data held in the ROM address section 5 is reset, the start address of the all-clear processing program in the ROM 4 is specified, and the all-clear processing in step _S1 is performed.

In the above embodiment, the check data is written in the 0th digit of the M register, but the 0th digit of each register or all digits of a specific register may be used.

Furthermore, the detection of data destruction is not limited to the embodiment, but it will be more effective if it is also performed after display.

Further, in the above embodiment, all clear processing is performed using the data destruction detection signal, but other processes such as power-off processing and alarm processing may also be performed.

Further, the present invention is not limited to small electronic calculators, but can be widely applied to electronic devices equipped with memory.

As described above, according to the present invention, check data is written in the memory, and the presence or absence of data corruption is determined based on this check data. Even if the key is destroyed, the state can be reliably detected, and error processing such as all clear processing and power-off processing can be performed. It is possible to effectively prevent this from happening.

[Brief explanation of drawings]

The drawings show one embodiment of the present invention; FIG. 1 is a circuit configuration diagram, FIG. 2 is a diagram showing the RAM register configuration, FIG. 3 is a flowchart showing the operation contents, and FIG. 4 is a diagram showing the operation. This is a timing chart for explanation. 3...RAM (random access memory),
4...ROM, 7...Instruction decoder, 11...Data destruction detection circuit, F1, F2...
…flipflop.

Claims (1)

[Claims] 1. In an electronic device equipped with a memory, means for setting specific data for checking in a predetermined area of the memory, and reading and checking the specific data from the memory at least once in a processing cycle, and detecting that the specific data has been destroyed. A data destruction detection device comprising: means for outputting a data destruction detection signal; and means for performing error processing using the data destruction detection signal output from the means.