JPH0120778B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a reset factor determination method for determining a reset factor of a processor equipped with a volatile memory.

[Technical Background of the Invention and Problems Therewith] Generally, in this type of processor, a reset (initialization) operation is performed mainly in the following three cases.

When the power is turned on When a reset instruction is received from the operator panel When the processor's runaway detection circuit is activated ((when the watch timer is detected) In the above cases, a system reset is required, so the processor has On the other hand, in the above case, because of the RAS function, error status information and execution information are traced to the trace area in volatile memory, and the work area in volatile memory is cleared. An operation to clear the area, etc. is performed.

In this way, the reset operation in the processor differs depending on whether the reset factor is one of the above. Therefore, in conventional processors, in order to determine the cause of a reset, a dedicated hardware flip-flop is provided to memorize the power-on (power-off → power-on), and when a reset signal is input, the contents of the flip-flop are read and the cause is determined. method was adopted.

Although such a conventional system performs a correct reset operation depending on the reset factor, it has the disadvantage of requiring a dedicated hardware flip-flop for storing the reset factor.

[Object of the Invention] The present invention has been made in view of the above-mentioned circumstances, and its object is to provide a reset factor determination method that can determine the reset factor of a processor without using a hardware flip-flop.

[Summary of the Invention] In the present invention, a keyword area for setting keywords is provided in a volatile memory of a processor. When a reset signal is input to the processor, the processor reads the keyword in the keyword area, and if a read error occurs or the keyword is different from the expected keyword, it determines that the reset is due to a power-off (power-off → power-on). However, if there is no read error and the keyword matches the expected keyword, it is determined that the reset is other than power-off. That is, the present invention actively utilizes the fact that the contents of volatile memory become undefined in a power-off state.

[Embodiment of the Invention] FIG. 1 shows the configuration of a processor (data processing device) according to an embodiment of the invention. In the figure, numeral 11 is a microprocessor that forms the center of the whole, and numeral 12 is a ROM (program
ROM), 13 is RAM (volatile memory).
The memory area of RAM13 includes trace area 1.
In addition to well-known areas such as 4 and work area 15, a keyword area 16 in which predetermined (regular) keywords are set is allocated. 1
Reference numeral 7 denotes a monostable multivibrator (hereinafter referred to as a monomulti) to which a clock signal 18 output from the microprocessor 11 is supplied. The monomulti 17 receives the clock signal 18 (period T).
For example, depending on the rise of
T'>T) Outputs a signal at "H" (HIGH) level. 19 is a runaway detection flip-flop (F/F) for detecting runaway of the microprocessor 11; The runaway detection F/F 19 includes a preset terminal PR to which an output signal from the monomulti 17 is supplied, and a clear terminal to which a power on/off signal 20 indicating the power on/off state of the system is supplied.
CLR, and an output terminal Q. This power on/off signal 20 changes from the "L" (LOW) level to the "H" (HIGH) level in response to the system power being turned on.
The state changes from the "H" level to the "L" level before the power is turned off. An output signal from the output terminal Q of the runaway detection F/F 19 is supplied to the OR gate 22 as a runaway detection signal (watchdog timer detection signal) 21 indicating that the microprocessor 11 has runaway. This or gate 22
In addition to the power on/off signal 20, a reset instruction signal 2 is sent from an operator panel (not shown).
3 is also supplied. The output signal from OR gate 22 is supplied to microprocessor 11 as a reset signal 24.

Next, the operation of one embodiment of the present invention will be explained with reference to the flowchart of FIG. Now, any of the power on/off signal 20, runaway detection signal 21, or reset instruction signal 23 supplied to the OR gate 22 changes from the "L" (LOW) level to the "H" level.
It is assumed that the state has transitioned to the (HIGH) level. As a result, the OR gate 22 outputs a valid reset signal 24 to (a predetermined input terminal of) the microprocessor 11. Therefore, the microprocessor 11 receives the reset signal 24 from the OR gate 22.
When the execution address of the microprocessor 11 is detected, the execution address of the microprocessor 11 is moved to a predetermined address of the ROM 12 (generally the first address or the last address of the program area).
The program starting from the address (see the flowchart in FIG. 2) is executed.

First, the microprocessor 11 uses the RAM 13
The contents (keywords) of the keyword area 16 are read out (step S11). Then, the microprocessor 11 determines whether or not a read error (parity error, ECC error, etc.) has occurred during the above reading (step S12), and in the case of a read error (in the case of YES determination), It is determined that the reset was caused by a power outage (power off → power on). In this case, the microprocessor 11
executes steps S16 and 17, which will be described later. On the other hand, if there is no read error (if the determination in step S12 is NO), the microprocessor 1
1, it is determined whether the data read from the keyword area 16 matches a predetermined value (predetermined keyword) (step S13).

If the determination in step S13 is YES, the microprocessor 11 determines that the reset was caused by a factor other than a power outage, and first stores necessary information such as error status information and execution information in the trace area 14 of the RAM 13. (Step S14). Next, the microprocessor 11 clears the work area 15 (writes "0") (step S15).

On the other hand, if the determination at step S13 is NO (that is, if the data read from the keyword area 16 does not match the predetermined keyword), the microprocessor 11 (if the determination at step S12 is YES) It is determined that the reset was caused by a power outage (power off → power on). This is because when the power is turned off and then turned on again, the contents of the keyword area 16 of the RAM 13 are undefined (that is, the data is randomly set/reset), and therefore cannot be read. This is due to the necessity of an error or a mismatch with a predetermined keyword. When the microprocessor 11 determines that the reset factor is due to a power outage, it first performs an initialization operation (writing all "0") to clear the entire area of the RAM 13 (step S16). Next, the microprocessor 11 writes a predetermined keyword into the keyword area 16 of the RAM 13 (step
S17).

[Effects of the Invention] As described in detail above, according to the present invention, the cause of a processor reset can be determined without using a hardware flip-flop.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a processor according to an embodiment of the present invention, and FIG. 2 is a flowchart for explaining the operation. 11...Microprocessor, 12...
ROM, 13...RAM (volatile memory), 16...
...Keyword Area, 22...Or Gate.

Claims (1)

[Scope of Claims] 1. A volatile memory having a keyword area in which a predetermined keyword is stored, and a first signal indicating a power outage that is a reset factor or a second signal indicating a reset factor other than a power outage. Reset signal output means for outputting a reset signal when a signal is generated; and a processor for inputting the reset signal from the reset signal output means and reading a keyword from the keyword area of the volatile memory when the reset signal is input. The processor is configured to generate the reset signal when a read error occurs in reading the keyword or when the read keyword is different from an expected keyword. If it is determined that the reset signal is generated due to a reset factor other than the power interruption, if no read error occurs in reading the keyword and the read keyword matches the expected keyword. A reset factor determination method characterized by determining.