JPS5478636A - Input/output interface circuit - Google Patents

Input/output interface circuit

Info

Publication number
JPS5478636A
JPS5478636A JP14572377A JP14572377A JPS5478636A JP S5478636 A JPS5478636 A JP S5478636A JP 14572377 A JP14572377 A JP 14572377A JP 14572377 A JP14572377 A JP 14572377A JP S5478636 A JPS5478636 A JP S5478636A
Authority
JP
Japan
Prior art keywords
circuit
input
cpu1
control
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14572377A
Other languages
Japanese (ja)
Inventor
Tsuneki Mori
Hideo Asano
Isamu Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP14572377A priority Critical patent/JPS5478636A/en
Publication of JPS5478636A publication Critical patent/JPS5478636A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To secure the control for the input/output device which is not set previously by the specifications, by connecting the simple external circuits such as the FF to show the state of the control circuit, the register to store the data, etc. to the LSI-formed input/output control circuit.
CONSTITUTION: The data transfer system comprises CPU1, interface circuit 2 containing LSI-formed input/output control circuit 4, and input/output device 3. And register 11 to store the command given from CPU1 into circuit 2 plus circuit 12 to control device 3 via the contents of register 11 are installed in the data transfer system. Furthermore, FF group 6 and 7 are provided to count down the signal indicating the data request means or the data writing signal which is delivered from circuit 4 or transmitted to circuit 4 from CPU1. Then the state of circuit 2 is informed to CPU1 and device 3 via FF7, thus enabling the control for device 3 which is not set previously by the specifications.
COPYRIGHT: (C)1979,JPO&Japio
JP14572377A 1977-12-06 1977-12-06 Input/output interface circuit Pending JPS5478636A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14572377A JPS5478636A (en) 1977-12-06 1977-12-06 Input/output interface circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14572377A JPS5478636A (en) 1977-12-06 1977-12-06 Input/output interface circuit

Publications (1)

Publication Number Publication Date
JPS5478636A true JPS5478636A (en) 1979-06-22

Family

ID=15391632

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14572377A Pending JPS5478636A (en) 1977-12-06 1977-12-06 Input/output interface circuit

Country Status (1)

Country Link
JP (1) JPS5478636A (en)

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