JPS58129567A - Multi-system control device - Google Patents

Multi-system control device

Info

Publication number
JPS58129567A
JPS58129567A JP1135782A JP1135782A JPS58129567A JP S58129567 A JPS58129567 A JP S58129567A JP 1135782 A JP1135782 A JP 1135782A JP 1135782 A JP1135782 A JP 1135782A JP S58129567 A JPS58129567 A JP S58129567A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
device
processing
lock
system
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1135782A
Inventor
Toshinao Ide
Original Assignee
Nec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus

Abstract

PURPOSE:To reduce the number of times of main storage access as a system, and to raise efficiency of the whole system, by providing a lock bit, and generating an operation inhibiting signal. CONSTITUTION:A multi-system control device is constituted by connecting processing devices 2, 3 to a main storage device 1, and connecting a system control device 4 to the respective processing devices 2, 3. On this control device 4, FFs 15, 16 showing a lock bit, AND gates 17-22 and OR gates 23-25 are provided. In this state, when the FFs are not receiving a lock request of other processing devices 2, 3 in plural processing devices 2, 3, a lock of one processing device 2 or 3 received, and a lock from the other processing device 3 or 2 is not received. Also, when the lock request from the other processing device 3 or 2 is received, an operation inhibiting signal is sent out to the processing device 3 or 2 in accordance with the lock request or a lock reference requet from the processing device 2 or 3, and efficiency of the whole system is raised.
JP1135782A 1982-01-27 1982-01-27 Multi-system control device Pending JPS58129567A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1135782A JPS58129567A (en) 1982-01-27 1982-01-27 Multi-system control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1135782A JPS58129567A (en) 1982-01-27 1982-01-27 Multi-system control device

Publications (1)

Publication Number Publication Date
JPS58129567A true true JPS58129567A (en) 1983-08-02

Family

ID=11775771

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1135782A Pending JPS58129567A (en) 1982-01-27 1982-01-27 Multi-system control device

Country Status (1)

Country Link
JP (1) JPS58129567A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4975833A (en) * 1986-07-15 1990-12-04 Fujitsu Limited Multiprocessor system which only allows alternately accessing to shared memory upon receiving read and write request signals

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5365034A (en) * 1976-11-22 1978-06-10 Nippon Telegr & Teleph Corp <Ntt> Competitive circuit
JPS5462749A (en) * 1977-10-28 1979-05-21 Hitachi Ltd Multiple information processing system
JPS55103663A (en) * 1979-01-31 1980-08-08 Nissin Electric Co Ltd Micro computer composite unit
JPS5654562A (en) * 1979-10-09 1981-05-14 Nippon Telegr & Teleph Corp <Ntt> Competing circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5365034A (en) * 1976-11-22 1978-06-10 Nippon Telegr & Teleph Corp <Ntt> Competitive circuit
JPS5462749A (en) * 1977-10-28 1979-05-21 Hitachi Ltd Multiple information processing system
JPS55103663A (en) * 1979-01-31 1980-08-08 Nissin Electric Co Ltd Micro computer composite unit
JPS5654562A (en) * 1979-10-09 1981-05-14 Nippon Telegr & Teleph Corp <Ntt> Competing circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4975833A (en) * 1986-07-15 1990-12-04 Fujitsu Limited Multiprocessor system which only allows alternately accessing to shared memory upon receiving read and write request signals

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