JPS6318452A - Dma controller - Google Patents

Abstract

PURPOSE:To improve a processing speed by providing a DMA controller formed in an information processor for executing binary format data transfer with a circuit converting an ASCII code into a binary format. CONSTITUTION:What data are sent from an information processor to an I/O device 12 in the information processor 1, the device 12 sends a signal DREQ to the DMA controller 1. The controller 11 sends a signal HRQ to a CPU14. When a signal HLDA is returned from the CPU 14, the controller 11 sends a signal RD to the device 12. Data sent from the device 12 are stored in a register 113a. Reference data are stored in a register 113b. When the contents stored in the registers 113a, 113b coincide with each other, the contents of the register 113a are sent to a converter circuit 111a for converting an ASCII code into a binary format. Since data transfer is executed by using the converted data, the processing speed can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a DMA controller used to transfer data between information processing devices.

A conventional DMA controller provided in a conventional technical information processing device transfers the sent binary data as is to another information processing device.

However, if there is a code that cannot be used due to the protocol of the data transfer path, it is necessary to convert the transfer data in advance before transferring it. This converted data is inversely converted on the receiving side to return it to the original binary data. In this case, since conventional DMA controllers are equipped with only bidirectional buffers, in addition to necessary data, unnecessary data such as data simply indicating that the conversion has been performed is read into the storage device. Since extra software is required to perform the conversion, the storage area that can be effectively used is reduced.

Problems to be Solved by the Invention As explained above, conventional DMA controllers simply transfer data as is. For this reason, if data is converted as necessary during transfer, the receiving side performs reverse conversion using software. As a result of the need for software, processing speed is reduced and the storage area that can be effectively used in the storage device is reduced.

The present invention attempts to solve the above problems by providing data conversion hardware within the controller.

Means for Solving the Problems The DMA controller of the present invention for solving the above problems has a first register that stores data serving as a reference for comparison, and a second register that sequentially stores data to be transferred. A comparator that compares the stored contents of the register, the first and second registers, and a comparator that compares the recorded contents of the first register and the second register, and if they match, compares the contents of the second register. A
A conversion circuit that converts from SCII code to binary format, a latch that holds the output data of the conversion circuit, a buffer that temporarily stores the output of the latch, and the stored contents of the first register and the second register are compared. and a buffer for temporarily storing the data contents of the second register as they are if they do not match.

If the data to be transferred is reserved by the protocol, the conversion circuit 1 provided in the DMA controller 11
11a to convert from ASCII code to binary format. The converted transfer data is sent to the latch 115a,
Buff through 115b 7 yl16a, 116b
is temporarily stored.

If the data to be transferred is not reserved by the protocol, the data is temporarily stored as is in the buffer 116c.

The data stored in the buffers 116a, 116b, and 116c is output to the internal data bus 16 and then written to the address of the storage device 13 set in the storage device address counter 112b.

Example Hereinafter, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

Data from the information processing device 2 is transferred to the information processing device 1 including the DMA controller of the present invention.

The data 4 shown in Figure 3 Q:1), which is an example of the data to be transferred, is transferred to the binary format 10101011 (OA B
Assume that H). This data 4 is 10101011 B
(OA B H), and it is desirable to be able to transfer it as is. However, if the same data 0ABH is already reserved in the protocol, data 4 cannot be transferred as is.

If data 4 is reserved in the protocol, the upper data l0IOB is converted to data 2 shown in FIG. 3(a) in ASCII code, and the lower data l0IOB is
ASCII 0IIB to data 3 shown in Figure 3(a)
All you have to do is convert it to an I code and transfer it.

When converted into ASCII code, data 2 becomes 41H (0AH in binary format) and data 3 becomes 42H (0BH in binary format). Note that data 1 is special data indicating that the binary format has been converted into an ASCII code. Here, it is assumed that the data l is 2DH.

The block diagram shown in FIG. 1 will be explained below with reference to the timing chart shown in FIG. 4.

When data is sent from the information processing device 2 to the input/output device 12 in the information processing device 1, this input/output device 12 is operated as shown in FIG.
As shown in 1), a data request signal DREQ is sent to the DMA controller 11. Then, the DMA controller 11 sends a hold request signal HRQ shown in FIG. 4(2) to the central processing unit 14 to request control of the system bus. From the central processing unit 14, as shown in FIG.
The hold acknowledge signal HLDA shown in 3) is sent back to the D-1A controller 11. This hold acknowledge signal indicates whether control of the system bus has been relinquished. The DMA controller 11 is now the fourth
A read signal RD shown in FIG. 8 is sent to the input/output device 12. As can be seen from FIG. 4 (4) and (5), in synchronization with this read signal, the address data of the input/output device 12 set in the input/output device address counter 112a in the DMA controller 11 is read. It is stored in the register 113a.

The input/output device 12 receives the read signal and outputs the input/output data acknowledge signal I0DACK shown in FIG. 4(6).
It is sent back to the MA controller 11.

Data is read from the input/output device 12 onto the internal data bus 16 and stored in the register 113a. The other register is a special data setting register 113b, in which data 1, ie, 20H, is stored in this embodiment. Note that in FIG. 1, the path for storing data from the information processing device 2 in the register 113b is omitted.

The data stored in both registers l'13a and 113b are compared by a data comparator 114a. When the data stored in the register 113a and the data stored in the register 113b are the same, that is, both data are data 1 (20H), an enable signal E is sent from the data comparator 114a. occurs, the timing generator 11
8a will be manually operated. If the data stored in register 113a and the data stored in register 113b are different, enable signal Eln will not be generated.

First, the enable signal E l is sent from the data comparator 114a.
The case where n occurs will be explained. In this case, the following operations will be performed in sequence.

Following data 1, data 2 (41H) is stored in register 113a in the same manner as described above. Data 2 stored in this register 113a is stored in the conversion circuit 111a.
where it is converted from ASCII code to binary format.

FIG. 2 shows a detailed circuit of the conversion circuit 111a. The conversion circuit uses the lower 5 bits D of the ASCII code. ,Dl,D
1, D3, and D4 are input. D4 is input to the control input terminal of non-inverting buffer 2 old, 202.203.204. D4 is also inverted and input to the control input terminals of the inverting buffers 205 and 208.

D is further inverted and input to the control input terminals of non-inverting buffers 206 and 207. D3 is non-inverting buffer 2
01 and simultaneously input to the inversion buffer 205. Dl is the non-inverting buffer 202 and OR gate 2
10 will be man-powered. The output of OR gate 210 is connected to the input of non-inverting gate 206. Dl is a non-inverting buffer 203, an AND gate 211, and an XOR gate 212
It is man-powered. The output of the AND gate 211 serves as the other input for the OR gate 210. The output of XOR gate 212 is connected to the input of non-inverting buffer 207. Least significant bit D. is the non-inverting gate 204 and AN
The other input terminal of D gate 211 and XOR gate 2
12 and the inverting gate 208 .

The output of the non-inverting buffer 201 and the output of the inverting buffer 205 are connected, and the output from either buffer becomes the output as a converted value. Similarly, the outputs of non-inverting buffers 202 and 206, the outputs of non-inverting buffers 203 and 207, and the output of non-inverting buffer 204 and inverting buffer 208 are connected, respectively.

The operation of the conversion circuit having the above configuration will be described below, taking as an example the case where data 2 (41H) is input.

In this case, the data bits (Do, D=, Dl, D3
,D,) becomes (0,1,0,0,0). Since D4 is 0, this value is directly input to the control input terminal of the non-inverting buffers 201, 202, and 203.
．． 204 is in a cut state. In contrast, the inverting buffer 205.208 and the non-inverting buffer 206.20
7 is the inverted value of D, that is, 1, which is manually inputted as the control input, so these buffers 20 and 20 are input as converted values.
The output value of 5.206.207.208 will be output.

Since D3 is 0, the output of the inversion buffer 205 to which D3 is manually input is 1. Similarly, the inversion buffer 208 to which D is directly input outputs 0 since D0 is 1 in this case. AND game) 211. and D
1, that is, 1 and 0 are input manually, so 0 is output and input to the OR gate 210. This OR gate 210
Since the other human power is Dl, which is also 0, the OR gate 210 outputs 0. Therefore, 0 is output from the non-inverting buffer 206 to which the output of the OR gate 210 is input. Connect to XOR gate 212. and Dl are manually operated. Since each value is 1.0, this XO
The output of the R gate 212 becomes l. Since this output is input to the non-inverting gate 207, the output becomes 1. From the above, the converted result becomes 1.0.1.0 starting from the upper bit.

Data 2 manually entered into the conversion circuit 111a shown in FIG.
(41H) is l0 as upper data in binary format.
It was found that it was reconverted to IOB (OAH). Fourth
As shown in FIG. 11, the enable signal E from the timing generator 118a is synchronized with the read signal at the data 2 position. utl becomes low.

Therefore, data holding latch 115a is disabled and reconverted data 1010B (OAH) is latched (following data 2), and data 3 (42H) is transferred to register 113a in the same manner as described above. is memorized.

Data 3 stored in this register 113a is sent to the conversion circuit 111a, and in the same way as data 2, the AS
Converted from CII code to binary format.

That is, data 3 is reconverted to l0IIB (OBH) as lower data in binary format. Figure 4 (12)
As shown, the enable signal E from the timing generator 118a is synchronized with the read signal at the data 3 position. ut2 becomes low. Therefore, the data holding latch 115b is disabled and the reconverted data l0IIB (OBH) is latched.

When the above operations are completed, the DMA controller 11 sends a hold request (HRQ) signal shown in FIG. 4(2) to the central processing unit 14. The central processing unit 14 sends a hold acknowledge (HLDA) signal back to the DMA controller 11, as shown in FIG. 4(3). The DMA controller 11 then sends the write signal WR shown in FIG. 4 (9) toward the storage device 13. In synchronization with this, a write signal WRI is generated from the timing generator 118a, and the data buffer 11
6a and 116b are permitted to be output. Therefore, the upper data (OAH) and lower data (OBH) latched in the data holding latches 115a and 115b are written to the storage device 13 as 10101011 (OABH) in binary format. The address is set in the storage device address counter 112b in the DMA controller 11 and specified via the internal address bus 15. When the writing is completed, the storage device 13 is stored in the state shown in FIG. 4 (7).
) is the memory data acknowledge signal MDACK shown in D.
It is sent back to the MA controller 11. This completes the series of operations.

Next, the enable signal E i from the data comparator 114a
The case where n does not occur will be explained. In this case DM
The A controller 11 does not convert data. D
MA controller 11 receives hold request signal HRQ
is sent to the central processing bag 214. Then, the central processing unit 14 sends a hold acknowledge signal HLDA back to the DMA controller 11. The DMA controller 11 then sends the write signal WR to the storage device 13. At this time, the timing generator 118a generates a write signal WR2 to enable the data buffer 116C to output. Therefore, the data is written to the storage device 13 as is. The address is set in the storage device address counter 112b in the DMA controller and specified via the internal address bus 15. When writing is completed, the storage device 13 outputs a memory data acknowledge signal MDA.
The CK is sent back to the DMA controller 11, and the series of operations ends.

In the DMA controller 11 there is a booter rank 119a.
The number of data is counted according to the timing of the start signal WRI or WR2. When the conditions are met, a signal is sent to the interrupt generator 117a. This interrupt generator 117a
sends an interrupt signal INT to the central processing unit 14 when receiving a signal from the data counter 119a or a terminal count signal TC.

This completes the data transfer.

Effects of Hakko As explained in detail above, the DMA controller of the present invention is provided with a circuit that converts data expressed in ASCII code into binary format. For this reason,
This has the effect of improving processing speed because software for converting ASCII code into binary format is no longer required.

Another advantage is that the storage area of the storage device can be used effectively.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of an information processing apparatus including a DMA controller of the present invention, and FIG.
Embodiment of the data conversion circuit provided in the MA controller. FIG. 3 is a diagram showing the data structure. FIG. 4 is a timing chart showing the timing of the information processing apparatus shown in FIG. (Main reference numbers) l, 2...Information processing device 11...DMA controller 12...Population device 13
...Storage device 14..Central processing unit 15..Internal address bus 16..Internal data bus 111a..Conversion circuits 112a, 112b..Address counter 113a,
113b...Register 114a...Comparator! 15a,
115b...Latch 116a1116bs 116c...Hough 7711
7a...Interrupt generator 118a...Timing generator 119a...Data counter 2 old, 202.203.204.206.20? ...Non-inverting buffer 205.2(l(...Inverting buffer data 1 data 2 data! 3 data 4 Fig. 3

Claims (1)

[Claims] A DMA controller provided in an information processing device that transfers data in binary format, the DMA controller including a first register that stores data serving as a reference for comparison, and a first register that sequentially stores data to be transferred. a comparator that compares the stored contents of the second register and the first and second registers; and a comparator that compares the recorded contents of the first register and the second register, and if they match, the second register; a conversion circuit that converts the contents of from ASCII code to binary format, a latch that holds the output data of the conversion circuit, a buffer that temporarily stores the output of the latch, and the storage contents of the first register and the second register. DM characterized in that it is equipped with a buffer that temporarily stores the data contents of the second register as is if they do not match.
A controller.