JPH07281997A - Data transfer system - Google Patents

Abstract

PURPOSE:To transfer data at high speed while reducing the number or lines connecting two devices by transferring the data from the first device through the output of a counter, write signal and dual port random access memory (RAM) to the second device. CONSTITUTION:A counter 4 is reset by an A system start signal 1e and counted up by an A system write signal 1c. The output of this counter 4 becomes an A system address bus 1f of a dual port RAM 3. Corresponding to the A system start signal 1e, the counter 4 is reset, and the A system bus 1f is turned to '0'. Afterwards, data DATA'0' on an A system data bus 1d are written corresponding to the output of the A system write signal 1c and after the write, the A system address bus 1f is changed from '0' to '1'. Afterwards, the data are successively written from a device A to the dual port RAM by the similar operation as well.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a data transfer system between two devices.

[0002]

2. Description of the Related Art A conventional data transfer system will be described with reference to FIGS. 3 and 4 by taking a plant controller used as a sequence controller for electric power as an example. As one method of transferring data from one plant control device to the other plant control device, there is a serial transfer method in which information is sequentially transferred bit by bit. FIG. 3 is a block diagram illustrating this example. The plant control device A (hereinafter referred to as the device A) and the plant control device B (hereinafter referred to as the device B) are connected by several serial lines a, and the device A to the device (B) are connected using the serial line a. The data is serially transferred to 2 bit by bit. Examples of this method include RS-232C and RS-422A.

On the other hand, there is a parallel transfer system for simultaneously transferring a plurality of bits, and FIG. 4 is a block diagram for explaining an example of this. In FIG. 4, 3 is a dual port random access memory (hereinafter referred to as a dual port RAM) that can be simultaneously accessed from two plant control devices. A case of transferring data from the device A to the device B will be described. The device A uses the A system data bus 1a, the A system address bus 1b, and the A system write signal line 1c to set the A system data bus 1a to a specific address on the dual board RAM 3, that is, the address indicated by the A system address bus 1b. Write the data above. After this, the device B is connected to the B-system data bus 2
a, B system address bus 2b, B system read signal line 2c
Using a specific address on the dual port RAM3,
That is, the data is read from the address written by the device A, and the transfer from the device A to the device B is completed.

[0004]

The serial transfer method is
It has a feature that there are few lines connecting between two devices, but since it transmits serially bit by bit, it has a drawback that the transfer speed becomes slow. In addition, the parallel transfer method uses a plurality of data lines and thus has a high transfer rate, but has a drawback that many lines connect two devices.

Assuming that the dual port RAM 3 is arranged on the device B side in FIG. 4, the lines connecting the two devices are the A system data bus 1a and the A system address bus.
1b and A system write signal line 1c.

Now, assuming that the processor of the plant control device has a 32-bit structure and the amount of data to be transferred is 1 Kbyte, there are 32 A-system data buses 1a and 8 A-system address buses 1b (because 32 bits are 4 bytes. 1 Kbyte transfer is 1 Kbyte / 4 bytes = 256 = 2 ⁸ , and 8 address buses are required.), A system write signal line 1c
A total of 41 pieces.

Although it is possible to configure the A-system data bus 1a to have 8 lines by using 8 bits, the A-system address line (1 Kbyte = 2 ¹⁰ for 10 lines) is required.
You need 19 lines. An object of the present invention is to provide a data transfer system which can reduce the number of lines connecting two devices and can transfer data at high speed.

[0008]

In order to achieve the above object, in the present invention, a first device, a data bus consisting of a plurality of lines for transmitting data from this device, and a timing of writing the data. A write signal line for sending a write signal from the first device, a start signal line for sending a start signal for starting writing of data on the data bus from the first device, the write signal and the start signal , A dual port random access memory for inputting the output of the counter, the write signal, and the data on the data bus, and the transfer of the data from the first device through the memory And a second device for receiving the data.

[0009]

In the system thus constructed, the start signal line is input to the counter, and the counter causes the address of the dual port random access memory to be generated.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. In FIG. 1, 4 is a dual port R
This is a counter for generating the address of AM3. The same reference numerals are used for the configuration corresponding to FIG.

The connection lines between the device A and the dual port RAM 3 are a total of 10 8-bit A-system data buses 1d, A-system write signal lines 1c, and A-system start signals 1e.

The counter 4 is reset by the A system start signal (line) 1e, and the A system write signal (line) 1c.
Count up with. The output of the counter 4 becomes the A system address bus 1f of the dual port RAM 3.

The relationship between these signals is shown in FIG. The A-system start signal 1e resets the counter 4, and the A-system address bus 1f becomes "0". After this, the data Data (0) on the A system data bus 1d is written according to the output of the A system write signal 1c, and after writing, the A system address bus 1f changes from "0" to "1". After this, by the same operation, data is sequentially written from the device A to the dual port RAM 3. After that, the method in which the device B acquires the data is the same as the conventional technique.

In this embodiment, the start address for storing the data transferred from the device A is fixed from the address "0". However, if it is determined in advance that the start address will be a fixed address between the two devices, the data will be changed. There is no transfer problem. According to this embodiment, by adding one A-system start signal line, it is possible to obtain the transfer rate performance of the 8-bit parallel transfer system with a total of 10 lines.

[0015]

According to the present invention, by adding one start signal line, it is possible to eliminate the address bus in the conventional parallel transfer system, and it is possible to perform high-speed data transfer with a small number of connection lines.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment.

FIG. 2 is a time chart explaining the operation of one embodiment.

FIG. 3 is a block diagram illustrating a conventional serial transfer system.

FIG. 4 is a block diagram illustrating a conventional serial transfer system.

[Explanation of symbols]

 A, B ... Plant control device, 3 ... Dual port random access memory, 4 ... Counter, a ... Serial line, 1a, 1d ... A system data bus, 1b, 1f ... A system address bus, 1c ... A system write signal ( Line), 1e ... A system start signal (line), 2a ... B system data bus, 2b ... B system address bus, 2c ... B system read signal (line).

Claims (1)

[Claims] 1. A first device, a data bus comprising a plurality of lines for transmitting data from the device, and a write signal line for transmitting a write signal for determining the timing of writing the data from the first device. A start signal line for sending a start signal for starting writing of data on the data bus from the first device, a counter operating by inputting the write signal and the start signal, an output of the counter, the write signal And a dual port random access memory for inputting data on the data bus, and a second device for receiving the data transfer from the first device via the memory. .