JPH10269137A - Memory system and data processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a new memory system and a data processing system that very fast perform write/read of mass data among plural memory means through a system data bus. SOLUTION: This memory system is provided with memory means 26, which are connected between M-bit local data buses 28 N-bit (provided that N>M and that N and M are integers) system data bus 20 and a controlling means 30, which controls the input-output of data of the memory means, and the means 30 controls the input-output of N-bit parallel data to/from the memory means through the bus 20.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a memory system and a data processing system suitable for high-speed data transfer processing.

[0002]

2. Description of the Related Art With the development of technologies such as digital communication and digital television broadcasting, it has become necessary to perform arithmetic processing on a large amount of digital data at a very high speed. For that purpose, it is necessary to greatly improve not only the processing speed but also the data transfer speed in the system. In particular, when a series of arithmetic processing is performed using a plurality of arithmetic units, the data transfer speed between memories in each arithmetic unit affects the processing performance of the entire system. FIG. 4 is a block diagram showing an example of a configuration of a conventional memory system. System data bus 10 is a hardware system having a larger bit width than local data bus 12. Of course, this system includes a system address bus and a control bus in addition to the system data bus, but these are not shown for convenience of explanation. The bit width N of the system data bus is larger than the bit width M of the local bus (N> M). Usually, N is an integer multiple of M or 2 to the n-th power (n is an integer of 2 or more). Designed to. For example, the bit width of system data bus 10 is 256 bits and the bit width of local data bus 12 is 32 bits. In such a case, conventionally, a bit width converter 14 is provided, and the system data bus 10 and the local data bus 12 exchange the data bit width with each other to exchange data. For this reason, since a certain time is required for the bit width conversion process, it is extremely difficult to write a large amount of data into the memory 16 at high speed. For example, when converting 256-bit system data to 32-bit data, the original data width is divided into eight equal parts, and the local data
The 32-bit data is sequentially transferred to the memory 1 via the bus 12.
6 must be written. Until this processing is completed, new data cannot be written from the system data bus 10 to the memory 16.

Therefore, data transfer is performed at high speed,
In order to process a large amount of data in a short time, it is desirable to eliminate the bit width conversion between the system data bus and the local data bus. It is extremely difficult to reduce the number of bits of a processor that performs arithmetic processing to 256 bits, both technically and costly.

[0004] It is an object of the present invention to overcome the above-mentioned problems,
It is an object of the present invention to provide a novel memory system and a data processing system capable of writing / reading a large amount of data at a very high speed between a plurality of memory means or data processing means via a system data bus.

[0005]

SUMMARY OF THE INVENTION A memory system of the present invention comprises an M-bit local data bus and an N-bit (where N> M, N and M are integers) system data bus.
A memory means connected to the bus, and control means for controlling the input and output of data of the memory means. The control means transmits N bits to the memory means via a system data bus. The input / output of parallel data is controlled.

[0006] The memory means may include a plurality of dual port memories, each dual port memory having a pair of M-bit data input / output ports.

A local data buffer connected between the memory means and the local data bus;
A system data buffer connected between the memory means and the system data bus, wherein the control means includes a local data buffer for inputting and outputting data to and from the memory means via the system data buffer. -The buffer may be configured to be in a cutoff state. in this case,
The control means may be configured to shut off the system data buffer when inputting / outputting data to / from the memory means via the local data buffer.

Further, the memory means may include a plurality of single memories.
The single-port memory may include a port memory, and each of the single-port memories may be configured to have an M-bit input / output port.

The bit width N of the system data bus is
An integer multiple of the local data bus bit width M;
In particular, the bit width N may be configured to be the product of 2 to the power of n (n is an integer of 2 or more) and the bit width M.

In the data processing system of the present invention, an N-bit (N is an integer) system data bus to which a plurality of data processing means (PE) are connected in parallel, and a plurality of data processing means (PE) are connected in parallel to the plurality of data processing means. A source address bus, a destination address bus connected in parallel to the plurality of data processing means, and N-bit parallel data between a pair of data processing means among the plurality of data processing means. Control means for controlling input and output,
The source address bus and destination
By simultaneously addressing the address bus, data transfer between the pair of data processing means is performed in one cycle.

[0011]

FIG. 1 is a block diagram showing a configuration of an example of an embodiment of the present invention. A plurality of PEs (processing elements) 2 functioning as data processing means are provided on a system data bus 20 having a width of 256 bits.
2-i (i = 1, 2,...) Are connected in parallel. In the preferred embodiment of the present invention, a maximum of 64 PEs 22-i (i = 1 to 64) are used for system data transmission.
Although it is connectable to the bus 20, the present invention
It is not limited to the number of E. Each of these PEs includes a processor 24 and a memory means 26, and in each PE, the processor 24 and the memory means 26 are connected by a local data bus 28 having a width of 32 bits. Further, a source address bus 27 and a destination address bus 29 are connected in parallel to all the PEs 22-i. A control bus for performing other controls is also provided, but is not shown for convenience of explanation. Without the illustration of such a control bus, one skilled in the art would not have any trouble understanding the operation of the memory.

The plurality of PEs 22-i are interconnected via a system data bus 20, a source address bus 27, and a destination address bus 29, so that data can be transmitted and received between arbitrary PEs. Is possible. The system controller 30 controls transmission and reception of data on the system data bus 20 in this case. Generally, two PEs are selected from a plurality of PEs, and one of the two PEs functions as a data source that transmits data, and the other PE functions as a data destination to which data is transmitted. . In FIG. 1, a case will be described where, for example, the PE 22-2 functions as a data source and the PE 22-1 functions as a data destination. Note that the selection of the pair of PEs is for convenience, and it goes without saying that any of the plurality of PEs can be selected as the data source or the data destination.

First, PE-2 transfers some data to PE2.
2-1, the PE 22-2 sends a request signal for the right as a source to the system controller 30.
Send to When an acknowledgment signal is supplied from the system controller 30 to the PE 22-2, the PE 22-2
You have the right to act as a source. Then PE
22-2 sends a data transmission instruction to PE 22-1 in the system
When supplied to the controller 30, the system controller 30 supplies a destination memory request signal to the PE 22-1. The PE 22-1 returns a data write acknowledgment signal to the system controller 30 when data can be written to its own memory. When this data write acknowledgment signal is received, an address signal is simultaneously supplied from the system controller 30 to the PE 22-2 and the PE 22-1 via the source address bus 27 and the destination address bus 29, respectively. To PE2
Data transfer to 2-1 is performed simultaneously in one cycle period. At this time, the transfer of data having a maximum width of 256 bits via the system data bus 20 is performed in one cycle. As described above, the data transfer from the data source to the data destination can be performed in one cycle because the source address bus 27 and the destination address bus 29 are connected to all PEs in parallel independently of each other. Because he did. After the data transfer process,
The system controller 30 sends the end signal to the PE22-
2 to release the right to use the bus of PE22-2 as a data source.

Thus, a plurality of PEs 22-i (i =
1, 2,...) Is selected as a data source, and when the bus usage right is acquired, an arbitrary PE is selected as a data destination by a request from the data source, and Data transfer is performed from the source to the data destination. The maximum bit width of the data to be transferred is the bit width N of the system data bus, which in the preferred embodiment is 256 bits. Of course, the present invention is not limited to this bit width, but can transmit much larger amounts of data in a shorter time than a unit of data normally processed by a processor. The time over which data is transferred is extremely short. Further, since the memory in each PE (processing element) has a capacity of, for example, about 2 megabytes, it is possible to continuously write data required for normal data processing in a very short time. Therefore, it is possible to solve the inconvenience that the bit width of one word data is converted and the data of the next word cannot be transmitted until the write processing to the local memory is completed, as in the related art. Since a plurality of PEs can execute arithmetic processing independently of each other, each processor 24 transmits / receives data to / from its own memory means 26 via a local data bus 28 as necessary, and Arithmetic processing can be performed. In addition, as described above, the configuration in which the source address bus 27 and the destination address bus 29 are independently connected in parallel to all the PEs allows an address signal to be simultaneously applied to the data source and the data destination. The data transfer can be performed in one cycle. By configuring the system in this way, in a memory system in which a plurality of PEs are connected in parallel, transmission and reception of arbitrary data can be performed at extremely high speed, and pipeline processing and distributed processing of arithmetic processing by a plurality of processors can be performed. Thereby, it is possible to easily improve the data processing capability of the system.

FIG. 2 is a block diagram showing an example of the detailed configuration of one PE (processing element) 22 of FIG. 1 includes a plurality of single-port RAMs 32-j (j = 1, 2,...), Each single-port RAM 32-j, the system data bus 20, and the local data bus. 28, buffers 34-j and 36-j are provided, respectively. For example, if system data bus 20 is 256 bits wide and local data bus 28 is 32 bits wide, eight 32-bit single port RAs may be used.
The memory means 26 of FIG. 1 can be constituted by M and 16 buffers. It can be easily understood that the required number of RAMs and buffers can be appropriately set according to the bit width relationship between the system data bus 20 and the local data bus 28. In general, the bit width N of the system data bus 20 is equal to the bit width M of the local data bus 28.
In particular, it is desirable to set the value to 2 n times (n is an integer).

For example, when 256-bit data is written in parallel from the 256-bit system data bus 20 to eight single-port RAMs 32-1 to 32-8, eight buffers 34-1 to 34- are used. 8 are on, while the eight buffers 36-1 through 36-
8 is set to the off state. With this, 8 RAMs
It is ensured that data is simultaneously written to 32-1 through 32-8, and the processor 2 is connected via the local data bus 28.
4 can be avoided. Then, the eight buffers 34-1 through 3-3
4-8 is set to the off state, the PE (processing element) is disconnected from the system data bus 20, and the processor 24 sequentially sends local data to the eight buffers 36-1 to 36-8.・ Bus 28
Data can be exchanged via the. When the local data bus 28 is 32 bits, reading data of 256 bits requires 8 cycles of read processing. Since this processing is independent of the system data bus 20 and other PEs, the effect on the processing of the entire system can be substantially ignored.

FIG. 3 is a block diagram showing the configuration of another embodiment of the memory means 26 of FIG. In this configuration, a single port RAM is not used, a plurality of dual port RAMs are used, and no special buffer is required.
With this configuration, the system data bus 20 and the plurality of dual port RAMs 38-k (k = 1, 2,...)
.) Write / read processing and multiple dual
The write / read processing between the port RAM 38-k and the processor 24 can be executed simultaneously. With this configuration, it is possible to further improve the data processing efficiency of the entire system.

The preferred embodiment of the present invention has been described above.
It will be apparent to those skilled in the art that the present invention is not limited to only the above-described embodiments, and that various changes and modifications can be made without departing from the spirit of the present invention.

[0019]

As described above, since a large amount of data can be continuously written to and read from the memory means at a high speed by using a system data bus having a large bit width, an extremely high-speed and high-efficiency memory can be used. A system and a data processing system can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an example of an embodiment of the present invention.

FIG. 2 is a block diagram showing an example of a detailed configuration of a part of the system in FIG. 1;

FIG. 3 is a block diagram showing in detail an example of another embodiment of a part of the system of FIG. 1;

FIG. 4 is a block diagram showing an example of a configuration of a conventional memory system.

[Explanation of symbols]

 Reference Signs List 20 system data bus 22 processing element (data processing means) 24 processor 26 memory means 27 source address bus 28 local data bus 29 destination address bus 30 controller (control means)

Claims (15)

[Claims] 1. An M-bit local data bus and N
Memory means connected to a system data bus of bits (where N> M, M and N are integers); and control means for controlling data input / output of the memory means. Means for controlling input / output of N-bit parallel data to / from the memory means via the system data bus. 2. The memory means includes a plurality of dual port memories, each dual port memory having one dual port memory.
The memory system of claim 1, comprising a pair of M-bit data input / output ports. 3. A local data buffer connected between said memory means and said local data bus, and a system data buffer connected between said memory means and said system data bus. 2. A buffer according to claim 1, wherein said control means turns off said local data buffer when inputting / outputting data to / from said memory means via said system data buffer. Memory system. 4. The memory device according to claim 1, wherein the memory means includes a plurality of single memory devices.
4. The memory system according to claim 1, further comprising a port memory, wherein each of the single port memories has an M-bit input / output port. 5. The memory system according to claim 1, wherein said N is an integer multiple of said M. 6. The memory system according to claim 5, wherein said N is a product of 2 n (n is an integer of 2 or more) and said M. 7. The system according to claim 3, wherein said control means turns off said system data buffer when inputting / outputting data to / from said memory means via said local data buffer. Memory system. 8. An N-bit (N is an integer) system data bus in which a plurality of data processing means are connected in parallel; a source address bus connected in parallel to said plurality of data processing means; A destination address bus connected in parallel to the data processing means, and control means for controlling input / output of N-bit parallel data between a pair of data processing means among the plurality of data processing means. The source address bus and the destination
A data processing system wherein data transfer between the pair of data processing means is performed in one cycle by simultaneously addressing an address bus. 9. The data processing means includes: an M-bit (M is an integer) local data bus; and the local data bus and the N-bit (N
9. The system of claim 8, further comprising: memory means connected to the system data bus of > M), and a processor connected to said memory means via said local data bus. Data processing system. 10. The memory of claim 8, wherein said memory means includes a plurality of dual port memories, each dual port memory having a pair of M-bit data input / output ports. Data processing system. 11. A local data buffer connected between said memory means and said local data bus, and a system data buffer connected between said memory means and said system data bus. 9. A buffer according to claim 8, wherein said control means closes said local data buffer when data is input / output to / from said memory means via said system data buffer. Data processing system. 12. The memory device according to claim 8, wherein said memory means includes a plurality of single-port memories, each of which has an M-bit input / output port. Data processing system. 13. The data processing system according to claim 9, wherein said N is an integer multiple of said M. 14. The apparatus according to claim 13, wherein said N is a product of 2 to the nth power (n is an integer of 2 or more) and said M.
Data processing system as described. 15. The system according to claim 11, wherein said control means turns off said system data buffer when inputting / outputting data to / from said memory means via said local data buffer. Data processing system.