JPS60246457A - Memory access controlling circuit - Google Patents

Abstract

PURPOSE:To eliminate a variation of the contents of a channel buffer by executing access directly to a main storage device by using a flag signal of the time when memory access from a channel processor is executed to an input/output status word. CONSTITUTION:When memory access from a channel processor CHP is executed to an input/output status UCW on a main storage device MSU, notice is taken to a fact that a flag signal is outputted. In this state, by using a flag signal set to a UCW flag 13, a valid bit V read out of a channel buffer CHB tag part 30 us blocked forcibly by AND circuits 50, 51, and valid flags 70, 71 are set to off, and controlled. In case of a UCW fetch, the valid bit flags 70, 71 always seem to be off, therefore, are operated so as to execute fetch access to the MSU by an output signal of a UCW access flag 8. Access to CHB is not executed, therefore, the contents of the CHB are not varied.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a main storage unit (MSU) and a channel processing unit.
In a data processing device having a channel buffer (C)IB) between a channel buffer (C)
The present invention relates to a memory access control circuit that accesses a main storage unit (MSU) without referring to the main storage unit (MSU).

Technical background Generally speaking, in a data processing device that has a channel buffer (hereinafter referred to as CHB) between a main storage unit (hereinafter referred to as MSU) and a channel processing unit (hereinafter referred to as CHP), the COB is Considering that MSU access is performed in channel (CH) units and the access addresses are consecutive on the MSII address, channel (C1l
) and placed in the memory control unit (MCU).

Two blocks of C)IB are allocated to each channel (CI()), and the size of one block is 64 bytes.

FIG. 1 schematically shows the operation at C) IB in the above continuous data transfer. In this figure, DO~015 indicates byte numbers of continuous data.

First, ■ "In case of fetching data" With fetch access from channel (C)l), CUB
If the desired data does not exist, the MSU
to C) Load 64 bytes of data into the IB and at the same time transfer the specified 8 bytes directly to the CHP. From then on, C
It operates to fetch continuous data in units of 8 bytes from the HB.

The following 8 bytes of data within the above 64 bytes are vk
Read from cllB (for example, block 0) and CHP
When a specific 8 hides (C6 or D7 in the figure) are fetched within the 64 bytes, the briefetch control circuit is activated and the next 64 bytes consecutive on the address are fetched from the other block (e.g. , block 1).

■“In the case of data store” In case of store access from channel (CI(), CH
B, select any block (for example, block O) according to the contents of the tag part, and store the data in the byte mark (8 vias indicating which 8-byte area the data was stored in). ) works as if it were written.

If a subsequent store access requires a different block, the store data is controlled to be written to the other block (for example, block 1).

At this time (for example, when storing to C8), register the address of the block written in the previous store access (i.e., block 0) in the move-out queue (hoQUEUE), and then write the address of the block written in the previous store access to the move-out queue (MOQUELE).
Control is performed to sequentially move out the blocks from the MSU to the MSU.

■“When fetching something other than data [channel address word (CAM), channel command word (CCW)]”C
1 (Refer to B, if there is an address registered in the fetch operation, after invalidating the information, ?lsu is accessed and the information read from the iSU is controlled to be sent to the CHP. In this case, since the information is not continuous data, it is controlled not to be loaded into the CHB.

Further, if the result of referencing the CUB matches the address registered in the store operation, the block is moved out to the MSU and then the MSU is fetched.

■ "In the case of storing [channel status word (C!J)] other than data" Refers to the CHB, and if there are stored blocks, move them all (up to 2 blocks) to the MSU, and After the out operation is completed, the store access is executed to the MSU. In this case as well, writing to CHB is not performed.

For accesses other than data via CIIP, the channel address word (CIV) and channel command word (CC) are used.
W), fetching of input/output status word (UCW), etc., and channel status! ! (CSW), input/output status IN (UCW), etc.

The present invention relates to a method for effectively accessing an input/output status word (υcty) among non-data accesses, which does not require ordering.

(C1 Prior art and problems) In a data processing device having a CHB between the MSυ and CHP, subchannel information, dynamic address translation (DAT) table information, etc. are placed in a fixed area of the MSU, and when accessed, Access to the input/output status word (hereinafter referred to as U (J)) that does not require ordering is also
In the conventional method, the above-mentioned ■.

■It was under control. Therefore, if the fllUcW access is delayed depending on the state of the CHB, the "busy" period of the CHP boat becomes longer as a result, which poses a problem that adversely affects the throughput of data access in the CHP.

(2) In general, UCW access is performed in parallel with data transfer, so if the CUB is referenced each time and the data being transferred is invalidated or moved out, the number of block loads and moveouts will increase. However, there is a problem in that the throughput of data access in CHP is reduced.

(dl Purpose of the Invention In view of the above-mentioned conventional drawbacks, the present invention originally provides a data processing device having C)1B between the NSU and the CHP.
Even without CHB, CHP can be used as a means to detect address exception events when accessing the MSU from C) IP (for example, access exception events when the UC-area is accessed during normal data access). MSU
When accessing the above υC sodo area, the flag signal “CI
Focusing on outputting "IP IJc-", the purpose is to use this flag signal to provide an access method that takes into account the characteristics of the u side when CI (P accesses the above 11C- area). It is something to do.

(el Structure of the invention and this object is that according to the invention, a central processing unit (C
PU), a channel processing device (C) IP) that controls a plurality of channels (CH), a main storage device (?l5U),
a memory control unit (MCU) that performs access control to the main storage unit and interface control between the central processing unit (CPU) and the channel processing unit (CUP); and the main storage unit (MSU) and the channel processing unit (CUP). IP)
In a data processing device that has a channel buffer (CUB) between the channel buffer (CUB), general data access from the channel (CI) is performed via the channel buffer (CHB), but depending on the content to be accessed, the channel buffer (CUB) This is achieved by providing a method with the ability to directly access the main storage unit (MSU) without referencing the channel The contents of the buffer (CHD) do not change and the contents of the channel processing unit (CHD) do not change.
This has the advantage of preventing a drop in throughput in CIIP.

lfl Embodiments of the Invention First, to summarize the gist of the present invention, when a memory access from CHP is executed to uC-,
Flag “CIIPUCW” indicating uC-access from HP
'' is sent, and using the flag signal,
iSu directly without referencing (i.e. ignoring) CHB
It is designed to be accessed.

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the present invention, and 1.2 is a CHP address register (CHPAR).

11.21 is a channel (C)l) identification register, 12
．． 22 is a C) IP number identification section, 13 is a U (J flag necessary to implement the present invention, and 30.31 is a CHB tag section (CHB TAG), which corresponds to blocks 0 and 1, respectively. 40 .41 is a comparison circuit (C) provided corresponding to each block, and a CHP address register (CH
PAR) l contents and CHB tag part (CUB TAG)
The address part (^DDR) of 30.31 is compared bit by bit, and if they match, a match signal is output, and the tag part matches and a distal 0.61 is set. 8 is a UCC access flag, which is turned on by the output signal of the UC flag 13 only when the C1IP accesses the UC on the MSLI. 9 is a converter (DEC), the tag part matches and the distal 0, 61 . It decodes the contents of valid bit flags 70 and 71, which will be described later, to generate a part of the address of the CIIB data section (CHB DATA) 32. IOL 102.103 is the address register for CH, B data section (C11B[lAT^) 32, and for 101°102, the above channel (CI)
The output of the CHP number identification unit 22 is sent to the register 21, and for 103, the converter (DEC) 9
The output of is cents.

33 is CHB data register (CHP[lI?), 3
4 is C liver store data register (C) IPSTDR),
35 is the CIIP fencing data register (CHPFC
HI)R), 50.51 is an AND circuit with an inhibit input, and 70.71 is a 7-bit flag, each corresponding to block 0.1.

Now, when a memory access is performed from the CUP to the MSU, the memory address is written to the CHP address register (C) IPAR) 1, and the channel number to be accessed is written to the channel (CH) identification register 11. C) The IP number identification unit 12 has the corresponding channel (C)I)
is connected to the CI (P number is sent).

And channel (C11) 4M separate desk 11. and the contents of the CIP number identification section 12 as an address, CH
The B tag section (C) 18 TAG) 30.31 is accessed, its address section (ADDj?) is read out, and the comparison circuit (C) 40.41 compares it with the contents of the CHP address register (CHPAR) l. Ru.

According to the above comparison results, the finch operation and the store operation are performed.
9. lr! fil! Showa 56-091698. Special request 1977
8-166910, etc., so the explanation will be omitted, and only the parts related to the present invention will be explained below.

The present invention provides that memory access from the CHP is
When the upper UC is the enemy, the flag signal “CHP 11 (J”)
C) IB tag section (CFIB
The valid bit V read from TAG) 30 is forcibly closed by the AND circuit 50.51, the valid bit flag 70.71 is turned off, and the following control is performed.

(a) In the case of "rUc-fetch".

Due to the above operation, the valid bit flag is always 70.7.
1 appears to be off, the output signal of the Uc-access flag 8 operates to perform fetch access to the MSU.

That is, the command for the MSU at this time is "8-byte access", and the 8-byte fetch data fetched from 83υ is not loaded into CHB (i.e., U
(The gate circuit GF is controlled by the output signal of J access flag 8, and the CHP fetch data register (CHPFCH) is
DR) 35) directly to the CIIP and terminate the operation.

(b) In the case of “rUc-store”.

As in the case of the above fetch operation, since the valid bit flag 70 appears to be off, C) IB tag section (CH
B TAG) Referring to 30.31, a new block is selected and attempted to be stored, but due to UC-access, it is not stored in C) IB (i.e. uC
The gate circuit GS is controlled by the output signal of the d access flag 8, and the CI (P store data register ((JIPST)
DR), stores the 8-byte data directly in the MSU, and ends the operation.

As described above, when the present invention is implemented and uC-access is performed, the CHB is not accessed, so the CHH content does not change.

(a) Effects of the Invention As explained in detail above, the memory access control circuit of the present invention, when a memory access from C[' is executed to UC-, sets a flag cop indicating UC- access from CHP. ucW" is sent out, and uses this flag signal to directly access iSu without referring to (i.e., ignoring) CIIB, so it is possible to access iSu directly from the CHP to the input/output status area. (U(J)
Even if the access is executed, the contents of the COB do not change and the CH
This has the effect of preventing a decrease in throughput in P.

[Brief explanation of the drawing]

! @ Figure 1 is a diagram explaining the concept of the operation in C) 18 during continuous data transfer, and Figure 2 is a block diagram showing an embodiment of the present invention. In the drawing, DO-D15 is the number of consecutive 8-byte data, and 1 and 2 are COP address registers (CHP
AR), 11.21 is channel (C11) &! li separate register, 12.22 is CHP number identification section, 13 is t
ic-flag, 30.31 is the CHB tag part (CHB
TAG), 32 is the data section (CHB DATA),
40.41 is a comparison circuit (C), 50.51 is an AND circuit 160.61 is a tag part match register, 70.71 is a valid bit flag, 8 is a uC-access flag, 9
is a converter (DEC), 101 to 103 are address registers of the CHB data section (C) IB DATA), 3
3 is CI (B data register (CI (PDR)), 34
is (jlP storer register (CHPSTDR),
35 is a CHP fetch data register (CHPFCH
[lR), GS, and GF represent gate circuits, respectively.

Claims (1)

[Claims] A central processing unit (CPU) and a plurality of channels (C1l)
Access control to the channel processing unit (JIP), main storage unit (MSU), and main storage unit that controls the central processing unit (CPU) and channel processing unit (C
A memory control device (HP) that controls the interface between
MCU'), and a channel buffer (CHB) between the main storage unit (MSU) and the channel processing unit (CI(P)).
) in a data processing device having a channel (C)
General data access from I) is performed via the channel buffer (CHB), but depending on the content to be accessed, there is a function to directly access the main memory (MS[I) without referring to the channel buffer. A memory access control circuit comprising: