JPS57103526A - Interruption controlling system - Google Patents

Interruption controlling system

Info

Publication number
JPS57103526A
JPS57103526A JP17982580A JP17982580A JPS57103526A JP S57103526 A JPS57103526 A JP S57103526A JP 17982580 A JP17982580 A JP 17982580A JP 17982580 A JP17982580 A JP 17982580A JP S57103526 A JPS57103526 A JP S57103526A
Authority
JP
Japan
Prior art keywords
register
command
bit
interruption
fact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17982580A
Other languages
Japanese (ja)
Inventor
Noboru Yamamoto
Toshiaki Ihi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP17982580A priority Critical patent/JPS57103526A/en
Publication of JPS57103526A publication Critical patent/JPS57103526A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked

Abstract

PURPOSE:To obtain the desired processing capacity without increasing the capacity of an interface register for the debug, etc., by realizing the decision whether or not the contents stored in the interface register shows the address of a main storage device for the interruption bit. CONSTITUTION:When an interruption bit is set, the fact that a command is stored in a command register 7 or the address storing the command within a main storage device 2 is shown to the bit. A subprocessor detects an interruption; and if the bit contents shows the former fact, the contents of the register 7 are read. Then a prescribed process is carried out based on a working program of a substorage device, and the result of this process is sent to a main processor 1. In the case of the latter fact, the subprocessor reads the command at the position of the address of a register 7 through a DMA controlling circuit 6 to carry out a prescribed process. In such way, this control method is effective for the setting of a number of command parameters in case the number of commands is numerous to be stored in the register 7 and in the case of the debug in particular.
JP17982580A 1980-12-19 1980-12-19 Interruption controlling system Pending JPS57103526A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17982580A JPS57103526A (en) 1980-12-19 1980-12-19 Interruption controlling system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17982580A JPS57103526A (en) 1980-12-19 1980-12-19 Interruption controlling system

Publications (1)

Publication Number Publication Date
JPS57103526A true JPS57103526A (en) 1982-06-28

Family

ID=16072543

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17982580A Pending JPS57103526A (en) 1980-12-19 1980-12-19 Interruption controlling system

Country Status (1)

Country Link
JP (1) JPS57103526A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63223943A (en) * 1987-03-13 1988-09-19 Fujitsu Ltd Direct memory access control system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63223943A (en) * 1987-03-13 1988-09-19 Fujitsu Ltd Direct memory access control system
JPH0564820B2 (en) * 1987-03-13 1993-09-16 Fujitsu Ltd

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