JPS57162031A - Address stack control system - Google Patents

Address stack control system

Info

Publication number
JPS57162031A
JPS57162031A JP4827781A JP4827781A JPS57162031A JP S57162031 A JPS57162031 A JP S57162031A JP 4827781 A JP4827781 A JP 4827781A JP 4827781 A JP4827781 A JP 4827781A JP S57162031 A JPS57162031 A JP S57162031A
Authority
JP
Japan
Prior art keywords
address
stack
control information
stored
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4827781A
Other languages
Japanese (ja)
Other versions
JPS6325372B2 (en
Inventor
Kenji Sakai
Takashi Aoki
Sadao Nakao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP4827781A priority Critical patent/JPS57162031A/en
Publication of JPS57162031A publication Critical patent/JPS57162031A/en
Publication of JPS6325372B2 publication Critical patent/JPS6325372B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
    • G06F9/262—Arrangements for next microinstruction selection

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE:To lighten the burden of a program generating person, and to easily change a return instruction or a routine of the return instruction, by automatically storing the control information in a stack, and making it unnecessary that the generating person gives the return instruction over again. CONSTITUTION:A data for generating an address data of a main routine and subroutines 2, 3 stored in a microprogram storage device (CS) 6 from a computer is supplied to a CS red address generating circuit 5. In this circuit 5, an address of the CS 6 is generated, and a stack point being a write and read-out address is stored in a stack 4. Also, the address control information is provided to the stack 4 and the circuit 5, and an address of the control information generated by the circuit 5 is stored in address control information storage areas 7-0-7-n. In this state, the routine 1 is executed, and after that, when the control is shifted to the subroutines 2, 3, a return address to the routines 2, 3 and the address control information informing that the control is shifted after the return instruction has been issued are stored in the stack 4.
JP4827781A 1981-03-31 1981-03-31 Address stack control system Granted JPS57162031A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4827781A JPS57162031A (en) 1981-03-31 1981-03-31 Address stack control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4827781A JPS57162031A (en) 1981-03-31 1981-03-31 Address stack control system

Publications (2)

Publication Number Publication Date
JPS57162031A true JPS57162031A (en) 1982-10-05
JPS6325372B2 JPS6325372B2 (en) 1988-05-25

Family

ID=12798934

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4827781A Granted JPS57162031A (en) 1981-03-31 1981-03-31 Address stack control system

Country Status (1)

Country Link
JP (1) JPS57162031A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62286128A (en) * 1986-05-16 1987-12-12 インテル・コ−ポレ−シヨン Stack frame cash and control mechanism used therefor

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02130475A (en) * 1988-11-10 1990-05-18 Nec Corp Probe

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62286128A (en) * 1986-05-16 1987-12-12 インテル・コ−ポレ−シヨン Stack frame cash and control mechanism used therefor

Also Published As

Publication number Publication date
JPS6325372B2 (en) 1988-05-25

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