JPS5563436A - Operator panel control unit - Google Patents

Operator panel control unit

Info

Publication number
JPS5563436A
JPS5563436A JP13647878A JP13647878A JPS5563436A JP S5563436 A JPS5563436 A JP S5563436A JP 13647878 A JP13647878 A JP 13647878A JP 13647878 A JP13647878 A JP 13647878A JP S5563436 A JPS5563436 A JP S5563436A
Authority
JP
Japan
Prior art keywords
line
operator panel
opc2
control unit
panel control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13647878A
Other languages
Japanese (ja)
Inventor
Shinji Nishibe
Ikuya Itatsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP13647878A priority Critical patent/JPS5563436A/en
Publication of JPS5563436A publication Critical patent/JPS5563436A/en
Pending legal-status Critical Current

Links

Landscapes

  • Digital Computer Display Output (AREA)

Abstract

PURPOSE: To simplify the display to the operator panel, by transferring the contents of the register in CPU every given bit, in transferring the content of the register in CPU to the register in the operator panel control section OPC.
CONSTITUTION: The EXEC line 3 is connected between CPU1 and OPC2, and the start of operation is requested from OPC2 via the line 3. The data line 4 transfers the data between CPU1 and OPC2 and the data line of bidirectionality. Further, the two bit control line 5 is connected between CPU1 and OPC2, and the line 5 determines the direction of transfer of the data line 4, and the data line 4 consists of 16 bits and the control line is made up of 2 bits.
COPYRIGHT: (C)1980,JPO&Japio
JP13647878A 1978-11-06 1978-11-06 Operator panel control unit Pending JPS5563436A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13647878A JPS5563436A (en) 1978-11-06 1978-11-06 Operator panel control unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13647878A JPS5563436A (en) 1978-11-06 1978-11-06 Operator panel control unit

Publications (1)

Publication Number Publication Date
JPS5563436A true JPS5563436A (en) 1980-05-13

Family

ID=15176063

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13647878A Pending JPS5563436A (en) 1978-11-06 1978-11-06 Operator panel control unit

Country Status (1)

Country Link
JP (1) JPS5563436A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61182142A (en) * 1985-02-06 1986-08-14 Nec Corp Signal processing method and signal processing microprocessor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61182142A (en) * 1985-02-06 1986-08-14 Nec Corp Signal processing method and signal processing microprocessor

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