JP2010027202A - Magnetic storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To attain high-speed data access in a magnetic storage device. <P>SOLUTION: Source lines (SL0-SL3) arranged correspondingly to memory cell columns are driven by source line drivers (SLDR0, SLDR1) in accordance with read column selection signals (CSLR0, CSLR1). In a selected state of word lines (WL), a write current can be supplied into bit lines. Therefore, data can be continuously read out and/or written while the word lines are maintained in the selected state and high-speed access to a page mode or the like can be attained. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a magnetic storage device, and more particularly to a configuration for speeding up data access of a magnetic storage device.

  Thin film magnetic memory (MRAM: Magnetic Random Access Memory) has attracted attention as a memory that stores data in a nonvolatile manner with low power consumption.

  The memory cell of the thin film magnetic memory includes, in a data storage unit, a free magnetic layer whose magnetization direction is determined by an applied magnetic field, a fixed magnetic layer having a constant magnetization direction regardless of the applied magnetic field, A variable magnetoresistive element constituted by these free magnetic layers and a barrier insulating film between the fixed magnetic layers is included.

  When the magnetization direction of the free magnetic layer and the fixed magnetic layer is the same, the electrical resistance value of the storage section of this data is the lowest, and when the magnetization direction of the free magnetic layer and the fixed magnetic layer is different, the electrical resistance value Becomes higher. If this magnetoresistive effect is utilized, current can be supplied to the path of the free magnetic layer and the fixed magnetic layer of the memory cell, and the amount of current flowing through the memory cell can be detected to read the stored data of the memory cell.

  At the time of data writing, current is passed through digit lines and bit lines arranged orthogonal to each other corresponding to the memory cells, and the combined magnetic fields induced by the currents flowing through these digit lines and bit lines are respectively used. The magnetization direction of the free magnetic layer is set. By setting the magnetization direction of the combined magnetic field according to the write data, the magnetization direction of the free magnetic layer can be set to a high resistance state and a low resistance state according to the write data.

  The basic configuration and operation of such an MRAM are described in Non-Patent Document 1 (ISSCC 2000 Lecture Number TA-7.2), Non-Patent Document 2 (ISSCC 2000 Lecture Number TA-7.3), Non-Patent Document 3 (ISSCC 2001 Lecture Number 7). .6).

  In the MRAM shown in these non-patent documents, a memory cell is composed of one read selection transistor and one MTJ (Magnetic Tunnel Junction) element.

  In order to reduce power consumption in such an MRAM, the source line to which the read transistor is connected and the bit line to which the variable resistance element is connected are precharged to the same voltage level, and the bit line and source line of the selected column are precharged. Patent Document 1 (Japanese Patent Application Laid-Open No. 2002-343077) discloses a configuration in which each is connected to an internal data line and a ground line.

  The MRAM cell stores data using the magnetoresistive effect, and the ratio of the resistance value between the high resistance state and the low resistance state is required to be sufficiently large in order to accurately read the data. When the magnetization characteristics of the memory cell vary due to variations in manufacturing parameters, the resistance value of the variable magnetoresistive element also varies. In such a case, when data is read by comparison with the resistance value of a reference memory cell such as a dummy cell, accurate data reading is not guaranteed. Therefore, the following data reading method called a self-reference method has been proposed. Data in the selected memory cell is read and held. Next, for example, a fixed value of “0” is written to the selected memory cell, the fixed value data written from the selected memory cell is read again, the previously held read data and the newly read fixed value data Are compared to generate internal read data. Fixed value data is written in the same memory cell, and the read fixed value data shows the effect of resistance value fluctuation in the same direction as the original stored data. Is read out and data is read out.

  Such a self-reference type MRAM is disclosed in Patent Document 2 (Japanese Patent Laid-Open No. 2002-269968), Non-Patent Document 4 (ISSCC 2003 Lecture Number 16.1), and Non-Patent Document 5 (ISSCC 2003 Lecture Number 16.2). It is shown.

JP 2002-343077 A JP 2002-269968 A

ISSCC 2000 lecture number TA-7.2 ISSCC 2000 Lecture Number TA-7.3 ISSCC 2001 Lecture Number 7.6 ISSCC 2003 lecture number 16.1 ISSCC 2003 lecture number 16.2

  In the MRAM cell array, memory cells are arranged in a matrix. In a one-transistor, one-MTJ (or TMR (tunnel magnet-resistive)) element type memory cell structure, a word line and a digit line are provided corresponding to each row of memory cells, and a bit corresponding to each column of memory cells. Lines and source lines are provided. The word line is connected to the gate of the read selection transistor of the memory cell in the corresponding row, and the source line is connected to one conduction terminal (source) of the read selection transistor in the corresponding column. Usually, the source line is maintained at the ground voltage level. A variable magnetoresistive element (MTJ element or TMR element) of the memory cell in the corresponding column is connected to the bit line. The digit line is arranged away from the variable magnetoresistive element of the memory cell in the corresponding row.

  At the time of data writing, a write current is supplied to the digit line, and a magnetic field is induced by the write current. Since this digit line is not connected to a load, it is current-driven, and the write current can be raised and lowered relatively quickly. On the other hand, at the time of data reading, the word line is driven to the selected state and its voltage level is set to H level. The word line constitutes the gate of the read selection transistor, has a large load such as parasitic capacitance, and is voltage driven, so that the rise and fall of the word line voltage is relatively slow. For this reason, there is a mismatch in access time that the data write operation is relatively fast and the data read operation is relatively slow. As one method of compensating for this mismatch, it is desirable to be able to realize a page mode operation in which data is written or read while one word line is maintained in a selected state.

  However, in the MRAM cell array configuration in which the source line is fixed at the ground voltage level, when the word line is selected, all the read selection transistors of the memory cells connected to the word line are turned on, and therefore connected to the selected word line. A bit line is coupled to the source line via the memory cell. Therefore, when a write current is supplied to the bit line for data writing, this bit line write current flows out to the source line via the memory cell. When such a bit line write current leak occurs, a magnetic field having a desired magnitude cannot be induced, and erroneous writing occurs due to insufficient bit line induced magnetic field. In addition, a high voltage is applied to the variable magnetoresistive element of the memory cell in the high resistance state, and there is a problem that the tunnel barrier insulating film may be destroyed.

  In the above-mentioned Patent Document 1, a configuration is shown in which the bit line and the source line are precharged to the same potential, and only the source line of the selected column is coupled to the ground during data reading. At the time of data writing, the bit line pair of the selected column is connected to the internal data line pair with the source line separated from the ground, and the bit line write current is supplied from the internal data line by the write driver. However, in Patent Document 1, although reduction of current consumption is considered, high-speed access mode such as page mode operation is not considered.

  Also, Non-Patent Documents 1 to 3 merely show the basic configuration of the MRAM, and do not consider high-speed access modes such as page mode operation.

  In the self-reference type data reading, two sensing operations and one data writing operation are performed, and the data reading cycle becomes long. In the above-mentioned Patent Document 2, a configuration is shown in which high-speed data reading is realized by reading and latching 32-bit data internally in a self-reference manner and outputting the data to the outside in synchronization with a clock signal. Yes. The memory cell array is divided into a plurality of units each having a 32-bit width, and data is read from the plurality of units according to a self-reference method in a predetermined sequence in a pipeline manner. In this configuration, by accessing a plurality of units in a pipeline manner, 32-bit data from each unit is read every clock cycle in synchronization with the clock signal.

  However, in the configuration of Patent Document 2, a 32-bit sense amplifier is arranged for each unit. Therefore, a sense amplifier is arranged corresponding to each bit line. This increases the number of sense amplifiers and increases the layout area of the data read unit. In addition, since a selection sequence of a plurality of units is uniquely determined, there arises a problem that only continuous serial access can be performed. Further, in Patent Document 2, the relationship of the selection address between units is not considered, and there is no configuration for continuously accessing this array while maintaining the word line in the selected state in one array. It is not considered and data write access is not considered.

  SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a magnetic memory device capable of performing data access at high speed while suppressing an increase in circuit scale.

  A magnetic memory device according to a first aspect of the present invention corresponds to a plurality of memory cells having variable resistance elements arranged in a matrix and each having a resistance value set according to stored data, and each memory cell row A plurality of word lines connected to the memory cells in the corresponding row, and a plurality of bit lines arranged corresponding to the columns and connected to the memory cells in the corresponding columns. A reference voltage source for supplying a reference voltage, row selection means for maintaining a selected word line arranged corresponding to a row addressed according to a first address signal, and an active period of the row selection means Are activated and deactivated selectively according to the operation mode instruction signal, and when activated, column selection means for selecting a bit line according to the applied second address signal, and operates in parallel with this column selection means. , Row selection hand And a selective connection means for forming a path for read current flows through the memory cell selected by binding to the row and column selection means a portion of a memory cell on the selected word line to a reference voltage source by.

  A magnetic memory device according to a second aspect of the present invention includes a memory cell array including a plurality of memory cells each having a variable resistance element whose resistance value is set in accordance with stored data, and row and column address signals of the memory cell array A first internal read circuit for generating internal read data in accordance with the storage data of the selected memory cell specified by, and the fixed value data written to and read from the selected memory cell; After the storage data of the selected memory cell designated by the row and column address signals is read to the first internal read circuit, the fixed value data is written to the selected memory cell, and the memory cell to which the fixed value data is written A first read control circuit coupled to the internal read circuit and another selection specified by another row and column address signal of the memory cell array A second internal read circuit for generating internal read data in accordance with the stored data of the memory cell, and at the time of data reading, the selection is performed after reading the stored data of this other selected memory cell of the memory cell array to the second internal read circuit. A second read control circuit for writing fixed value data to the memory cell and coupling the memory cell having the fixed value data written thereto to a second internal read circuit, and an internal read from the first and second internal read circuits An output circuit that generates external read data in accordance with data and outputs the data to the outside, and a main control circuit that individually activates the first and second read control circuits in accordance with an operation mode instruction signal. These first and second read control circuits can be activated independently.

  A magnetic memory device according to a third aspect of the present invention includes a memory cell array including a plurality of memory cells arranged in a matrix and each having a variable resistance element whose resistance value is set according to stored data, and the memory cell array Internal read data having a smaller number of bits than the columns of the memory cell array is generated according to the storage data of the selected memory cell designated by the row and column address signals and the fixed value data written to and read from the selected memory cell Internal read circuit and, at the time of data read, after reading the stored data of the selected memory cell of this memory cell array to the internal read circuit, the fixed value data is written to the selected memory cell, and the memory cell to which the fixed value data has been written is read internally. In accordance with the read control circuit coupled to the circuit and the internal read data from the internal read circuit, external read data is generated and output to the outside. And an output circuit which, an output control circuit for activating an output circuit according to a read mode instruction signal. The output control circuit activates the output circuit so that the internal data read operation period of the internal read circuit overlaps at least a part of the operation period.

  In the magnetic memory device according to the first aspect, the column selection means is selectively activated in accordance with the operation mode instruction signal while the selected word line is in the selected state, and a part of the memory cells of the selected word line are set to the reference voltage. Coupled to the source. Therefore, when continuous access is performed with the word line selected, only some memory cells are coupled to the reference voltage source during data reading, and a read current path can be formed in the memory cell to be read. The data can be read out with. In addition, since the column selection means and the selection connection means operate in parallel, the memory cell is separated from the reference voltage source at the time of writing, and there is no leak path for the bit line write current, so that the writing due to the magnetic field failure It is possible to prevent imperfection, and data can be written in the page mode.

  In the magnetic memory device according to the second aspect, the first and second internal read circuits read data of the memory cells selected according to the row and column address signals, respectively, and a read circuit is provided for each column. There is no need to arrange the layout area, and the layout area of the data reading section is reduced. The data read control circuit can be activated independently and can randomly access a memory cell at an arbitrary address according to an address signal at an optimum timing.

  In the magnetic memory device according to the third aspect, the data of the memory cells in the selected column of the memory cell array is read out and output, the scale of the read circuit is reduced, and the memory cell at an arbitrary address in a random sequence Can be accessed. Further, data can be accessed at high speed by operating the internal read circuit and the output circuit in a pipeline manner.

1 schematically shows an entire configuration of a magnetic memory device according to a first embodiment of the present invention. FIG. It is a figure which shows roughly the structure of the principal part of the magnetic body memory | storage device shown in FIG. FIG. 3 is a timing chart showing an access operation of the magnetic memory device shown in FIG. 1. FIG. 2 is a diagram illustrating an example of a configuration of a bit line driving circuit illustrated in FIG. 1. FIG. 2 is a diagram schematically showing a configuration of a main control circuit shown in FIG. 1. FIG. 6 is a diagram showing an example of a configuration of a write mode detection circuit and a write activation circuit shown in FIG. 5. FIG. 7 is a timing chart showing an operation of the circuit shown in FIG. 6. FIG. 7 is a timing chart showing an operation in a page mode of the circuit shown in FIG. 6. FIG. 6 is a diagram showing an example of a configuration of a word line activation circuit shown in FIG. 5. FIG. 10 is a timing chart showing an operation of the circuit shown in FIG. 9. FIG. 2 is a diagram showing an example of a configuration of a portion that generates an address latch instruction signal of the main control circuit shown in FIG. 1. FIG. 12 is a timing diagram illustrating an operation of the circuit illustrated in FIG. 11. FIG. 2 is a diagram schematically showing a configuration of a word line driving circuit shown in FIG. 1. FIG. 2 is a diagram showing an example of a configuration of a digit line driving circuit shown in FIG. 1. FIG. 2 schematically shows an example of a configuration of a read column selection circuit shown in FIG. 1. FIG. 2 is a diagram showing an example of a configuration of a write column selection circuit shown in FIG. 1. It is a timing diagram which shows the data access sequence of the magnetic body memory device according to the modification of Embodiment 1 of this invention. It is a figure which shows schematically the structure of the principal part of the magnetic body memory | storage device in the example of a change of Embodiment 1 of this invention. It is a figure which shows schematically the structure of the data input / output circuit of the magnetic body memory | storage device in the modification of Embodiment 1 of this invention. It is a figure which shows roughly the structure of the whole magnetic body memory | storage device according to Embodiment 2 of this invention. FIG. 21 schematically shows a configuration of a data read cycle of the magnetic memory device shown in FIG. 20. FIG. 21 is a signal waveform diagram representing an operation during data reading of the magnetic memory device shown in FIG. 20. FIG. 21 is a timing chart showing an example of a data read sequence of the magnetic memory device shown in FIG. 20. FIG. 21 schematically shows a configuration of a bank control circuit shown in FIG. 20. FIG. 21 schematically shows a configuration of a write data generation circuit shown in FIG. 20. It is a figure which shows roughly the structure of the memory cell in the modification 1 of Embodiment 2 of this invention. It is a figure which shows roughly the structure of the modification 2 of the memory cell in Embodiment 2 of this invention. It is a figure which shows roughly the structure of the modification 3 of the memory cell in Embodiment 2 of this invention. It is a figure which shows roughly the structure of the whole magnetic body memory | storage device in Embodiment 3 of this invention. FIG. 30 schematically shows a configuration of a data read cycle of the magnetic memory device shown in FIG. 29. FIG. 30 is a timing chart showing a data reading sequence of the magnetic memory device shown in FIG. 29. FIG. 30 is a diagram showing an example of a configuration of a part that generates a read column selection signal of the column selection circuit shown in FIG. 29; FIG. 30 schematically shows a configuration of a column selection gate circuit of the column selection circuit shown in FIG. 29. FIG. 30 is a diagram showing an example of a configuration of a portion for generating a write column selection signal of the column selection circuit shown in FIG. 29. FIG. 30 schematically shows a configuration of a read control circuit shown in FIG. 29. FIG. 36 is a timing chart showing an operation of the read control circuit shown in FIG. 35. FIG. 30 schematically shows configurations of an internal readout circuit and a parallel-serial conversion circuit shown in FIG. 29. FIG. 30 schematically shows a configuration of a write circuit shown in FIG. 29. It is a figure which shows roughly the whole structure of the magnetic body memory | storage device according to Embodiment 4 of this invention. It is a figure which shows an example of the data reading sequence of the magnetic body memory | storage device shown in FIG. It is a figure which shows schematically the structure of the principal part of the magnetic body memory | storage device of the example of a change of this Embodiment 4. FIG. FIG. 42 is a timing diagram illustrating an operation of the circuit illustrated in FIG. 41.

[Embodiment 1]
FIG. 1 schematically shows an overall configuration of a magnetic memory device according to the first embodiment of the present invention. In FIG. 1, the magnetic memory device includes a memory cell array 1 having a plurality of memory cells M arranged in a matrix. In the memory cell array 1, the memory cell M includes a variable resistance element whose electrical resistance value changes according to storage data such as a TMR element or an MTJ element, in a storage unit. A word line WL and a digit line DL are arranged corresponding to each row of the memory cells M, and a bit line BL and a source line SL are arranged corresponding to each column of the memory cells. FIG. 1 representatively shows word line WL, digit line DL, bit line BL, and source line SL for one memory cell M indicated by a broken-line circle.

  The magnetic memory device further includes a main control circuit 2 that takes in a command CMD instructing an external operation mode in synchronization with the clock signal CLK and generates various internal operation instruction signals, and a row address latch from the main control circuit 2. Address input circuit 3 which takes in external address signal AD in accordance with instruction signal RAL and column address latch instruction signal CAL to generate internal row address signal RA and internal column address signal CA, and word line activation signal from main control circuit 2 The row address signal RA from the address input circuit 3 is decoded according to RX, and the address according to the word line drive circuit 4 for driving the addressed word line to the selected state and the write activation signal WX from the main control circuit 2 Decodes row address signal RA from input circuit 3 and writes to addressed digit line Digit line drive circuit 5 for supplying current and read column selection for selecting a column of memory cell array 1 by decoding internal column address signal CA from address input circuit 3 in accordance with read column activation signal RY from main control circuit 2 A read column selection circuit 6 for generating a signal and a source line drive circuit 7 for coupling a source line corresponding to a column addressed in accordance with the read column selection signal to a reference voltage source (ground) at the time of data reading.

  These read column selection circuit 6 and source line drive circuit 7 constitute a selective connection means, and source lines for some of the memory cells on the word line WL selected by the word line drive circuit 4 are provided. Coupled to a reference voltage source (ground).

  This magnetic memory device further decodes internal column address signal CA in accordance with write activation signal WX, generates a write column selection signal, and selects a column in accordance with this write column selection signal. A bit line driving circuit 8 for supplying a current to the bit line corresponding to the write data in a direction corresponding to the write data, and a current flowing through the bit line corresponding to the column selected by the read column selecting circuit 6 to the internal data bus RB. Includes an internal read circuit 10 for generating internal read data and an input / output circuit 11 for inputting / outputting data to / from the outside.

  Read column selection circuit 6 couples the bit line corresponding to the selected column to internal read data bus RB when activated. Internal read circuit 10 supplies a read current to the bit line in accordance with data read activation signal SEN from main control circuit 2, and generates internal read data in accordance with the read current.

  Input / output circuit 11 includes an output circuit for buffering internal read data from internal read circuit 10 in accordance with output activation signal OEN from control circuit 2 to generate external read data DQ. The input / output circuit 11 also generates internal data in accordance with external data DQ and supplies it to the bit line driving circuit 8. The input circuit of input / output circuit 11 may generate write data in each clock cycle in synchronization with clock signal CLK, and external data DQ in accordance with a write instruction signal (not shown) from main control circuit 2. May be latched to generate internal write data.

  In the configuration shown in FIG. 1, a word line drive circuit 4 and a digit line drive circuit 5 are arranged facing both sides of the memory cell array 1. These word line drive circuit 4 and digit line drive circuit 5 may be arranged adjacent to one side of the memory cell array.

  In the magnetic memory device shown in FIG. 1, source line SL and bit line BL are precharged to the same voltage level. At the time of data reading, the source line SL corresponding to the selected column is driven to the reference voltage (ground voltage) level by the source line driving circuit 7, and a current flows between the bit line and the source line via the selected memory cell M. Form a pathway. During data writing, the source line driving circuit 7 maintains the source line at the precharge voltage level. Therefore, even if the word line WL is in the selected state, the source line SL is separated from the reference voltage source, and even if a bit line write current corresponding to the write data is supplied to the selected bit line BL, Since the write current does not flow out to the source line SL, the bit line write current can be sufficiently supplied. Thus, data can be written and read according to column address signal CA while word line WL is maintained in the selected state, and high-speed access can be realized using page mode.

  FIG. 2 is a diagram more specifically showing a configuration of a main part of the magnetic memory device shown in FIG. FIG. 2 representatively shows a configuration of a portion related to memory cells M arranged in 2 rows and 4 columns. Memory cell M includes a variable magnetoresistive element VRE formed of an MTJ element or a TMR element, and a read selection transistor ATR that connects the variable resistance element VRE to a corresponding source line SL according to a signal potential on the corresponding word line.

  Word lines WL (WL0, WL1) and digit lines DL (DL0, DL1) are provided corresponding to the memory cell rows, and bit lines BL (BL0-BL3) and source lines SL are provided corresponding to the memory cell columns, respectively. (SL0-SL3) are arranged. The variable magnetoresistive element VRE is connected to the corresponding bit line BL, and one of the conduction terminals of the read selection transistor ATR is connected to the corresponding source line SL.

  The word line drive circuit 4 shown in FIG. 1 is provided corresponding to each of the word lines WL (WL0, WL1), and drives the corresponding word line to the selected state according to each of the word line selection signals WSL (WSL0, WSL1). Line drivers WDR (WDR0, WDR1) are included.

  Digit line driving circuit 5 shown in FIG. 1 is provided corresponding to each digit line, and in response to digit line selection signal DSL (DSL0, DSL1), digit line driver DLDR ( DLDR0, DLDR1). As an example, digit line driver DLDR includes a transfer gate that receives a digit line selection signal DSL at its gate. Digit lines DL (DL0, DL1) are always coupled to the power supply node and precharged to the power supply voltage VCC level. At the time of data writing, the digit line driver of the selected row is activated, and a current flows through the selected digit line from the power supply node to the ground node.

  Internal read data bus RB shown in FIG. 1 includes two internal read data lines RDB1 and RDB2. Data writing / reading is executed in 2-bit units.

  Read column select circuit 6 is provided corresponding to an adjacent bit line, and connects read bit select pair RCG (respectively) to a corresponding bit line pair to internal data lines RDB1 and RDB2 in accordance with read column select signal CSLR (CSLR0, CSLR1). RCG0, RCG1). Read column selection signal CSLR (CSLR0, CSLR1) is generated at the time of data reading from a read column decoder (not shown) included in read column selection circuit 6 in accordance with column address signal CA.

  A source line driver circuit 7 shown in FIG. 1 includes source line drivers SLDR (SLDR0, SLDR1) provided corresponding to pairs of source lines in adjacent columns. Source line driver SLDR is formed of an inverter, and drives a corresponding source line in accordance with read column selection signal CSLR for the corresponding column. Source line driver SLDR0 drives source lines SL0 and SL1, and source line driver SLDR1 drives source lines SL2 and SL3. Read column selection signal CSLR is at the H level (logic high level) when selected, and only the source line for the selected column is driven to the ground voltage level in accordance with source line driver SLDR, and the remaining unselected source lines are connected to power supply voltage. Maintained at level. Therefore, at the time of data writing, read column select signal CSLR is at L level (logic low level), so that source lines SL0 to SL3 are all maintained at H level (power supply voltage VCC level), and from bit line to memory cell M and There is no path for current to flow through the source line to the ground node.

  In this case, it is conceivable that in the selected column, current is supplied from the source line SL to the bit line BL via the memory cell M by the source line driver SLDR during data writing. By sufficiently reducing the current driving capability of the source line driver SLDR, the influence of the leakage current from the source line driver SLDR on the bit line write current can be substantially suppressed. Even when a leak current from the source line driver is supplied to the bit line, the source line leak current is supplied from the source line SL to the bit line BL in the direction of increasing the bit line write current. There is no problem of induced magnetic field failure due to insufficient write current, and data can be written accurately.

  The bit line driving circuit 8 shown in FIG. 1 includes bit line drivers BDR (BDR0 to BDR3) and BDL (BDL0 to BDL3) provided on both sides of each bit line BL (BL0 to BL3). Bit line drivers BDR and BDL are selected according to write column selection signal CSLW (CSLW0, CSLW1) applied to the corresponding column, and when selected, write current is applied to the corresponding bit according to complementary write data D, / D. Supply to the wire. The write column selection signals CSLW0 and CSLW1 are also supplied to the bit line drivers BDL0 to BDL3 together with the write data D and / D, but this path is not shown in FIG. 2 in order to simplify the drawing. .

  FIG. 3 is a timing diagram representing an operation in the page mode of the magnetic memory device according to the first embodiment of the present invention. Hereinafter, the operation in the page mode of the storage device shown in FIGS. 1 and 2 will be described with reference to FIG.

  This magnetic memory device operates in synchronization with the clock signal CLK. In access cycle # 1, an open row command Open-Row indicating the start of the page mode and a read command (L level read instruction signal / RE) indicating data reading are applied. The open row command Open-Row is a command for instructing driving of the word line to the selected state, and specifies the operation start in the page mode. When the open row command Open-Row is applied, the selected word line is maintained in the selected state until a closed row command for instructing driving of the selected word line to a non-selected state is applied.

  In accordance with row address signal RA # 1 applied in access cycle # 1, word line WL is driven to a selected state. Further, read column selection circuit 6 shown in FIG. 1 performs a column selection operation in accordance with column address signal CA # 1, and read column selection signal CSLR corresponding to the addressed column is driven to the selected state. Accordingly, in the source line drive circuit 7 shown in FIG. 1, the source line driver SLDR corresponding to the selected column drives the corresponding source line SL to the ground voltage level, and in the memory cell M of the selected column, the source from the bit line is sourced. A path through which current flows is formed in the line. On the other hand, read column select gate RCG included in read column select circuit 6 is rendered conductive in the selected column, and couples the selected bit line to internal data lines RDB1 and RDB2. Thereafter, read column selection signal CSLR is driven to a non-selected state at a predetermined timing.

  The data in the memory cell designated in access cycle # 1 is read out as data DOUT # 1 in access cycle # 2 after the elapse of one clock cycle. When a read command is again applied in synchronization with clock signal CLK in access cycle # 2, a column selection operation is performed in accordance with column address signal CA # 2 at that time. In this case, since word line WL is already in the selected state, it is only required to couple the bit line of the selected column to internal data bus RB and read through internal read circuit 10 shown in FIG. . Therefore, data DOUT # 2 is output at the falling edge of clock signal CLK.

  Therefore, in the page mode, data is read out in a half cycle of the clock signal CLK. Therefore, when the page mode operation is performed with the open row command Open-Row, the rising and falling edges of the clock signal CLK are detected. Data is accessed synchronously. Data write only drives the digit line with current, selects the digit line and bit line in half a cycle of the clock signal CLK, supplies the write current, and writes data to the selected memory cell. Can be done.

  Therefore, access cycle # 3 starts with the fall of clock signal CLK, and write column select signal CSLW is driven to the selected state by write column select circuit 9 shown in FIG. 1 in accordance with column address signal CA # 3 at that time. A bit line write current according to write data DIN # 3 is supplied to the selected column from bit line drive circuit 8 shown in FIG. For example, when bit lines BL0 and BL1 are selected in FIG. 2, bit line write current is supplied to bit line BL0 by bit line drivers BDL0 and BDR0, and bit line BL1 and bit line driver 1 are connected to bit line BL1 by bit line drivers BDL1 and BDR1. A write current is supplied. At this time, source lines SL0 and SL1 are at the H level, and there is no path through which a write current flows from bit lines BL0 and BL1 to source lines SL0 and SL1.

  At this time, digit line driving circuit 5 shown in FIG. 1 operates in accordance with the write command (indicated by write instruction signal / WE) in accordance with the latched row address signal, and digit line DL corresponding to the selected word line is grounded. Coupled to the node to generate a digit line write current. As a result, data DIN # 3 is written to the selected column. At the time of data writing, digit line DL is current-driven, and digit line current can be raised and lowered at a higher speed than word line, and data can be written within half cycle of clock signal CLK. Can be executed.

  In the next access cycle # 4, the write command is again applied, and write instruction signal / WE is at L level and read instruction signal / RE is at H level. A column selection operation is performed in accordance with column address signal CA # 4 applied in access cycle # 4, write column selection signal CSLW for the selected column is driven to a selected state, and digit line drive is performed in accordance with the latched row address signal. In circuit 5, the digit line corresponding to the selected word line is coupled to the ground node by the corresponding digit line driver, and data is written.

  In access cycle # 5, write instruction signal / WE is at H level, read instruction signal / RE is at L level at the falling edge of clock signal CLK, and a read command is applied. When this read command is applied, column selection operation is performed by read column selection circuit 6 shown in FIG. 1 according to address signal CA # 5 at that time, and read column selection signal CSLR for the selected column is driven to a selected state. Is done. Corresponding source line driver SLDR couples the source line corresponding to the selected column to the ground node, and corresponding read column selecting gate RCG is turned on, and bit line BL corresponding to the selected column is connected to internal data lines RDB0 and RDB0. Connected to RDB1, data is read out. Even when a read command is applied in access cycle # 5, data line DOUT # 5 is output at the rising edge of the next clock signal CLK because word line WL is still selected.

  In access cycle # 6, a close row command indicating the end of the page mode is applied together with the write command, the open row command (page mode instruction signal) Open-Row is at the L level, the write instruction signal / WE is at the L level, the read instruction signal / RE is set to H level. Thus, the column selection operation is performed according to column address signal CA # 6 at that time, and after data DIN # 6 is written to the selected memory cell, word line WL is driven to the non-selected state.

  Therefore, data is accessed by giving a write command and a read command indicating data writing and reading, respectively, in a state where word line WL is maintained in a selected state when open row command Open-Row is applied. be able to. At the time of data reading to which a read command is applied, the word line WL is already in a selected state and it is only necessary to select a column. Therefore, data can be read out in a half cycle of the clock signal CLK, and high speed Access can be realized.

  In page mode operation, data is transferred in synchronization with both the rising edge and falling edge of the clock signal CLK, and high-speed data transfer according to the DDR (double data rate) mode that is generally used at present. Can be realized.

  FIG. 4 is a diagram showing an example of the configuration of bit line drivers BDR0 to BDR3 and BDL0 to BDL3 shown in FIG. FIG. 4 generically shows bit line drivers BDL and BDR provided for bit line BL.

  Write column selection circuit 9 shown in FIG. 1 includes a decoder 19 provided corresponding to a bit line pair. When the write activation signal WX is activated, the decoder 19 decodes a predetermined set of bits of the internal column address signal CA to generate a write column selection signal CSLW. Write column select signal CSLW from decoder 19 is applied commonly to bit line drivers BDR and BDL.

  Bit line driver BDL includes a NAND gate NG1 receiving write data D and write column selection signal CSLW, an AND gate AG1 receiving write column selection signal CSLW and complementary write data / D, and NAND gate NG1. A P channel MOS transistor PQ1 that conducts when the output signal is at L level and supplies current from the power supply node to the bit line BL, and conducts when the output signal of the AND gate AG1 is at H level and conducts from the bit line BL to the ground node. An N channel MOS transistor NQ1 for drawing a current to is included. Data D and / D are complementary to each other.

  Bit line driver BDR has a NAND gate NG2 receiving write column selection signal CSLW and complementary write data / D, an AND gate AG2 receiving write data D and write column selection signal CSLW, and an output of NAND gate NG2. P channel MOS transistor PQ2 that conducts when the signal is at L level and supplies current from the power supply node to bit line BL, and conducts when the output signal of AND gate AG2 is at H level and conducts current from bit line BL to the ground node. An N channel MOS transistor PQ2 to be extracted is included.

  At the time of data reading and precharging, decoder 19 is inactive and write column select signal CSLW is at L level. Therefore, the output signals of NAND gates NG1 and NG2 are both at H level, the output signals of AND gates AG1 and AG2 are at L level, and MOS transistors PQ1, PQ2, NQ1, and NQ2 are all in an off state. At the time of data reading, bit line BL is coupled to an internal data line by a transfer gate in read column selection gate RCG shown in FIG.

  At the time of data writing, write data D and / D are set to a logic level corresponding to external data. When write column selection signal CSLW from decoder 19 attains H level, NAND gates NG1 and NG2 operate as inverters, and AND gates AG1 and AG2 operate as buffer circuits. When write data D is "1" (H level), complementary write data / D is at L level. In bit line driver BDL, the output signals of NAND gate NG1 and AND gate AG1 are at L level. MOS transistor PQ1 is turned on and MOS transistor NQ1 is turned off. In bit line driver BDR, the output signals of NAND gate NG2 and AND gate AG2 are both at H level, MOS transistor PQ2 is turned off, and MOS transistor NQ2 is turned on. Therefore, a current is supplied to bit line BL from the power supply node via MOS transistor PQ1, and this supplied current is discharged to the ground node via MOS transistor NQ2, and the bit line write current on bit line BL is discharged. IW (BL) flows from right to left.

  On the contrary, when the write data D is “0” (L level), in the bit line driver BDL, the output signals of the NAND gate NG1 and the AND gate AG1 are both at the H level. In bit line driver BDR, the output signals of NAND gate NG2 and AND gate AG2 are both at L level, MOS transistor PQ2 is turned on, and MOS transistor NQ2 is turned off. Therefore, in this state, a current is supplied from the power supply node to bit line BL via MOS transistor PQ2, and the supplied current is discharged via MOS transistor NQ1. Therefore, a bit line write current IW (BL) flows from the bit line driver BDR toward the bit line driver BDL.

  The configuration of the bit line drivers BDL and BDR shown in FIG. 4 is merely an example, and another configuration may be used. A circuit configuration for supplying a current corresponding to write data to the bit line of the selected column is used. , Just use.

  Note that a predetermined combination of column address bits of the multi-bit column address signal CA may be supplied to the decoder 19, or a signal obtained by predecoding the multi-bit column address signal CA may be supplied.

  FIG. 5 schematically shows a configuration of a main part of main control circuit 2 shown in FIG. In FIG. 5, the main control circuit 2 includes an AND gate 20 that receives a clock signal CLK and an open row command (page mode instruction signal) Open-Row, and a clock signal CLK and a close row command (page mode completion instruction signal) Close-Row. And an AND gate 21 receiving the page clock signal CLKPG and the close-row command Close-Row, an OR gate 23 receiving the output signals of the AND gates 21 and 22, and an output signal of the AND gate 20 and A set / reset flip-flop 24 that is reset according to the output signal of the OR gate 23 to generate the page mode designation signal OPRW, and delays the page mode designation signal OPRW for a half clock cycle period of the clock signal CLK. A clock delay circuit 25, an AND gate 26 to generate a page mode clock signal CLKPG receives the clock signal / CLK of the complement and delayed page mode designation signal OPRWD from half-clock delay circuit 25.

Clock signals CLK and / CLK are complementary to each other.
The main control circuit 2 further receives a page mode clock signal CLK, a clock signal CLK and an external write instruction (write command) ext / WE, and generates a write mode designation signal WE. Write activation circuit 28 for generating write activation signal WX that is active for a predetermined period in accordance with write mode designating signal WE, page mode clock signal CLKPG and clock signal CLK, and an external data read instruction (read command) ) Read mode detection circuit 29 for generating read mode designation signal RE in response to ext / RE, and read column activation for maintaining read column activation signal RY in an active state for a predetermined period in accordance with activation of read mode designation signal RE A word line activation signal RX is generated in accordance with circuit 30, read mode designation signal RE and page mode designation signal OPRW. It includes word line activation circuit 31.

  Write mode detection circuit 27 drives write mode designating signal WE to an active state when a write command is applied when clock signal CLK rises or page mode clock signal CLKPG rises. In response, write activation circuit 28 maintains write activation signal WX in an active state for a predetermined period. Similarly, read mode detection circuit 29 activates read mode designating signal RE when a read command is applied at the rise of clock signal CLK or page mode clock signal CLKPG, and read column activation circuit 30 causes read column activation signal RY. Are driven to the active state for a predetermined period. Therefore, when the page mode is designated, the rising edges of both the page mode clock signal CLKPG and the clock signal CLK are used as command detection triggers. Therefore, in the page mode, the rising edge and the falling edge of the clock signal CLK are synchronized. Thus, data writing / reading is designated (page mode clock signal CLKPG is generated from complementary clock signal / CLK).

  The word line activation circuit 31 drives the word line activation signal RX to an active state for a predetermined period (one clock cycle period) when the read mode designation signal RE is activated, and the word line activation circuit 31 operates while the page mode designation signal OPRW is in the active state. The line activation signal RX is maintained in the active state.

  FIG. 6 is a diagram showing an example of the configuration of write mode detection circuit 27 and write activation circuit 28 shown in FIG. In FIG. 6, a write mode detection circuit 27 includes a gate circuit 27a that receives a clock signal CLK and an external write command (write instruction signal) ext / WE, a page mode clock signal CLKPG, and an external write command ext / WE. A gate circuit 27b that receives WE, a one-shot pulse generation circuit 27c that generates a one-shot pulse signal in response to the rise of the output signal of the gate circuit 27a, and a one-shot in response to the rise of the output signal of the gate circuit 27b Includes a one-shot pulse generation circuit 27d for generating a pulse signal of 1 and an OR circuit 27e for receiving the output signals of these one-shot pulse generation circuits 27c and 27d and generating a write mode designation signal WE.

  Gate circuits 27a and 27b are H level signals in response to rising of clock signal CLK and page mode clock signal CLKPG when external write command ext / WE is at L level and the write mode is instructed. Are output respectively.

  The one-shot pulse generation circuit 27c generates a one-shot pulse signal at the data write timing in the normal operation mode, and the one-shot pulse generation circuit 27d generates a one-shot pulse signal at the write timing in the page mode To do.

  Write activation circuit 28 is activated when delay page mode designating signal OPRWD is inactive, and generates a one-shot pulse signal in accordance with activation of write mode designating signal WE from write mode detection circuit 27. A shot pulse generating circuit 28a, a one shot pulse generating circuit 28b which is activated when the delayed page mode designating signal OPRWD is activated, and generates a one shot pulse signal in response to the activation of the write mode designating signal WE; An OR circuit 28c for receiving the output signals of these one-shot pulse generation circuits 28a and 28b and generating write activation signal WX is included.

  One shot pulse generation circuit 28a generates a one shot pulse signal in accordance with activation of write mode designation signal WE in the normal access operation mode, and one shot pulse generation circuit 28b generates a write mode designation signal in the page mode operation. A one-shot pulse signal is generated according to WE. At the time of data writing, the amount of write current flowing through the bit line and the digit line is the same in the normal operation mode and the page operation mode. Only the data writing timing is different. Therefore, the one-shot pulse generation circuits 28a and 28b only differ in the pulse generation timing, and the time widths of the generated pulses are the same.

  FIG. 7 is a timing chart representing operations in normal operation mode of write mode detection circuit 27 and write activation circuit 28 shown in FIG. Hereinafter, the operation of the circuit shown in FIG. 6 in the normal operation mode will be described with reference to FIG.

  In the normal operation mode, page mode clock signal CLKPG is at L level, and the output signal of gate circuit 27b is maintained at L level. When the external write command ext / WE is set to the L level at the rising edge of the clock signal CLK, the output signal of the gate circuit 27a becomes the H level and accordingly has a predetermined time width from the one-shot pulse generation circuit 27c. A one-shot pulse is generated, and accordingly, write mode designating signal WE from OR circuit 27e goes to H level.

  In write activation circuit 28, delayed page mode designating signal OPRWD is at L level, so that one-shot pulse generation circuit 28b is inactive and its output signal is at L level. On the other hand, the one-shot pulse generation circuit 28a is enabled, and a one-shot pulse signal is generated at a predetermined timing in response to the activation of the write mode designation signal WE, and the write from the OR circuit 28c is performed accordingly. Activation signal WX is activated. Thereafter, in the normal operation mode, every time a write command is applied at the rising edge of the clock signal CLK, the write mode designation signal WE and the write activation signal WX are respectively set in the form of a one-shot pulse signal. Activated at timing.

  FIG. 8 is a timing chart showing operations in page mode of write mode detection circuit 27 and write activation circuit 28 shown in FIG. Hereinafter, the operation of the circuit shown in FIG. 6 in the page mode will be described with reference to FIG.

  When the page mode is designated, the page mode designation signal OPRW from the set / reset flip-flop 24 shown in FIG. 5 becomes H level, and the delayed page from the half clock delay circuit 25 (see FIG. 5) is delayed by half a clock cycle. Mode designation signal OPRWD becomes H level. In accordance with the activation of delayed page mode designating signal OPRWD, page mode clock signal CLKPG from AND gate 26 shown in FIG. 5 is generated in reverse phase with clock signal CLK.

  In clock cycle #A, when write command ext / WE is applied at the rising edge of clock signal CLK, the output signal of gate circuit 27a shown in FIG. 6 rises, and one-shot pulse generation circuit 27c responds to a one-shot pulse. And write mode designation signal WE is activated accordingly. In write activation circuit 28, one-shot pulse generation circuit 28a is in a disabled state in accordance with activation of delayed page mode designation signal OPRWD, while one-shot pulse generation circuit 28b is in an enabled state. Therefore, one-shot pulse generation circuit 28b generates a one-shot pulse in accordance with activation of write mode designation signal WE, and in response to write from OR circuit 28c in the form of a one-shot pulse at a predetermined timing. An activation signal WX is generated.

  In clock cycle #B, when a write command is applied at the fall of clock signal CLK, gate circuit 27b raises this output signal in accordance with page mode clock signal CLKPG, and one-shot pulse generation circuit 27d responds to one-shot. And the write mode detection signal WE from the OR circuit 27e is activated. Therefore, one shot pulse generation circuit 28b generates write activation signal WX in the form of a one shot pulse.

  When a write command is applied at the rising edge of clock signal CLK in clock cycle #C, write signal detection circuit 27 causes the output signal of gate circuit 27a to rise in synchronization with the rise of clock signal CLK. The one-shot pulse generation circuit 27c generates a one-shot pulse, and the write mode detection signal WE is activated. In response, one-shot pulse generation circuit 28b again generates a one-shot pulse in accordance with activation of write mode designating signal WE, and write activation signal WX is activated.

  In the page mode, therefore, a write command can be applied in synchronization with both the rising edge and falling edge of clock signal CLK.

  Read mode detection circuit 29 and read column activation circuit 30 shown in FIG. 5 have the same configurations as write mode detection circuit 27 and write activation circuit 28 shown in FIG. In the configuration shown in FIG. 6, a read command ext / RE may be given instead of the write command ext / WE. By providing the one-shot pulse generation circuits 28a and 28b in the write activation circuit 28 separately for the normal operation mode and the page mode, the data write / read in the normal operation mode and the page mode are provided. The readout period and timing can be optimized.

  Data read activation signal SEN for activating internal read circuit 10 shown in FIG. 1 is activated in response to activation of read column activation signal RY from read column activation circuit 30 shown in FIG. The

  FIG. 9 schematically shows a structure of word line activation circuit 31 shown in FIG. In FIG. 9, a word line activation circuit 31 includes a one-shot pulse generation circuit 31a that generates a one-shot pulse signal PUR in response to activation of a read mode designation signal RE, a one-shot pulse signal PUR and a delayed page mode. An OR circuit 31b that receives the designation signal OPRWD and generates the word line activation signal RX is included.

  One shot pulse signal PUR from one shot pulse generation circuit 31a determines the word line selection period and timing in the normal operation mode, and has an activation period longer than a half clock cycle of clock signal CLK.

  FIG. 10 is a timing chart showing the operation in the page mode of the word line activation circuit 31 shown in FIG. Hereinafter, the operation of the word line activation circuit 31 shown in FIG. 9 will be described with reference to FIG.

  When an open row command designating a page mode is applied together with a read command designating data reading, read mode designating signal RE is activated, and then in response to the fall of clock signal CLK, delayed page mode designating signal OPRWD Is activated. In this first clock cycle, pulse signal PR is generated from one-shot pulse generation circuit 31a in accordance with activation of read mode detection signal RE, and word line activation signal RX is activated in accordance with this one-shot pulse signal PUR for addressing. The word line WL arranged corresponding to the selected row is driven to the selected state.

  Even if the pulse signal PUR is deactivated, the delayed page mode designating signal OPRWD is in the active state, so that the word line activation signal RX remains in the active state.

  A read command is applied at the rising edge of the clock signal CLK, and the read command is applied again in response to the next falling of the clock signal CLK. In this case, one-shot pulse generation circuit 31a generates one-shot pulse signal PUR in response to activation of read mode designation signal RE. Since the activation period of this one-shot pulse signal PUR is longer than a half clock cycle of clock signal CLK, pulse signal PUR is not applied to read mode designating signal RE generated in response to the fall of clock signal CLK. Not generated.

  In clock cycle # 2, when a read command is applied in response to the fall of clock signal CLK, one-shot pulse signal PUR is again generated from one-shot pulse generation circuit 31a. Even in this case, since delayed page mode designation signal OPRWD is in the active state, the state of word line activation signal RX is not changed and is maintained in the active state.

  In clock cycle # 3, in synchronization with the rise of clock signal CLK, a close row command for instructing the end of page mode and a read command for instructing data reading are applied. In this read command in clock cycle # 3, since pulse signal PUR is in an active state due to the read command in previous clock cycle # 2, a one-shot pulse is not newly generated in clock cycle # 3. After data reading is performed in response to the rise of clock signal CLK in clock cycle # 3 (by output signal RY of read column activation circuit 30 shown in FIG. 5), in response to the fall of clock signal CLK. Delay page mode designating signal OPRWD falls to L level, and pulse signal PUR also goes to L level. In response, the word line activation signal RX from the OR circuit 31b is deactivated, and the page mode ends.

  Read mode designation signal RE is generated from read mode detection circuit 29 shown in FIG. Read mode detection circuit 29 has a configuration similar to that of write mode detection circuit 27 shown in FIG. 6, and reads in accordance with a read command applied in synchronization with the rising and falling edges of clock signal CLK in the page mode. The mode designation signal RE is activated. The word line activation period in the normal operation mode is determined by using the one-shot pulse generation circuit 31a. As a result, the selected word line can be accurately maintained in the active state for a necessary period in both the normal operation mode and the page mode.

  FIG. 11 is a diagram schematically showing a configuration relating to the address control of main control circuit 2 shown in FIG. 1 and address input circuit 3. In FIG. 11, main control circuit 2 includes an OR circuit 36 that receives read mode designation signal RE and write mode designation signal WE, an OR circuit 36 that receives write activation signal WX and read column activation signal RY, A set / reset flip-flop 37 which is set in response to the rise of the output signal of circuit 35 and reset in response to the fall of the output signal of OR circuit 36 to generate column address latch instruction signal CAL; It includes an OR circuit 38 which receives an instruction signal CAL, a page mode designation signal OPRW and a delayed page mode designation signal OPOWD and generates a row address latch instruction signal RAL.

  Address input circuit 3 latches external address AD in response to activation of row address latch instruction signal RAL and generates internal row address signal RA, and when column address latch instruction signal CL is activated. Includes a column address latch circuit 3b which latches an external column address signal AD and generates an internal column address signal CA. A row address signal and a column address signal of external address signal AD are applied to row address latch circuit 3a and column address latch circuit 3b, respectively.

  FIG. 12 is a timing chart showing the operation of the circuit shown in FIG. The operation of the circuit shown in FIG. 11 will be described below with reference to FIG.

  In clock cycle # 0, an open row command and a read command are applied, read mode designation signal RE is activated, and read column activation signal RY is activated accordingly. At this time, page mode designation signal OPRW is activated, and accordingly, row address latch instruction signal RAL is activated, and row address latch circuit 3a is latched. When the read operation is completed in clock cycle # 0, read column activation signal RY is deactivated, and column address latch instruction signal CAL is deactivated accordingly. Therefore, in clock cycle # 0, column address signal CA is latched for a period from when read mode designating signal RE is activated until read column activation signal RY is deactivated.

  Page mode operation is performed in clock cycle # 3 after clock cycle # 1, and data writing / reading is executed at the rising and falling edges of clock signal CLK. In clock cycle # 1, a read command is applied in synchronization with the rising and falling edges of clock signal CLK, and column address latch instructing signal CAL is in accordance with inactivation of read mode designating signal RE and read column activation signal RY. In response, column address latch circuit 3b is latched for a half clock cycle period of clock signal CLK, and generates a new internal column address signal CA according to the applied column address signal.

  In each of clock cycles # 2 and # 3, a write command instructing data writing is applied in synchronization with the rising edge and falling edge of clock signal CLK, and in accordance with write mode designating signal WE and write activation signal WX. Column address latch instruction signal CAL is generated (activated) by set / reset flip-flop 37 shown in FIG. Therefore, also in this case, column address latch circuit 3b latches the column address signal in synchronization with each rising edge and falling edge of clock signal CLK, and generates internal column address signal CA.

  In this page mode operation, row address latch instruction signal RAL is in the active state and row address latch circuit 3a is in the latched state, so that internal row address signal RA does not change and the word line in the same row is in the selected state. Maintained.

  In clock cycle # 4, a close row command is applied together with a read command, page mode designation signal OPRW is deactivated, and delayed page mode designation signal OPRWD is deactivated in accordance with the fall of clock signal CLK. In clock cycle # 4, at the fall of clock signal CLK, column address latch instructing signal CAL is already inactive (data reading is performed in a half clock cycle), and row address latch instructing is performed. Signal RAL is deactivated in accordance with deactivation of delayed page mode designating signal OPRWD, and row address latch circuit 3a is released from the latched state.

  Using set / reset flip-flop 37, column address latch instructing signal CAL is activated in accordance with activation of read mode designating signal RE and write mode designating signal WE to latch the column address, and write activation signal WX or read column By deactivating the column address latch instruction signal CAL in response to the deactivation of the activation signal RY, the column selection period in the page mode and the normal operation mode is set to the optimum timing, and each column access Column address latch instruction signal CAL can be activated / deactivated in a cycle.

  FIG. 13 schematically shows a structure of a portion for generating word line selection signal WSL included in word line drive circuit 4 shown in FIG. In FIG. 13, a word line drive circuit 4 is activated in response to activation of a word line activation signal RX, decodes an internal row address signal RA, and generates a decode circuit 4a for generating a word line selection signal WSL. Including. The decode circuit 4a is provided corresponding to each word line, and the word line selection signal WSL is applied to a word line driver arranged on the corresponding word line.

  The word line activation signal RX is in an active state according to the page mode designation signal OPRW in the page mode, and the word line selection signal WSL for the same row is maintained in the active state from the decode circuit 4a, and the same row is selected. It is put.

  FIG. 14 schematically shows a structure of a portion for generating digit line selection signal DSLj included in digit line drive circuit 5 shown in FIG. In FIG. 14, digit line drive circuit 5 is activated in response to activation of write activation signal WX, decodes internal row address signal RA, and generates a digit line selection signal DSLj. including. Decoding circuit 5a is provided corresponding to each digit line DL shown in FIG. 2, and digit line selection signal DSLj is applied to a digit line driver arranged on the corresponding digit line. At the time of data writing, decode circuit 5a is activated, and digit line selection signal DSLj for the digit line corresponding to the selected row is driven to the selected state in accordance with row address signal RA in the latched state.

  FIG. 15 schematically shows a structure of a portion generating read column selection signal CSLRj included in read column selection circuit 6 shown in FIG. Read column select circuit 6 includes a decode circuit 6a provided corresponding to each bit line pair. Decode circuit 6a is activated when read column activation signal RY is activated, and decodes internal column address signal CA to generate read column select signal CSLRj. Read column select signal CSLRj is applied to a read column select gate and a source line driver provided for the corresponding bit line.

  Read column activation signal RY is activated at the time of data reading, and therefore read column selection signal CSLRj is activated only at the time of data reading.

  FIG. 16 schematically shows a structure of write column selection circuit 9 shown in FIG. In FIG. 16, write column select circuit 9 includes a decode circuit 9a provided corresponding to each bit line pair. Decode circuit 9a is activated when write activation signal WX is activated, and decodes internal column address signal CA to generate a write column selection signal CSLWj. Write column select signal CSLWj is applied to the bit line driver arranged in the corresponding column. As a result, the decode circuit 9a is activated only at the time of writing to perform a decoding operation, and can generate the write column selection signal CSLWj.

[Example of change]
FIG. 17 is a timing chart showing the operation in the page mode of the modification of the first embodiment of the present invention. Hereinafter, the operation in the page mode of the magnetic memory device shown in FIG. 2 will be described with reference to FIG.

  In clock cycle # 0, an open row command, a read command, and a write command are applied, external read address RDAD and write address WRAD are applied, row and read column address signals RA and CAR # 1, and write Column address signal CAW # 1 is generated. When the read command and the write command are applied in parallel, the external write instruction signal (write command) / WE and the external read instruction signal (read command) / RE are set to the L level, and the open low The command (page mode instruction signal) Open-Row is set to the H level. At this time, write data DIN # 1 for data writing is also provided.

  In clock cycle # 0, a column select operation is performed, read column select signal CSLR and write column select signal CSLW are driven to a selected state, read column select gate RCG is turned on, and corresponding bit line BL is connected to internal data line RDB1. And RDB2. For data writing, bit line drivers BDL and BDR for the selected column are activated. Read column address signal CAR # 1 and write column select signal CSLW # 1 define different columns. The source line of the read column is driven to the ground voltage level, while the source line of the write column maintains the power supply voltage level. Data can be written to and read from the bit lines in these different columns without adversely affecting each other. Since an open row command is applied, word line WL maintains the selected state even after data writing / reading.

  A read command is applied at the rise of clock signal CLK in clock cycle # 1, and read column address signal CAR # 2 is applied as read address RDAD at that time, and read column select signal CSLR designated by the selected column is driven to the selected state. Then, the data of the memory cell connected to the bit line of the selected column is read out.

  A write command is applied at the fall of clock signal CLK in clock cycle # 1, write column address signal CAW # 3 is applied as write address WRAD, and write data DIN # 3 is applied. In this case, write column selection signal CSLW corresponding to the selected column is driven to the selected state, the corresponding bit line driver and the data line of the selected row shown in FIG. 2 (not shown) are driven, and data DIN # 3 for the selected memory cell is driven. Is written. Although data DOUT # 2 is output in this cycle, data output and data input can be executed in parallel by using the DQ separation configuration in which the data output node is arranged separately from the data input node.

  A read command and a write command are applied at the rise of clock signal CLK in clock cycle # 2, and read column selection signal CSLR and write column selection signal CSLW are selected by column address signals CAR # 4 and CAW # 4 at that time, respectively. Driven to the state, data writing and reading are performed in parallel.

  A read command is applied in synchronization with the fall of clock signal CLK in clock cycle # 2, and read column select signal CSLR for the selected column is driven to the selected state in accordance with read column address signal CAR # 5 at that time, and the data Reading is performed. Read data DOUT # 4 is output at the fall of the clock signal of clock cycle # 2.

  In clock cycle # 3, a close row command and a write command are applied at the rise of clock signal CLK, write column select signal CSLW is driven to a selected state in accordance with write column address signal CAW # 6, and data DIN # 6 is written. Is executed. In this cycle, data DOUT # 5 of the memory cell specified by column address signal CAR # 5 applied in the previous cycle is output.

  In clock cycle # 3, word line WL is driven to a non-selected state in accordance with a close row command after completion of data writing.

  In other words, when the same word line is driven to the selected state and the read column address signal CAR and the write column address signal CAW specify different columns, data writing and reading are executed in parallel within the same clock cycle. can do. Thereby, data can be transferred at higher speed.

  FIG. 18 schematically shows structures of main control circuit 2 and address input circuit 3 in the modification of the first embodiment of the present invention. These main control circuit 2 and address input circuit 3 correspond to main control circuit 2 and address input circuit 3 shown in FIG. 1, respectively.

  In FIG. 18, main control circuit 2 is set in response to activation of read mode designating signal RE and reset in response to inactivation of read column activation signal RY, so that read column address latch instruction signal RCAL. Set / reset flip-flop 50 for generating the write column address latch and set in response to the activation of write mode designating signal WE and reset in response to the deactivation of write activation signal WX Set / reset flip-flop 51 for generating instruction signal WCAL, OR circuit 52 for receiving read mode designating signal RE and write mode designating signal WE, output signal of OR circuit 52, page mode designating signal OPRW, and delay page mode designating An OR circuit 53 that receives the signal OPRWD and generates a row address latch instruction signal RAL is included.

  Write mode designating signal WE and write activation signal WX are output from write mode detection circuit 27 and write activation circuit 28 shown in FIG. Read mode designating signal RE and read column activation signal RY are output from read mode detection circuit 29 and read column activation circuit 30 shown in FIG. Page mode designating signal OPRW and delayed page mode designating signal OPRWD are output by set / reset flip-flop 24 and half-clock delay circuit 25 shown in FIG.

  Address input circuit 3 is responsive to read column address latch instruction signal RCL to read column address latch circuit 55 for latching external read column address signal CAR # and generating internal read column address signal CAR, and write address latch Write column address latch circuit 56 that latches external write address signal CAW # in response to instruction signal WCAL to generate internal write column address signal CAW, and external row address in response to row address latch instruction signal RAL A row address latch circuit 57 for latching signal RA # and generating internal row address signal RA is included.

  Read column address signal CAR # and write column address signal CAW # are externally applied in parallel. Row address signal RA # is commonly applied to these writing and reading.

  When read mode is designated, set / reset flip-flop 50 maintains read column address latch instructing signal RCAL in an active state during a data read period, and read column address latch circuit 55 is in a latched state. Internal read column address signal CAR is generated in accordance with address signal CAR #. At the time of data writing, write column address latch instruction signal WCAL is activated by set / reset flip-flop 512, and write column address latch circuit 56 is in a latched state during the data write period, so that external write Internal write column address signal CAW is generated according to embedded column address signal CAW #.

  When data access is designated, row address latch instruction signal RAL is activated by OR circuit 53, and external row address signal RA # is latched as internal row address signal RA by row address latch circuit 57.

  The configuration shown in FIG. 5 can be used as a configuration for controlling other read column selection circuit, word line drive circuit, source line drive circuit, and bit line drive circuit of main control circuit 2. In addition, the configuration described with reference to FIGS. 13 to 16 is used for both driving the memory cell to the selected state and writing / reading data as well as the configuration of the circuit for generating the selection signal. be able to.

  FIG. 19 schematically shows a structure of data input / output circuit 11 in a modification of the first embodiment of the present invention. The data input / output circuit 11 shown in FIG. 19 corresponds to the input / output circuit 11 shown in FIG. Data input / output circuit 11 generates internal write data DIN from external write data DIN # and applies the same to bit line driving circuit, and internal read data DOUT supplied from the internal read circuit as an output enable signal. A data output circuit 62 for sequentially outputting as external data DOUT # in accordance with OEN is included.

  Data input circuit 60 is in a latch state in accordance with a write instruction during a data write operation, latches external write data and generates internal write data DIN. In the bit line driver circuit portion, the data write timing for the memory cell is adjusted in synchronization with the clock signal. Data output circuit 62 is activated at a predetermined timing in accordance with read column activation signal RY or in accordance with data read activation signal SEN shown in FIG. 1 in consideration of latency and page mode / normal operation mode. By providing data input circuit 60 and data output circuit 62 in parallel, data can be written and read in parallel, and high-speed data transfer can be realized.

  In the configuration shown in FIG. 18, row address latch circuit 57 is provided in common for data writing and data reading. However, by providing row address latch circuit 57 separately for data writing and data reading, a 2-port memory having separate read ports for data reading and write ports for data writing is realized. Can do.

  As described above, according to the first embodiment of the present invention, memory cells are coupled to the reference voltage source with respect to the source line corresponding to the read column when data is read with the word line maintained in the selected state. ing. Therefore, even if data is written with the word line maintained in the selected state, there is no outflow path for the bit line write current, and data can be written / read in page mode. High speed access is realized.

  Data need not be written / read in units of 2 bits. The number of write / read data bits is determined according to the number of bits of external data.

[Embodiment 2]
FIG. 20 schematically shows a whole structure of the magnetic memory device according to the second embodiment of the present invention. 20, the magnetic memory device includes memory cell arrays 100a and 100b capable of performing memory cell selection operation and data writing / reading independently of each other. Each of these memory cell arrays 100a and 100b has a configuration similar to that of the first embodiment. The memory cell array 100a constitutes the bank BKA, and the memory cell array 100b constitutes the bank BKB.

  For bank BKA, a row address signal from address latch circuit 102a is decoded, a row selection circuit 104a for generating a row selection signal, and a word line of memory cell array 100a according to a row selection signal output from row selection circuit 104a or A word / digit line drive circuit 106a for driving a digit line to a selected state; a write column selection circuit 108a for generating a write column selection signal for selecting a write column according to a column address signal from the address latch circuit 102a; Bit line drive circuit 110a for supplying a write current to a bit line of a selected column of memory cell array 100a in accordance with a write column selection signal from embedded column selection circuit 108a and write data from write data generation circuit 111a, and an address A read column selection signal is generated according to a column address signal from latch circuit 102a, and Read column selection circuit 112a for coupling the bit line corresponding to the selected column to internal read bus RB0, and at the time of data reading, internal read data is generated on main read data bus MRB according to the data read from read column selection circuit 112a An internal reading circuit 114a for controlling the operation of these banks BKA and a bank A control circuit 116a are provided. In this bank BKA, a source line driver circuit is also arranged as in the first embodiment, but FIG. 20 does not show it for the sake of simplicity.

  Similarly to the bank BKA, the bank BKB also includes an address latch circuit 102b, a row selection circuit 104b, a word / digit line drive circuit 106b, a write column selection circuit 108b, a bit line drive circuit 110b, a write data generation circuit 111b, A read column selection circuit 112b, an internal read circuit 114b, and a bank B control circuit 116b are provided. Also in memory cell array 100b, the source line driver circuit is arranged as in the first embodiment, but is not shown in FIG. 20 for the sake of simplicity.

  Data write / read operations of these banks BKA and BKB are controlled by bank A control circuit 116a and bank B control circuit 116b, respectively. The peripheral circuit configuration of memory cell arrays 100a and 100b is substantially the same as that of the first embodiment. In bank A control circuit 116a and bank B control circuit 116B, data is read according to the self-reference method at the time of data reading. Therefore, the control signal generation sequence at the time of data reading is different from that of the first embodiment.

  The magnetic memory device further includes a main control circuit 120 that takes in an external command CMD in synchronization with a clock signal CLK, and generates an operation mode designation signal MODE, an output activation signal OE, and an input activation signal IE; An address input latch 122 that generates an internal address signal by latching an external address signal AD in accordance with a latch instruction signal (not shown) from the main control circuit 120, and an external input in accordance with a latch instruction signal from the main control circuit 120. Bank address latch 124 that latches bank address signal BAD to generate an internal bank address signal, and data that generates external read data Q from data on main read data bus MRB in accordance with output activation signal OE from main control circuit 120 Output activation signal from output circuit 126 and main control circuit 120 And generates an internal write data from external data D according to E, the write data generation circuit 111a and 111b, a data input circuit 128 for transmitting through the main write data bus MWB.

  The internal address signal from address input latch 122 is applied to address latch circuits 102a and 102b, and the bank address signal from bank address latch 124 is applied to bank A control circuit 116a and bank B control circuit 116b. These bank control circuits 116a and 116b are activated when the bank address signal from bank address latch 124 designates a corresponding bank, and perform necessary control for reading or writing data. The operation is performed according to the operation mode designation signal MODE from the control circuit 120.

  FIG. 21 shows a structure of a data read cycle at the time of self-reference type data read. As shown in FIG. 21, the data read operation includes a first cycle Read # 1 and a second cycle Read # 2. In first cycle Read # 1, storage data in the memory cell is read and latched, and then fixed data ("0") is written. In the second cycle Read # 2, the read fixed value data is read, the internal read data is generated based on the comparison between the previously latched stored data and the read fixed value data, and the internal read data is stored in the original memory. A restore is performed to write to the cell.

  By writing and reading fixed value data and comparing it with the original stored data, the sense amplifier (internal read circuit) can cancel out the deviation in the characteristics of the memory cells appearing in both the fixed value data and the stored data. Therefore, accurate internal read data can be generated, and the read margin can be improved.

  FIG. 22 is a signal waveform diagram representing an operation during data reading of the magnetic memory device shown in FIG. FIG. 22 shows a waveform at the time of data reading in one bank. Since memory cell arrays 100a and 100b have the same configuration as in the first embodiment, the signals shown in FIG. 2 are used as signals. Hereinafter, the data read operation of the magnetic memory device shown in FIG. 20 will be briefly described with reference to FIG.

  At the time of data reading, read mode designating signal RE is generated from main control circuit 120 as operation mode designating signal MODE and applied to bank A control circuit 116a and bank B control circuit 116b. At the same time, the bank control circuit provided for the selected bank is activated in accordance with the bank address signal applied from bank address latch 124 to generate a control signal necessary for data reading. In accordance with the activation of read mode designating signal RE, first cycle Read # 1 starts in the selected bank, and first cycle activation signal READ1 is driven to the active state. In accordance with activation of first cycle activation signal READ1, read activation signal RDEN (corresponding to signals RX and RY) is activated, word line WL is driven to a selected state, and read column selection signal CSLR is read column. Generated by the selection circuit (112a, 112b), the selected memory cell data is read and latched by the corresponding internal reading circuit (114a, 114b).

  After the read activation signal RDEN becomes inactive after a predetermined period of time, the write activation signal WREN (corresponding to the signal WX) is driven to the active state, and the corresponding word / digit line drive circuit is connected to the digit line DL. Current is supplied by (106a, 106b), a write column selection signal is generated by write column selection circuits (108a, 108b), and fixed value data “0” is generated by corresponding bit line drive circuits 110a, 110b. A current is supplied to the selected bit line in the writing direction. When this fixed value data is written, write activation signal WREN is deactivated and supply of write current to selected digit line DL and bit line BL is stopped. At this time, as in the first embodiment, the word line WL is maintained in the selected state. When the writing of the fixed value data is completed, the first cycle activation signal READ1 is deactivated and the first cycle Read # 1 is completed.

  In response to the deactivation of the first cycle activation signal READ1, the second cycle activation signal READ2 is activated and the second cycle Read # 2 starts. In response to activation of second cycle activation signal READ2, read activation signal RDEN is activated again, and read column selection signal CSLR is generated in accordance with the latched address signal (word line WL maintains the selected state). ) By activation of read column selection signal CSLR, fixed value data written in the selected memory cell is read out by the corresponding internal read circuit and compared with the stored data read in the first cycle Read # 1. And internal read data is generated.

  When read activation signal RDEN is deactivated and read column selection signal CSLR is deactivated, write activation signal WREN is activated again, and the data read by the internal read circuit is transferred to the original memory cell. Restore operation to write to is executed.

  In this restore operation, digit line DL and bit line BL are selected again according to the latched address signal, and a write current is supplied to selected digit line DL and selected bit line BL according to the read data. When this restore operation is completed, second cycle activation signal READ2 is deactivated, second cycle Read # 2 is completed, and one data read cycle for internally reading data is completed.

  The driving of the word line WL to the inactive state may be performed in response to the deactivation of the read activation signal RDEN in the second cycle Read # 2, and the deactivation of the write activation signal WREN. Similarly, when the internal circuit is reset to the initial state in response to the activation, the word line WL may be driven to the inactive state.

  FIG. 23 shows a data read sequence of the magnetic memory device according to the second embodiment of the present invention. In FIG. 23, four data read cycles # 1 to # 4 are shown.

  In synchronization with the rise of clock signal CLK, a read command is applied to bank BKA, and word line WL # 1 is driven to a selected state in accordance with address signal Add # 1 at that time to read data. Here, word lines WLA and WLB generically indicate the word lines of banks BKA and BKB. The bank BKA is specified when the bank address BAD is “0”, and the bank BKB is specified when the bank address BAD is “1”. After reading the stored data of the memory cell connected to word line WL # 1, writing to the selected memory cell with fixed value “0” is performed.

  In second cycle Read # 2 for word line WL # 1, the fixed value data written in the first cycle is read from the memory cell on word line WL # 1, and the internal read data is the main read data. Data Dout # 1 is output as external data Q after being read on bus MRB. When this external data is output, the read data on internal read data bus MRB is written into the original memory cell, and the stored data is restored.

  At the time of execution of second cycle Read # 2 of word line WL # 1, a read command instructing data reading for bank BKB is applied together with address signal Add # 2 in accordance with the rise of clock signal CLK. As a result, the word line WL # 2 in the addressed row of the word lines WLB in the bank BKB is driven to the selected state, and the storage data read, the fixed value data write, and the first value read in the first cycle Read # 1 The reading of the fixed value data and the rewriting (restoring) of the read data in two cycles Read # 2 are executed.

  Thereafter, in read cycles # 3 and # 4, data reading is instructed to banks BKA and BKB according to address signals Add # 3 and Add # 4, and data RD # 2 and RD # 3 are applied to internal main read data bus MRB. Data is read at each clock cycle, and data Dout # 2 and Dout # 3 are output as external data Q. Further, rewriting of the original memory cells of data RD # 2 and RD # 3 of these internal read data buses MRB is executed.

  Therefore, when data reading of this self-reference method is performed and two clock cycles are required for data reading, the data reading latency is set to two clock cycles by alternately giving data reading instructions to bank BKA and bank BKB. In this case, after two clock cycles have elapsed from the first read access cycle # 1, data Q can be output every clock cycle, and data can be read at high speed.

  As indicated by a broken line in FIG. 23, the word line may be driven to a non-selected state when writing fixed value data. When the word line is driven to a non-selected state at the time of writing the fixed value data, a configuration in which the source line, which will be described later as a modified example, is fixed to the ground voltage can be applied as the memory array structure, and the array structure is restricted. Is reduced.

  FIG. 24 shows an example of the configuration of bank A control circuit 116a and bank B control circuit 116b shown in FIG. Since these bank A control circuit 116a and bank B control circuit 116b are different only in the logic of the bank address signal applied and have the same internal configuration, in FIG. 24, these bank A control circuit 116a and bank B control circuit 116b are the same. The B control circuit 116 b is indicated by a bank control circuit 116.

  In FIG. 24, bank control circuit 116 is set in response to rising of the output signal of AND gate 150 receiving read mode designating signal RE and bank address signal BAD (or / BAD), and clock signal CLK A counter / counter 151 that counts the output of the AND gate 150 and is set in response to the rise of the output signal of the AND gate 150 and reset according to the count-up signal CUP from the ring counter 151 to output the first cycle activation signal READ1 The flip-flop 152 is set in response to the fall of the first cycle activation signal READ1, and is reset according to the count-up signal CUP from the ring counter 151 to output the second cycle activation signal READ2. Flip-flop 153, an OR circuit 154 receiving these activation signals READ1 and READ2, and a one-shot that outputs read activation signal RDEN in the form of a one-shot pulse in response to the rise of the output signal of OR circuit 154 A pulse generation circuit 155 and a one-shot pulse generation circuit 156 that generates a write activation signal WREN in a one-shot pulse form in response to a fall of the output signal of the OR circuit 154 are included.

  When activated, the ring counter 151 activates the count-up signal CUP when the count value of the clock signal CLK reaches a predetermined value, and performs the count operation from the initial value again. The ring counter 151 is deactivated in response to the fall of the second cycle activation signal READ2, and stops the count operation.

  In the configuration of bank control circuit 116 shown in FIG. 24, when a read operation is instructed to the corresponding bank, the output signal of AND circuit 150 becomes H level, ring counter 151 is activated, and the clock signal Count CLK. The set / reset flip-flop 152 maintains the first cycle activation signal READ1 in an active state until the count-up signal CUP is supplied from the ring counter 151. In response to the activation (rising) of first cycle activation signal READ1, the output signal of OR circuit 154 rises to the H level. In response to the rise of the output signal of OR circuit 154, read activation signal RDEN from one shot pulse generation circuit 155 is activated, word line selection and read column selection are performed, and storage data is read out. Executed.

  When read activation signal RDEN is deactivated after a predetermined time has elapsed, write activation signal WREN from one shot pulse generation circuit 156 is activated, a write column selection signal is generated, and digit line selection is performed. The fixed value data is written. When this first cycle is completed, the count-up signal CUP is generated from the ring counter 151, the set / reset flip-flops 152 and 153 are both reset, the first cycle activation signal READ1 is deactivated, and then Second cycle activation signal READ2 is activated, and read activation signal RDEN and write activation signal WREN are activated again for a predetermined period by one-shot pulse generation circuits 155 and 156, respectively.

  When the read cycle is completed, the second cycle activation signal READ2 is deactivated by the count up signal CUP from the ring counter 151, and the ring counter 151 stops the counting operation.

  In the configuration shown in FIG. 24, word line WL may be maintained in the selected state during the activation period of read activation signal RDEN. Alternatively, after the word line WL is driven to the selected state, when the second cycle activation signal READ2 is activated, the word line WL is driven to the unselected state in response to the deactivation of the write activation signal WREN. May be.

  FIG. 25 shows an example of the configuration of write data generation circuits 111a and 111b shown in FIG. Since these write data generation circuits 111a and 111b have the same configuration, in FIG. 25, the write data generation circuit 111 shows these write data generation circuits 111a and 111b.

  In FIG. 25, the write data generation circuit 111 is activated when the first cycle activation signal READ1 is activated, and outputs the fixed value data “0” and the activation of the second cycle activation signal READ2. Activated at the time of activation, transmitting tristate buffer 162 transmitting data on main read data bus MRB, NOR gate 163 receiving first and second cycle activation signals READ1 and READ2, and the output signal of NOR gate 163 being H It includes a tristate buffer 164 that is activated when the level is reached and transfers data on the main write data bus MWB. Outputs of these tri-state buffers 160, 162 and 164 are coupled in common, and the output data is transmitted to the bit line driving circuit of the corresponding bank.

  In the configuration of the write data generation circuit shown in FIG. 25, in the first cycle, tristate buffer 160 is activated and fixed value data “0” is transmitted to the corresponding bit line drive circuit. In the second cycle, tristate buffer 162 transfers the data on main read data bus MRB to the corresponding bit line drive circuit, and the stored data is restored. When the output signal of NOR gate 613 is at H level, activation signals READ1 and READ2 are both inactive, and data write is designated. At that time, main write data bus MWB Internal write data is transmitted to the corresponding bit line drive circuit.

  Thereby, in each cycle, fixed value data can be written and stored data can be restored. Writing of these data is executed in the bit line driving circuit in accordance with activation of write activation signal WREN.

  Note that the configuration of the above-described Patent Document 1 or Patent Document 2 may be used as the configuration of the internal readout circuit including the sense amplifier and the like. The internal readout circuit can be formed by the latch circuit and the comparison circuit.

[Modification 1]
FIG. 26 schematically shows a structure of memory cell M according to the first modification of the second embodiment of the present invention. In memory cell M shown in FIG. 26, source line SL to which access transistor ATR is coupled is always coupled to the ground node. When memory cell M shown in FIG. 26 is used, word line WL is driven to a non-selected state during data writing. That is, the selection period of word line WL is determined by the activation period of read activation signal RDEN. Even when the memory cell M shown in FIG. 26 is used, when data is read by the self-reference method, data can be read every clock cycle by alternately accessing the banks.

[Modification 2]
FIG. 27 schematically shows a structure of a memory cell according to the second modification of the second embodiment of the present invention. In FIG. 27, a memory cell M is formed of a variable magnetoresistive element VRE disposed between a bit line BL and a word line WL, and no read selection transistor is disposed. The memory cell M is arranged at the intersection of the word line WL and the bit line BL, and is called a so-called “cross point” cell. Digit lines and source lines are not arranged.

  At the time of data writing, a write current is supplied using word line WL as a digit line, and a write current is also supplied to bit line BL. Therefore, at the time of data writing, a write current flows between the word line WL and the bit line BL through the memory cell M, a magnetic field defect may occur, and the write margin may be reduced. For this reason, the resistance value of the variable magnetoresistive element VRE of the memory cell M is sufficiently increased, and the magnetoresistance ratio (ratio of magnetoresistance between the high resistance state and the low resistance state) is decreased (for example, 20%). Therefore, when such a high-resistance memory cell M is used, when data is read, the read current cannot be driven sufficiently, and the read cycle time becomes long. However, by reading data alternately in banks in the interleave manner as described above, the read cycle time can be effectively shortened and high-speed data reading can be performed. Data writing is simply the setting of the magnetization direction by an induced magnetic field, which is realized within a sufficiently short time compared to reading, and can be inserted between data reading cycles.

[Modification 3]
FIG. 28 schematically shows a structure of a memory cell M according to the third modification of the second embodiment of the present invention. The memory cell M shown in FIG. 28 includes a variable magnetoresistive element VRE and a PN diode DDE connected between the variable magnetoresistive element VRE and the word line WL. The PN diode DDE has an anode connected to the variable magnetoresistive element VRE and a cathode connected to the word line WL. Usually, the PN diode DDE is made of impurity-doped silicon. The other end of the variable magnetoresistive element VRE is connected to the bit line BL.

  In the configuration of the memory cell shown in FIG. 28, a write current is supplied to selected word line WL and selected bit line BL at the time of data writing. In this case, the PN diode DDE becomes conductive, and there is a possibility that the write current flows from the bit line BL to the word line WL. Therefore, also in the configuration of memory cell M shown in FIG. 28, the resistance value of variable magnetoresistive element VRE is made sufficiently high.

  In data reading, selected word line WL is driven to the ground voltage level, and unselected word line WL is maintained at the power supply voltage level. In the selected memory cell, the PN diode DDE is in a conductive state, and in the non-selected memory cell, the PN diode DDE is in a reverse bias state and is in a non-conductive state. In the selected memory cell, a read current flows from bit line BL to word line WL via variable magnetoresistive element VRE and PN diode DDE, and data is read according to the read current.

  In the configuration of memory cell M shown in FIG. 28 as well, data is normally read by the self-reference method. However, since the electric resistance value of variable magnetoresistive element VRE is sufficiently high, it takes a long time to read data, and data can be read at high speed by reading data in an interleaved manner. Data writing only reverses the magnetization direction of the variable magnetoresistive element VRE, and data writing can be performed in an extremely short time.

  In the memory cell M shown in FIG. 28 as well, the variable magnetoresistive element VRE and the PN diode DDE have a cross point cell structure arranged at the intersection of the bit line BL and the word line WL.

  As described above, according to the second embodiment of the present invention, in a magnetic memory device that reads data by a self-reference method, data is read by accessing in a bank interleaved manner. Internal reading can be performed, and high-speed data reading can be realized.

[Embodiment 3]
FIG. 29 schematically shows an overall configuration of the magnetic memory device according to the third embodiment of the present invention. In the magnetic memory device shown in FIG. 29, memory cells are arranged in a matrix in memory cell array 200. As the configuration of the memory cell array 200, the configuration of the memory cell array shown in the first embodiment may be used, and the memory cells M shown in FIGS. 26 to 28 may be arranged in a matrix. Therefore, in FIG. 29, since the configuration of the peripheral circuit differs depending on the configuration of the memory cell array 200, the source line driving circuit, the word line driving circuit, the digit line driving circuit, and the bit line driving circuit are specified as the peripheral circuits. Not shown.

  For this memory cell array 200, a row selection drive circuit 204 for driving a row of the memory cell array 200 to a selected state in accordance with a row address signal from the address input circuit 202, and an address signal from this address input circuit 202 (this path is not shown) ), A column selection circuit 206 for selecting a column of the memory cell array 200 and a write circuit 208 for writing data to the selected memory cell of the memory cell array 200 are provided.

  When memory cell array 200 has a configuration similar to that of the first embodiment, row selection drive circuit 204 includes a word line drive circuit and a digit line drive circuit, and column selection circuit 206 includes a read column selection signal generation circuit. Includes a write column selection signal generation circuit and a read column selection circuit. Write circuit 208 includes a write data generation circuit and a bit line drive circuit.

  This magnetic memory device further includes an internal read circuit 210 coupled to an internal read data bus RDB for transferring data of 32-bit memory cells simultaneously selected from column selection circuit 206, and main read from internal read circuit 210. A parallel-serial conversion circuit 212 that converts 32-bit data transferred via the data bus MRDB into 16-bit data and sequentially outputs the data; a data output circuit 214 that outputs 16-bit data from the parallel-serial conversion circuit 212; A data input circuit 216 for generating 16-bit internal write data in accordance with external 16-bit data is included. Internal write data from data input circuit 216 is applied to write circuit 208 via 16-bit write data bus WDB.

  In order to control the internal read operation, a main control circuit 218 that generates control signals required for various internal operations in accordance with an external command CMD, and internal data read and output in accordance with a read mode instruction signal RE from the main control circuit 218 A read control circuit 220 that controls necessary operations is provided. Read control circuit 220 controls the internal read operation so that internal read data is generated according to the self-reference method.

  The column address signal bit CA0 is given to the parallel-serial conversion circuit 212. When 32-bit data is generated, which of 16-bit data of the even address and 16-bit data of the odd address is output first. This is to decide.

  FIG. 30 shows a structure of a data read cycle in the third embodiment of the present invention. Since internal read data is generated by the self-reference method, the data read cycle reads and latches data stored in a 32-bit memory cell, and then writes 16-bit fixed data “0” to the 32-bit memory cell. A first cycle Read # F in which a read operation is performed, an internal read operation for generating internal read data based on a comparison between the read of 32-bit fixed value data “0” and the previously read storage data This includes a second cycle Read # S in which the restored operation of writing the read 32-bit data into the original memory cell in 16-bit units is performed.

  Internal write data bus WDB has a 16-bit width, and write circuit 208 also writes data in units of 16 bits. Therefore, at the time of writing 32-bit data, writing of 16-bit data is executed twice.

  To perform the restore operation, main read data bus MRDB is coupled to write circuit 208 as shown in FIG.

  FIG. 31 shows an example of a data read sequence according to the third embodiment of the present invention. FIG. 31 shows an operation sequence when first and second cycles Read # F and Read # S correspond to one clock cycle period of clock signal CLK, respectively.

  In access cycle # 1, a data read instruction is given in cycle C # 0 of clock signal CLK, and first and second cycles Read # F and Read # S are sequentially performed in accordance with address signal Add # 1 at that time. Internal read data is generated in internal read circuit 210 shown in FIG. 29, and 32-bit data Q # 1 is output to main read data bus MRDB in clock cycle C # 1. This 32-bit data Q # 1 is latched in parallel / serial conversion circuit 212, and the output order of 16-bit data is set according to column address signal bit CA0. In clock cycles C # 2 and C # 3, 16-bit data Q # 1 is set. # 1F and Q # 1S are output, respectively.

  Data read instruction is again applied in clock cycle C # 2, and memory cell data is read in accordance with address signal Add # 2 at that time. In access cycle # 2, read access subcycles Read # F and Read are read. When #S is executed, 32-bit data Q # 2 is generated by internal reading circuit 210 and taken into parallel / serial conversion circuit 212. From clock cycle C # 4, 16-bit data is subsequently selected in accordance with column address signal bit CA0 in parallel / serial conversion circuit 212, and data Q # 2F is output.

  Therefore, when data is read in accordance with the self-reference method, when two clock cycles are required for data reading, a data read instruction is given every two clock cycles, so that the data is internally read in parallel with the internal read data operation. A data output operation can be performed. After two clock cycles have elapsed from the first access cycle, external data Q can be output every clock cycle, and high-speed data transfer can be realized.

  FIG. 32 schematically shows a structure of a portion for generating a read column selection signal included in column selection circuit 206 shown in FIG. In FIG. 32, column selection circuit 206 receives OR column GT1 which generates read column selection signal CSLR1 in response to read column selection fast signal CSLRF0 and read column selection fast signal CSLRF1 generated from a read column decoder (not shown), An OR gate GT2 that receives column select first signal CSLRF1 and read column select fast signal CSLRF2 and generates read column select signal CSLR2 is included.

  In the portion that generates this read column selection signal, read column selection signal CSLR (i + 1) is generated in accordance with read column selection fast signals CSLRFi and CSLRF (i + 1). As a result, 32-bit memory cells can be simultaneously selected in accordance with a column address signal designating 16-bit memory cells having arbitrary column addresses.

  FIG. 33 shows a connection between a bit line and internal read data bus RDB. In FIG. 33, 16-bit even bit line group BLe is coupled to 16-bit wide even read data bus RDBe via read column select gate circuit 230e responsive to even column select signal CSLRe. On the other hand, the 16-bit odd bit line group BLo is coupled to an odd read data bus RDBo having a 16-bit width via an odd column read selection gate circuit 230o which is turned on in accordance with an odd read column selection signal CSLRo. These even data bus RDBe and odd read data bus RDBo form an internal read data bus RDB coupled to internal read circuit 210 shown in FIG. 29, and 32-bit memory cell data is transferred to internal read circuit 210. The

  FIG. 34 schematically shows a structure of a portion for generating a write column selection signal included in column selection circuit 206 shown in FIG. FIG. 34 representatively shows a configuration of a portion for generating write column selection signals CSLW0 to CSLW2.

  In FIG. 34, column selection circuit 206 selects one of write column selection fast signals CSLWF0 and CSLWF1 generated from a write column decoder (not shown) according to switching signal φSW to generate a write column selection signal CSLW1. SWK1 includes a switch circuit SWK2 that selects one of write column selection fast signals CSLWF1 and CSLW2 generated from a write column decoder and generates a write column selection signal CSLW2. Write column selection signal CSLW0 is generated by switch circuit SWK0 that selects one of the ground voltage and write column selection fast signal CSLWF0 in accordance with switching signal φSW.

  Switch circuits SWK1 and SWK2 select the corresponding write column selection first signal when switching signal φSW is at a first logic level of, for example, L level, and switching signal φSW is at a second logic level of, for example, H level. When set to, the preceding write column selection fast signal is selected. Switch circuit SWK0 selects corresponding write column selection fast signal CSLWF0 when switching signal φSW is at the first logic level, and selects the write voltage for the previous stage when switching signal φSW is at the second logic level. Select as signal.

  Therefore, first, when write column selection signal CSLWi is generated in accordance with write column selection fast signal CSLWFi generated based on the applied column address signal, and the logic level of switching signal φSW is switched, the previous write Write column select signal CSLW (i + 1) is driven to a selected state in accordance with column select fast signal CSLWFi. As a result, it is possible to write and restore 32-bit fixed value data using a 16-bit data bus.

  FIG. 35 schematically shows a configuration of read control circuit 220 shown in FIG. Read control circuit 220 shown in FIG. 35 is configured using the configuration of bank control circuit 116 shown in FIG. The read control circuit 220 differs from the bank control circuit shown in FIG. 24 in the following points. That is, read mode designating signal RE is applied to set input S of set / reset flip-flop 152 and set input S of ring counter 151.

  The one-shot pulse generation circuit 235 that generates a one-shot pulse signal in response to the fall of the output signal WREN1 of the one-shot pulse generation circuit 156, and the output signals of the one-shot pulse generation circuits 156 and 235 In response, an OR circuit 236 for generating a write activation signal WREN is provided. A one-shot pulse generation circuit 235 outputs a switching signal φSW.

  The other configuration of read control circuit 220 shown in FIG. 35 is the same as that of the bank control circuit shown in FIG. 24, and the corresponding portions are denoted by the same reference numerals and detailed description thereof is omitted.

  FIG. 36 is a timing chart representing an operation of read control circuit 220 shown in FIG. Referring to FIG. 36, the operation of read control circuit 220 shown in FIG. 35 will be briefly described.

  When the read mode is designated, read mode designation signal RE is activated, and first cycle activation signal READ1 is activated by set / reset flip-flop 152. In accordance with activation of first cycle activation signal READ1, one-shot pulse generation circuits 155, 156 and 135 sequentially generate one-shot pulse signals, read activation signal RDEN, write activation signal WREN1 and switching Signal φSW is sequentially activated. According to the output pulse signals of one-shot pulse generation circuits 156 and 235, write activation signal WREN is generated twice from OR circuit 236, and data writing in units of 16 bits is executed.

  When set / reset flip-flop 152 is reset according to count-up signal CUP of ring counter 151, second cycle activation signal READ2 is activated, and one-shot pulse generation circuits 155 and 156 are again activated according to the output signal of OR circuit 154. And 235 sequentially activates read activation signal RDEN, pulse signal WREN1, and switching signal φSW. At the time of writing in each cycle, first, data can be written in the 16-bit memory cell of the selected column according to the column address signal, and then the same data can be written in the 16-bit memory cell of the adjacent column.

  In accordance with write activation signal WREN, the write column decode circuit included in column selection circuit 206 shown in FIG. 29 is activated, and the bit line drive circuit is activated. When digit line DL is provided, digit line DL is also activated during data writing.

  The column address signal from the address input circuit 202 is latched, and during the internal data read period, an adjacent column address is generated by adding 1 to the latched column address signal, and the latched column address and the adjacent column address are switched. A configuration in which the signal φSW is switched and given to the write column selection circuit for decoding may be used.

  FIG. 37 schematically shows structures of internal reading circuit 210 and parallel-serial conversion circuit 212 shown in FIG. In FIG. 37, an internal read circuit 210 is coupled to a 16-bit even read data bus RDBe to generate a 16-bit internal data generation circuit 240e for generating 16-bit internal data, and an odd-read read data bus RDBo having a 16-bit width. A 16-bit internal data generation circuit 240o that generates 16-bit internal data is combined. These 16-bit internal data generation circuits 240e and 240o have any circuit configuration that reads internal data in accordance with the self-reference method, latches data read from the memory cell, and then fixes the fixed value data read from the memory cell. And latch data may be compared.

  The parallel-serial conversion circuit 212 latches according to the latch circuit 242e that latches the output data of the 16-bit internal data generation circuit 240e, the latch circuit 242o that latches the output data of the 16-bit internal data generation circuit 240o, and the column address signal bit CA0. It includes a multiplexer 244 that selects one of circuits 242e and 242o and provides 16-bit data to data output circuit 214 shown in FIG.

  Column address signal bit CA0 applied to multiplexer 244 specifies an even column or an odd column, and in the first clock cycle, 16-bit data of latch circuits 242e and 242o corresponding to the even column or the odd column is selected, and the next column The column address bit CA0 is inverted in the clock cycle, and the remaining 16-bit data is selected.

  The following configuration can be used as a configuration for selecting 16-bit data from 31-bit data for each clock cycle. Based on the second cycle activation signal READ2, a parallel / serial conversion activation signal is generated, and the parallel / serial conversion activation signal is shifted every clock cycle so that the column address signal bit CA0 and its inverted signal (/ CA0) are sequentially selected and supplied to the selection circuit of the multiplexer 244. In the first clock cycle, 16-bit data of the memory cell designated by column address signal bit CA0 is selected, and in the next clock cycle, the remaining 16-bit data is selected according to complementary column address signal bit / CA0.

  FIG. 38 schematically shows a structure of a write data generation circuit included in write circuit 208 shown in FIG. The write data generation unit shown in FIG. 38 is configured using the configuration shown in FIG. In write circuit 208 shown in FIG. 38, 16-bit main even read data bus MRBe and 16-bit main odd read data bus MRBo are selected in accordance with column address signal bit CA0 and switching signal φSW to generate 16-bit data. A selection circuit 250 is provided for supplying the generated 16-bit data to the tri-state buffer 162. The other configuration of the write data generation unit shown in FIG. 38 is the same as the configuration of the write data generation circuit shown in FIG. 25, and corresponding portions are denoted by the same reference numerals and detailed description thereof is omitted. .

  Select circuit 250 selects one of read data buses MRBe and MRBo according to column address signal bit CA0 when switching signal φSW is at the first logic level (L level). When switching signal φSW is at the second logic level (H level), column address signal bit CA0 is inverted to select the other of read data buses MRBe and MRBo. As a result, data is first written to the memory cell specified by column address signal bit CA0, and then the remaining 16-bit data is written to the memory cell in the adjacent column. Restoration can be performed.

  In the above configuration, 32-bit data is converted into 16-bit serial data and output. However, the relationship between the bit width of the internal read data and the bit width of the external output data may be appropriately determined according to the number of clock cycles required for reading the internal data.

  As described above, according to the third embodiment of the present invention, at the time of data reading, internal read data having a bit width wider than the bit width of the external output data is generated internally, and this internal read data is Even if it takes a long time to create internal read data, the data can be output to the outside every clock cycle, and data can be transferred at high speed. Can be performed.

[Embodiment 4]
FIG. 39 schematically shows an entire configuration of the magnetic memory device according to the fourth embodiment of the present invention. In the magnetic memory device shown in FIG. 39, one word is composed of 32 bits. Data input circuit 328 receives 32-bit data D and transfers 16-bit upper data and 16-bit lower data to 16-bit upper main write data bus UMWB and 16-bit lower main write data bus LMWB, respectively.

  Data output circuit 326 is coupled to 16-bit main read data bus MRB and outputs 16-bit data Q.

  When data is written, 32-bit data is written, and when data is read, 16-bit data is read. Therefore, the memory cell array includes a memory cell array 300a storing upper 16-bit data and lower 16-bit data. The memory cell array 300b to be stored is divided.

  In order to designate the upper and lower 16-bit data, the upper data enable signal UPE and the lower data enable LWE are latched under the control of the main control circuit 120, and the upper data activation signal UPEN and the lower data activation An input latch circuit 320 for generating the signal LWEN is provided.

  An upper block control circuit 316a and a lower block control circuit 316b are provided for memory cell arrays 300a and 300b, respectively. Upper block control circuit 316a controls operations necessary for writing / reading data to / from memory cell array 300a according to upper data activation signal UPEN from input latch circuit 320 and operation mode designating signal MODE from main control circuit 120. On the other hand, lower block control circuit 316b controls writing / reading of data to / from memory in memory cell array 300b in accordance with lower data activation signal LWEN and operation mode designation signal MODE from main control circuit 120.

  Since internal data is read according to the self-reference method, a write data generation circuit 311a is provided for memory cell array 300a, and a write data generation circuit 311b is provided for memory cell array 300b. Write data generation circuit 311a receives the data on 16-bit main read data bus MRB and the data on 16-bit upper main write data bus UMWB, and based on the fixed value and the internal read data at the time of data reading Write data is generated, and write data is generated according to the data on the 16-bit upper main write data bus UMWB at the time of data writing. Write data generation circuit 311b similarly generates write data according to fixed value data and data on 16-bit main read data bus MRB at the time of data reading, and at the time of data writing mode, 16-bit lower main writing Write data is generated according to the data on the embedded data bus LMWB.

  The upper block control circuit 316a and the lower block control circuit 316b are activated according to the upper data activation signal UPEN and the lower data activation signal LWEN, respectively. The bank control circuit in the magnetic storage device having the bank configuration shown in FIG. The activation signals UPEN and LWEN are received instead of the bank address signal. Therefore, the configuration of the peripheral circuit for selecting the rows and columns of memory cell arrays 300a and 300b is the same as the configuration shown in FIG. 20, and the corresponding parts are denoted by the same reference numerals and detailed description thereof is omitted.

  In the magnetic memory device shown in FIG. 39, when data is written, both upper data enable signal UPE and lower data enable signal LWE are activated, and 32-bit data is written. At the time of data reading, upper data enable signal UPE and write data enable signal LWE are activated alternately to read 16-bit data. At the time of this data reading, the page mode shown in the first embodiment may be used, and as shown in the second and third embodiments, the row and column addresses are given in each access cycle to read the data. May be performed.

  FIG. 40 shows a data read sequence of the magnetic memory device shown in FIG. Hereinafter, the data read operation of the magnetic memory device shown in FIG. 39 will be described with reference to FIG.

  A read cycle for reading data includes a first cycle Read # 1 and a second cycle Read # 2. These cycles Read # 1 and Read # 2 are the same as the internal read cycle in the second embodiment. In the first cycle Read # 1, storage data is read and latched and fixed value data is written. In two cycles Read # 2, reading of the written fixed value data and comparison with the stored data, generation of internal data based on the comparison result, and rewriting (restoration) of the internal data to the original memory cell are executed. Is done.

  Data read instruction is applied in cycle C # 1 of clock signal CLK, and access cycle # 1 starts. At this time, address signal Add # 1 is applied, upper data enable signal UPE is set in an active state, upper block control circuit 316a shown in FIG. 39 is activated, and reading of 16-bit data in memory cell array 300a is performed. Executed according to the self-reference method.

  Read instruction is again applied at the next clock signal C # 2, and address Add # 2 is applied. Data writing is performed in units of 32 bits, and these addresses Add # 1 and Add # 2 are the same address in order to correspond to the address at the time of writing.

  In clock cycle # 2, lower data enable signal LWE is set to an active state, lower block control circuit 316b shown in FIG. 39 is activated, and 16-bit data is read from memory cell array 300b. In cycle C # 2 of clock signal CLK, internal read cycles Read # 1 and Read # 2 are executed under the control of upper block control circuit 316a, and 16-bit internal read data QF is applied to main read data bus MRB. # 1 is output, and then 16-bit data Q # 1 is output via data output circuit 326. In accordance with internal read data QF # 1 read on main read data bus MRB in clock cycle C # 2, write data generating circuit 311a shown in FIG. 39 generates write data and stores it in the original memory cell. Rewrite bit data.

  In access cycle # 3, upper data enable signal UPE is activated again, upper block control circuit 316a is activated again in accordance with address signal Add # 3, and 16-bit data is read from memory cell array 300a. In clock cycle C # 3, 16-bit data QF # 2 read from memory cell array 300b in access cycle # 2 is transmitted to main read data bus MRB. Subsequently, external 16-bit data Q # 2 is transmitted. The data is output via the data output circuit 326.

  In clock cycle C # 4, a data read instruction is applied again, and address signal Add # 4 is applied. At this time, lower data enable signal LWE is set to an active state of H level, and in access cycle # 4, lower block control circuit 316b is activated again and 16-bit data is read from memory cell array 300b. .

  Therefore, when one clock cycle period of clock signal CLK is assigned to internal data read cycles Read # 1 and Read # 1, these first and second cycles Read # 1 and Read # 2 are Overlapping between different access cycles can be executed in parallel, and after the read latency (2 clock cycles), external data Q can be transferred 16 bits at each clock cycle, improving data transfer efficiency Can do.

  Instead of the bank address signal, a data activation signal UPEN and a lower data activation signal LWEN are used. As the configuration of the peripheral circuit in the magnetic memory device shown in FIG. 39, the magnetic memory shown in FIG. The same circuit configuration as that of the apparatus can be used.

[Example of change]
FIG. 41 shows a structure of a main part of a modification of the fourth embodiment of the present invention. In the configuration shown in FIG. 41, upper data activation signal UPEN and lower data activation signal LWEN are sequentially switched in accordance with read mode designating signal RE. More specifically, upper / lower data activation signal generating portion receives complementary output / Q at input D, and takes in and outputs the signal applied to input D in accordance with inactivation of read mode designating signal RE. AND circuit 342 receiving output signal of D flip-flop 340 and read mode designating signal RE, AND circuit 344 receiving signal of read mode designating signal RE and the complementary output / Q of D flip flop 340, An OR circuit 346 that receives the output signal of AND circuit 342 and write mode designation signal WE and generates lower data activation signal LWEN, and receives the upper signal of write mode designation signal WE and the output signal of AND circuit 344 OR circuit 348 for generating activation signal UPEN.

  Upper data activation signal UPEN and lower data activation signal LWEN are applied to upper block control circuit 316a and lower block control circuit 316b shown in FIG. 39, respectively.

  FIG. 42 is a timing chart showing the operation of the circuit shown in FIG. The operation of the circuit shown in FIG. 41 will be described below with reference to FIG.

  At the time of data reading, write mode detection signal WE is at L level. At the time of initialization, D flip-flop 340 is reset according to reset signal RST, so that the signal from output Q is at L level and the signal from complementary output / Q is at H level. The reset signal RST is activated when the system is reset or when the power is turned on.

  When read mode designating signal RE is activated, since the signal from complementary output / Q is at H level, the output signal of AND circuit 344 becomes H level, and upper data activation signal UPEN is activated. Is done. The signal of output Q is at L level, and lower data activation signal LWEN is at L level. When read mode designating signal RE is deactivated, a signal applied to input D is taken into D flip-flop 340 and its output state changes.

  Therefore, when read mode designating signal RE is next applied, the signal of output Q is at H level and lower data activation signal LWEN is at H level. Since the signal from complementary output / Q is at L level, upper data activation signal UPEN is at L level. When read mode designating signal RE is deactivated, the output state of D flip-flop 340 changes.

  At the time of data writing, read mode designation signal RE is at L level, and both upper data activation signal UPEN and lower data activation signal LWEN are activated in accordance with write mode designation signal WE. Therefore, 32-bit data is written at the time of data writing, and 16-bit upper data and 16-bit lower data can be sequentially read at the time of data reading. In the configuration shown in FIG. 41, the external processing device is not required to designate upper data / lower data at the time of data reading and data writing. At the time of data reading, it is only required to continuously give the same address for two clock cycles, and control at the time of access becomes easy.

  The bit width of data at the time of data reading and the bit width of data at the time of data writing may be appropriately determined according to the number of clock cycles required for internal data reading. 16-bit read data and 32-bit write It is not limited to embedded data. The IO separation configuration in which the data input node and the data output node are separately provided, and the output data bit width being smaller than the input data bit width are only required at a minimum.

  As described above, according to the fourth embodiment of the present invention, when reading data, data having a bit width smaller than that of write data is internally read out and output, and the data read cycle time is long. Even in this case, read data can be transferred at high speed.

  In the second to fourth embodiments, memory cell data is read by the self-reference method. However, in the magnetic memory device that reads data based on the read current from the memory cell itself or based on comparison with the reference data from the dummy cell, it is shown in the second to fourth embodiments. The configuration to be applied is applicable. The entire internal data read cycles Read # 1 and Read # 2 are made one read cycle, and the data read operation is executed in a pipeline manner so that data can be read at high speed even when the read cycle is long. Can do.

  The present invention can be applied as a non-volatile semiconductor memory device capable of transferring data at high speed in applications such as portable devices that are required to process a large amount of data such as image / audio data at high speed.

  1 memory cell array, 2 main control circuit, 3 address input circuit, 4 word line drive circuit, 5 digit line drive circuit, 6 read column selection circuit, 7 source line drive circuit, 8 bit line drive circuit, 9 write column selection circuit 10 internal readout circuit, 11 input / output circuit, BDR, BDR0-BDR3, BDL, BDL0-BDL3 bit line driver, SLDR0, SLDR1, SLDR source line driver, WDR, WDR0, WDR1 word line driver, DLDR0, DLDR1 digit line driver , RCG0, RCG1 Read column selection gate, 27 Write mode detection circuit, 28 Write activation circuit, 29 Read mode detection circuit, 30 Read column activation circuit, 31 Word line activation circuit, 100a, 100b Memory cell array, 102a , 102b Address latch circuit 104a, 104b row selection circuit, 106a, 106b word / digit line drive circuit, 108a, 108b write column selection circuit, 110a, 110b bit line drive circuit, 112a, 112b read column selection circuit, 114a, 114b internal read circuit, 111a, 111b Write data generation circuit, 126 data output circuit, 128 data input circuit, 120 main control circuit, 200 memory cell array, 202 address input circuit, 204 row selection drive circuit, 206 column selection circuit, 208 write circuit, 210 Internal read circuit, 212 parallel-serial conversion circuit, 214 data output circuit, 218 main control circuit, 220 read control circuit, 300a, 300b memory cell array, 316a upper block control circuit, 316b lower block control circuit, 320 input latch circuit .

Claims (5)

A memory cell array including a plurality of memory cells having variable resistance elements arranged in a matrix and each having a resistance value set according to stored data;
Column selection means for selecting a memory cell column of the memory cell array according to a column address signal;
The number of bits is smaller than that of the column according to the storage data of the selected memory cell and the fixed value data written to and read from the selected memory cell, coupled to the memory cell selected by the column selection means of the memory cell array An internal read circuit for generating internal read data;
At the time of data reading, after the storage data of the selected memory cell of the memory cell array is read to the internal reading circuit, the fixed value data is written to the selected memory cell, and the memory cell to which the fixed value data has been written is A read control circuit coupled to the read circuit;
An output circuit for generating external read data in accordance with internal read data from the internal read circuit and outputting the external read data; and
An output control circuit that activates the output circuit in accordance with a read mode instruction signal, wherein the output control circuit includes the output circuit so that an internal data read generation operation period of the internal read circuit overlaps at least a part of the operation period; Activated magnetic storage device.   2. The magnetic memory device according to claim 1, wherein the internal read data generated by the internal read circuit and the external data output by the output circuit have different numbers of bits.   2. The magnetic memory device according to claim 1, wherein the external data output from the output circuit is different in number of bits from externally applied write data. The internal readout circuit is divided into two sub-circuits;
The magnetic memory device according to claim 1, wherein the read control circuit activates the sub-circuit in an interleaved manner. An internal data bus,
5. The magnetic memory device according to claim 4, wherein the two sub-circuits are coupled to different bus line groups of the internal data bus.

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